WO2014079708A1 - Verfahren zum vereinzeln eines verbundes in halbleiterchips und halbleiterchip - Google Patents
Verfahren zum vereinzeln eines verbundes in halbleiterchips und halbleiterchip Download PDFInfo
- Publication number
- WO2014079708A1 WO2014079708A1 PCT/EP2013/073394 EP2013073394W WO2014079708A1 WO 2014079708 A1 WO2014079708 A1 WO 2014079708A1 EP 2013073394 W EP2013073394 W EP 2013073394W WO 2014079708 A1 WO2014079708 A1 WO 2014079708A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- composite
- semiconductor
- metallic layer
- carrier
- semiconductor chip
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 134
- 238000000034 method Methods 0.000 title claims abstract description 60
- 239000002131 composite material Substances 0.000 claims description 68
- 238000000926 separation method Methods 0.000 claims description 40
- CURLTUGMZLYLDI-UHFFFAOYSA-N Carbon dioxide Chemical compound O=C=O CURLTUGMZLYLDI-UHFFFAOYSA-N 0.000 claims description 8
- 238000005422 blasting Methods 0.000 claims description 8
- 239000007788 liquid Substances 0.000 claims description 5
- 229910002092 carbon dioxide Inorganic materials 0.000 claims description 4
- 238000001311 chemical methods and process Methods 0.000 claims description 4
- 239000001569 carbon dioxide Substances 0.000 claims description 3
- 239000003795 chemical substances by application Substances 0.000 claims description 3
- 238000002955 isolation Methods 0.000 claims description 3
- 230000000694 effects Effects 0.000 claims description 2
- 238000011068 loading method Methods 0.000 abstract description 5
- 239000000463 material Substances 0.000 description 19
- 230000005855 radiation Effects 0.000 description 13
- 230000015572 biosynthetic process Effects 0.000 description 9
- 239000000758 substrate Substances 0.000 description 5
- 238000004519 manufacturing process Methods 0.000 description 4
- 238000003486 chemical etching Methods 0.000 description 3
- 150000001875 compounds Chemical class 0.000 description 3
- 239000011888 foil Substances 0.000 description 3
- 239000007789 gas Substances 0.000 description 3
- 230000001939 inductive effect Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 3
- JBRZTFJDHDCESZ-UHFFFAOYSA-N AsGa Chemical compound [As]#[Ga] JBRZTFJDHDCESZ-UHFFFAOYSA-N 0.000 description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 229910005540 GaP Inorganic materials 0.000 description 2
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 2
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 235000011089 carbon dioxide Nutrition 0.000 description 2
- HZXMRANICFIONG-UHFFFAOYSA-N gallium phosphide Chemical compound [Ga]#P HZXMRANICFIONG-UHFFFAOYSA-N 0.000 description 2
- 229910052732 germanium Inorganic materials 0.000 description 2
- GNPVGFCGXDBREM-UHFFFAOYSA-N germanium atom Chemical compound [Ge] GNPVGFCGXDBREM-UHFFFAOYSA-N 0.000 description 2
- 230000001788 irregular Effects 0.000 description 2
- 238000002488 metal-organic chemical vapour deposition Methods 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 230000009897 systematic effect Effects 0.000 description 2
- 238000009623 Bosch process Methods 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000005540 biological transmission Effects 0.000 description 1
- 239000007767 bonding agent Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 239000002800 charge carrier Substances 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 229940125904 compound 1 Drugs 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000006378 damage Effects 0.000 description 1
- 238000000708 deep reactive-ion etching Methods 0.000 description 1
- 230000001419 dependent effect Effects 0.000 description 1
- 239000003989 dielectric material Substances 0.000 description 1
- 239000012153 distilled water Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- JEGUKCSWCFPDGT-UHFFFAOYSA-N h2o hydrate Chemical compound O.O JEGUKCSWCFPDGT-UHFFFAOYSA-N 0.000 description 1
- 238000004020 luminiscence type Methods 0.000 description 1
- 239000011159 matrix material Substances 0.000 description 1
- 229910001092 metal group alloy Inorganic materials 0.000 description 1
- 150000002739 metals Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 238000001020 plasma etching Methods 0.000 description 1
- 229910052697 platinum Inorganic materials 0.000 description 1
- 239000010970 precious metal Substances 0.000 description 1
- 238000002310 reflectometry Methods 0.000 description 1
- 229910052703 rhodium Inorganic materials 0.000 description 1
- 239000010948 rhodium Substances 0.000 description 1
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 1
- 229910052594 sapphire Inorganic materials 0.000 description 1
- 239000010980 sapphire Substances 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 230000003595 spectral effect Effects 0.000 description 1
- 238000000992 sputter etching Methods 0.000 description 1
- 238000002604 ultrasonography Methods 0.000 description 1
- 235000012431 wafers Nutrition 0.000 description 1
- 238000003631 wet chemical etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0095—Post-treatment of devices, e.g. annealing, recrystallisation or short-circuit elimination
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0016—Processes relating to electrodes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
- H01L2933/0058—Processes relating to semiconductor body packages relating to optical field-shaping elements
Definitions
- the method relates to a method for separating a composite into a plurality of semiconductor chips and such a semiconductor chip.
- various methods are known in which the
- Substrate material is severed.
- many separation processes are for the different occurring materials, such as semiconductor material, metals or
- One object is to provide a separating method that is simplistic and reliable to carry out. Furthermore, a semiconductor chip is to be specified, which can be produced in a simplified manner. These objects are achieved inter alia by a method or a semiconductor chip according to the independent patent claims. Embodiments and expediencies are the subject of the dependent claims. In accordance with at least one embodiment of the method for separating a composite into a plurality of
- Semiconductor chips are provided a composite.
- the composite extends in a vertical direction between a first major surface and a second major surface.
- the composite has a carrier.
- the carrier contains
- a semiconductor material such as silicon
- the carrier may be electrically conductive or electrically insulating.
- the composite has a semiconductor layer sequence.
- Semiconductor layer sequence is epitaxial, for example, deposited by means of MOCVD or MBE.
- Semiconductor layer sequence may be arranged on the carrier or on a growth substrate different from the carrier.
- the semiconductor layer sequence contains an active region intended for generating radiation and / or for receiving radiation.
- the semiconductor layer sequence contains a III-V compound semiconductor material.
- III-V compound semiconductor materials are for generating radiation in the
- Al x In y Gai x - y N in particular for blue to green radiation
- Al x In y Gai x - y P in particular for yellow to red
- the composite has a metallic layer.
- the metallic layer may be single-layered or multi-layered.
- the metallic layer is electrically conductively connected to the semiconductor layer sequence.
- the metallic layer can furthermore be used as a mirror layer for the layers to be produced or added in the semiconductor layer sequence
- the reflectivity for this radiation is at least 60%.
- separation trenches are formed in the support.
- the side surfaces of the separation trenches in particular form the lateral surfaces delimiting the semiconductor chip in the lateral direction. In particular, this is done
- a lateral direction is understood to mean a direction along a main plane of extension of the
- Semiconductor layers of the semiconductor layer sequence extends.
- the mesa trenches define the individual semiconductor bodies which, when the composite is singulated in
- the mesa trenches extend completely through the semiconductor layer sequence.
- the semiconductor layer sequence is already severed during the formation of the separation trenches.
- Separation trenches in particular along the mesa trenches. According to an alternative embodiment variant, when forming the separation trenches in the carrier and the
- Semiconductor layer sequence at least partially severed.
- the individual semiconductor body and carrier body of the later separated semiconductor chips are thus defined in a common manufacturing step.
- the separation trenches are formed by means of a chemical process
- the trenches are formed by means of a plasma separation method, for example by means of reactive deep ion etching (DRIE). This process is also called “Bosch process"
- DRIE reactive deep ion etching
- the separation trenches extend completely through the support.
- the composite is held together only over the metallic layer.
- the composite is subjected to a mechanical load so that the metallic layer breaks along the separation trenches and the composite is separated into semiconductor chips.
- semiconductor chips each have a part of the Semiconductor layer sequence, the carrier and the metallic layer.
- the mechanical loading takes place by means of a pressure effect on the composite in an oblique or perpendicular to one
- an abrasive method such as sawing is not considered to be a method in which a bond breaks due to mechanical stress.
- the mechanical load is a liquid jet or a
- a compressed air blasting method is suitable in which carbon dioxide is used as blasting agent, for example CO 2 snow blasting or dry ice blasting.
- a composite comprising a carrier, a carrier, a carrier
- Fracture edge at which the metallic layer is broken is characterized by an irregular structure.
- the process is characterized by low yield losses. Furthermore, precious metals used in the manufacturing process
- the metal layer extends over the composite over its entire area before mechanical stress is applied to the composite. This means that the metallic layer is completely unstructured in the lateral direction. In particular, after forming the separation trenches in the support
- adjacent semiconductor chips in each case mechanically connected to one another via the metallic layer.
- the composite can on a
- Subcarrier be arranged.
- a subcarrier for example, a film, a rigid support or a suitable
- the composite is attached to an auxiliary carrier prior to singulation, and the semiconductor chips lie on the latter after singulation
- the semiconductor chips are present in an ordered structure, for example a matrix-like arrangement.
- the semiconductor layer sequence is attached to the auxiliary carrier after the formation of the separation trenches on the side of the composite from which the separation trenches are introduced into the carrier.
- the composite can be transferred from a first auxiliary carrier, on which the formation of the separating trenches takes place, to a second auxiliary carrier, on which the mechanical load is exerted.
- Subcarrier as, for example, first, second or third subcarrier is for convenience of description only and does not necessarily imply an order of use of the subcarrier.
- Each of these auxiliary carriers can have at least one of the above-described features of the auxiliary carrier.
- the composite is subjected to a mechanical
- a semiconductor chip has according to at least one
- Embodiment a semiconductor body, a support body and a metallic layer, which are arranged in a vertical direction to each other.
- the metallic layer has a breaking edge on at least one side surface of the semiconductor chip.
- the metallic layer delimits the semiconductor chip in a vertical direction on a side of the carrier body facing away from the semiconductor body.
- the metallic layer delimits the semiconductor chip in a vertical direction on a side of the carrier body facing away from the semiconductor body.
- Layer form a back contact for the semiconductor chip.
- the metallic layer is arranged between the carrier body and the semiconductor body.
- connection partners by means of atomic and / or molecular forces
- a cohesive connection can be achieved for example by means of a bonding agent, such as an adhesive or a solder.
- a bonding agent such as an adhesive or a solder.
- the method described above for separating a composite into semiconductor chips is particularly suitable for the production of the semiconductor chip. Therefore, features described in connection with the method can also be used for the semiconductor chip and vice versa.
- Figures 1A to IE a first embodiment of a
- Figures 3A and 3B each show an embodiment of a
- FIG. 3C is a photograph of a scattered one
- a composite 1 is provided that extends in a vertical direction between a first main surface 11 and a second main surface 12.
- the composite 1 has a in this embodiment
- Carrier 4 a semiconductor layer sequence 2 and a
- the metallic layer 3 is arranged on the side facing away from the semiconductor layer sequence 2 of the carrier.
- the carrier 4 contains, for example, a semiconductor material, such as silicon, germanium, gallium phosphide or gallium arsenide or consists of such a material.
- the carrier may for example contain sapphire or consist of such a material.
- the semiconductor layer sequence 2 is preferably deposited epitaxially, for example by means of MBE or MOCVD.
- the semiconductor layer sequence is particularly suitable one of the aforementioned III-V compound semiconductor materials.
- semiconductor layer sequence 2 are for simplified illustration not explicitly shown.
- mesa trenches 21 are formed, which are the semiconductor layer sequence 2
- Semiconductor layer sequence 2 each divide into separate semiconductor body 20.
- the mesa trenches can be formed, for example, by wet-chemical or dry-chemical etching.
- the metallic layer 3 may be single-layered or
- the metallic layer may be gold, aluminum, silver, platinum,
- the metallic layer 3 preferably has a thickness of between 100 nm and 10 ⁇ inclusive.
- the carrier 4 is, as shown in Figure 1B, means
- the formation of the separation trenches 45 is preferably carried out by means of a chemical process, in particular by means of a dry chemical process.
- a plasma separation method for example reactive ion etching, has proved to be particularly suitable, in particular for a support 4 based on silicon.
- reactive ion deep etching separation trenches with a high aspect ratio, ie with a large ratio of the depth of the trenches to the width of the trenches, can be produced easily and reliably.
- the formation of the separation trenches 45 takes place in the region of the mesa trenches 21
- Forming the separation trenches is thus removed only material of the carrier.
- Semiconductor layer sequence 2 is not yet or at least not completely subdivided into individual semiconductor bodies before forming the isolation trenches 45. In this case, the formation of the separation trenches takes place through the semiconductor layer sequence 2 and the carrier 4.
- Main surface 11 ago On the first major surface 11 opposite second major surface 12 of the composite 1 is attached to a first auxiliary carrier 51.
- the first auxiliary carrier 51 On the first major surface 11 opposite second major surface 12 of the composite 1 is attached to a first auxiliary carrier 51.
- Subcarrier 51 may be, for example, a flexible carrier, such as a foil, or a rigid carrier.
- the carrier bodies 40 are still mechanically stable connected to one another via the metallic layer 3.
- the stability of the relative position of the individual carrier body 40 is ensured simplified over the metallic layer 3.
- the composite 1 is still held together by a layer which remains in the singulated and finished semiconductor chips.
- the composite 1 is transferred from the first auxiliary carrier 51 to a second auxiliary carrier 52 transfer.
- the compound 1 is now on the part of the first
- the carrier bodies 40 are each between the metallic layer 3 and the second
- Subcarrier 52 is arranged.
- the transfer to the second auxiliary carrier 52 can take place such that the composite 1 is subjected to a mechanical stress in the lateral direction, for example a tensile stress or compressive stress.
- the composite is already pre-tensioned with a mechanical load, for example by expanding the auxiliary carrier designed as a foil.
- the isolation can be supported.
- biasing can also be dispensed with.
- the composite 1, in particular the metallic layer 3, is acted upon by the second main surface 12 by means of a mechanical load.
- a mechanical load for example, a liquid jet 80 is suitable as a liquid is particularly suitable water or distilled water.
- the liquid jet can be exerted permanently or pulsating on the composite 1.
- a gas jet at a sufficiently high pressure such as compressed air, nitrogen or a
- Blasting agents for example C02 snow blasting or
- Dry ice blasting is suitable to make a a break
- the frequency is suitably adapted to the material and geometry conditions of the composite. 1
- an ultrasonicated high-pressure water jet for example, an ultrasonicated high-pressure water jet.
- the mechanical load is beyond the load limit of the metallic layer, so that the metallic
- the semiconductor chips 10 lie on the second auxiliary carrier 52 for further processing
- the semiconductor chips 10 are present in such a way that the first main surface 11 is arranged on the side facing away from the third subcarrier 53.
- Semiconductor body 20 is thus arranged on the side facing away from the third auxiliary carrier side of the carrier 4.
- a completed semiconductor chip 10 is shown schematically in a sectional view in FIG. 3A.
- the semiconductor chip 10 has a carrier body 40, a semiconductor body 20 with a semiconductor layer sequence and a metallic layer 3. In the lateral direction, the semiconductor chip 10 is bounded by side surfaces 110.
- the metallic layer 3 forms a backside contact 71 of the semiconductor chip.
- Contacts 71, 72 charge carriers are injected from different sides in the active region of the semiconductor chip 20 and recombine there under the emission of radiation.
- the semiconductor chip may, for example, as a
- Luminescence diode such as a laser diode or a light emitting diode, be formed.
- the carrier body 40 can emerge from a growth substrate for the semiconductor layer sequence of the semiconductor body 20 or from a carrier different from the growth substrate.
- the metallic layer 3 has respective break edges 8.
- a photographic view of the isolated composite is shown in FIG. 3C. Here is the irregular, caused by the fracture structure of the breaking edge 8 clearly visible.
- a composite 1 is provided, in which the metallic layer 3 is arranged between the carrier 4 and the semiconductor layer sequence 2.
- the metallic layer 3 has one of the semiconductor layer sequences
- connection layer can, for example, a
- the carrier is by means of
- the carrier is therefore not the growth substrate for the
- Metallic layer is structured in a lateral direction in separate metal surfaces.
- separating trenches 45 are formed. This can be done as described in connection with FIG. 2B.
- Semiconductor layer sequence 2 and the carrier 4 is located.
- the transfer from the first subcarrier 51 to the second subcarrier 52 and the loading of the composite with a mechanical load, shown in FIGS. 2C and 2D, can be carried out as described in connection with the first exemplary embodiment.
- the isolated semiconductor chips 10 are, as shown in Figure 2E, on the second subcarrier 52 to the other
- the thus-finished semiconductor chip 10 is shown schematically in a sectional view in FIG. 3B.
- FIG. 3B In contrast to the semiconductor chip 10 shown in FIG. 3A, FIG. 3B
- Layer 6 forms the rear-side contact 71.
- the semiconductor chips may also be two
- the semiconductor body 20 may be arranged one or more further layers, for example a
- Passivation layer such as an oxide layer or a
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Dicing (AREA)
- Recrystallisation Techniques (AREA)
- Led Devices (AREA)
- Drying Of Semiconductors (AREA)
Abstract
Description
Claims
Priority Applications (7)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
CN201380061117.4A CN104781939B (zh) | 2012-11-23 | 2013-11-08 | 用于将复合体分割成半导体芯片的方法和半导体芯片 |
KR1020157013296A KR102182873B1 (ko) | 2012-11-23 | 2013-11-08 | 집합체를 반도체 칩으로 분리하는 방법 및 반도체 칩 |
CN201811229024.9A CN109390282B (zh) | 2012-11-23 | 2013-11-08 | 用于将复合体分割成半导体芯片的方法和半导体芯片 |
DE112013005634.8T DE112013005634B4 (de) | 2012-11-23 | 2013-11-08 | Verfahren zum Vereinzeln eines Verbundes in Halbleiterchips und Halbleiterchip |
JP2015543381A JP6149120B2 (ja) | 2012-11-23 | 2013-11-08 | 集合体を半導体チップに個片化する方法および半導体チップ |
US14/647,071 US9728459B2 (en) | 2012-11-23 | 2013-11-08 | Method for singulating an assemblage into semiconductor chips, and semiconductor chip |
US15/670,968 US20180047628A1 (en) | 2012-11-23 | 2017-08-07 | Method for singulating an assemblage into semiconductor chips, and semiconductor chip |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE102012111358.0A DE102012111358A1 (de) | 2012-11-23 | 2012-11-23 | Verfahren zum Vereinzeln eines Verbundes in Halbleiterchips und Halbleiterchip |
DE102012111358.0 | 2012-11-23 |
Related Child Applications (2)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
US14/647,071 A-371-Of-International US9728459B2 (en) | 2012-11-23 | 2013-11-08 | Method for singulating an assemblage into semiconductor chips, and semiconductor chip |
US15/670,968 Continuation US20180047628A1 (en) | 2012-11-23 | 2017-08-07 | Method for singulating an assemblage into semiconductor chips, and semiconductor chip |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2014079708A1 true WO2014079708A1 (de) | 2014-05-30 |
Family
ID=49578283
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2013/073394 WO2014079708A1 (de) | 2012-11-23 | 2013-11-08 | Verfahren zum vereinzeln eines verbundes in halbleiterchips und halbleiterchip |
Country Status (6)
Country | Link |
---|---|
US (2) | US9728459B2 (de) |
JP (2) | JP6149120B2 (de) |
KR (1) | KR102182873B1 (de) |
CN (2) | CN109390282B (de) |
DE (2) | DE102012111358A1 (de) |
WO (1) | WO2014079708A1 (de) |
Cited By (6)
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CN105609555A (zh) * | 2014-11-14 | 2016-05-25 | 株式会社东芝 | 包含膜的装置及其制造方法 |
JP2016096266A (ja) * | 2014-11-14 | 2016-05-26 | 株式会社東芝 | デバイスの製造方法 |
JP2016103622A (ja) * | 2014-11-14 | 2016-06-02 | 株式会社東芝 | デバイスの製造方法及びデバイス |
JP2016134433A (ja) * | 2015-01-16 | 2016-07-25 | 株式会社東芝 | ダイシング装置 |
JP2017055012A (ja) * | 2015-09-11 | 2017-03-16 | 株式会社東芝 | デバイスの製造方法 |
US9947571B2 (en) | 2014-11-14 | 2018-04-17 | Kabushiki Kaisha Toshiba | Processing apparatus, nozzle, and dicing apparatus |
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Publication number | Priority date | Publication date | Assignee | Title |
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DE102012111358A1 (de) * | 2012-11-23 | 2014-05-28 | Osram Opto Semiconductors Gmbh | Verfahren zum Vereinzeln eines Verbundes in Halbleiterchips und Halbleiterchip |
DE102015102458B4 (de) * | 2015-02-20 | 2024-04-25 | OSRAM Opto Semiconductors Gesellschaft mit beschränkter Haftung | Verfahren zur Herstellung einer Mehrzahl von Halbleiterchips |
JP6689154B2 (ja) * | 2016-07-26 | 2020-04-28 | 株式会社ディスコ | デバイスウエーハの加工方法 |
JP6684182B2 (ja) * | 2016-08-08 | 2020-04-22 | 株式会社ディスコ | デバイスウエーハの加工方法 |
JP6684183B2 (ja) * | 2016-08-08 | 2020-04-22 | 株式会社ディスコ | デバイスウエーハの加工方法 |
TW201812887A (zh) * | 2016-09-23 | 2018-04-01 | 頎邦科技股份有限公司 | 晶圓切割方法 |
JP2018160577A (ja) * | 2017-03-23 | 2018-10-11 | 株式会社ディスコ | 加工方法 |
CN113255273B (zh) * | 2021-06-07 | 2021-10-01 | 上海国微思尔芯技术股份有限公司 | 分割及验证方法、装置、电子设备、存储介质 |
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WO2008019377A2 (en) * | 2006-08-07 | 2008-02-14 | Semi-Photonics Co., Ltd. | Method of separating semiconductor dies |
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Also Published As
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DE112013005634A5 (de) | 2015-08-20 |
US20180047628A1 (en) | 2018-02-15 |
KR102182873B1 (ko) | 2020-11-25 |
JP6149120B2 (ja) | 2017-06-14 |
KR20150087243A (ko) | 2015-07-29 |
CN109390282A (zh) | 2019-02-26 |
DE112013005634B4 (de) | 2021-10-14 |
JP2017139477A (ja) | 2017-08-10 |
CN104781939A (zh) | 2015-07-15 |
JP2016501444A (ja) | 2016-01-18 |
DE102012111358A1 (de) | 2014-05-28 |
CN109390282B (zh) | 2023-07-25 |
JP6431112B2 (ja) | 2018-11-28 |
CN104781939B (zh) | 2018-11-09 |
US9728459B2 (en) | 2017-08-08 |
US20150303112A1 (en) | 2015-10-22 |
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