WO2013168352A1 - 実装構造体とその製造方法 - Google Patents

実装構造体とその製造方法 Download PDF

Info

Publication number
WO2013168352A1
WO2013168352A1 PCT/JP2013/002354 JP2013002354W WO2013168352A1 WO 2013168352 A1 WO2013168352 A1 WO 2013168352A1 JP 2013002354 W JP2013002354 W JP 2013002354W WO 2013168352 A1 WO2013168352 A1 WO 2013168352A1
Authority
WO
WIPO (PCT)
Prior art keywords
resin
mounting structure
bump
electrode
circuit board
Prior art date
Application number
PCT/JP2013/002354
Other languages
English (en)
French (fr)
Inventor
新 岸
宏典 宗像
本村 耕治
弘樹 圓尾
Original Assignee
パナソニック株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by パナソニック株式会社 filed Critical パナソニック株式会社
Priority to EP13787864.1A priority Critical patent/EP2849216B1/en
Priority to JP2014514363A priority patent/JP6365841B2/ja
Priority to US14/396,297 priority patent/US9795036B2/en
Priority to CN201380018441.8A priority patent/CN104246997B/zh
Priority to KR1020147024643A priority patent/KR101975076B1/ko
Publication of WO2013168352A1 publication Critical patent/WO2013168352A1/ja
Priority to US15/699,570 priority patent/US10412834B2/en

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00Printed circuits
    • H05K1/18Printed circuits structurally associated with non-printed electric components
    • H05K1/181Printed circuits structurally associated with non-printed electric components associated with surface mounted components
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/48Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/73Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92Specific sequence of method steps
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/303Surface mounted components, e.g. affixing before soldering, aligning means, spacing means
    • H05K3/305Affixing by adhesive
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3463Solder compositions in relation to features of the printed circuit board or the mounting process
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/1012Auxiliary members for bump connectors, e.g. spacers
    • H01L2224/10152Auxiliary members for bump connectors, e.g. spacers being formed on an item to be connected not being a semiconductor or solid-state body
    • H01L2224/10155Reinforcing structures
    • H01L2224/10156Bump collar
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16238Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area protruding from the surface of the item
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29199Material of the matrix
    • H01L2224/2929Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L2224/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • H01L2224/29001Core members of the layer connector
    • H01L2224/29099Material
    • H01L2224/29198Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/29298Fillers
    • H01L2224/29299Base material
    • H01L2224/293Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32052Shape in top view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/3205Shape
    • H01L2224/32057Shape in side view
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321Disposition
    • H01L2224/32151Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32225Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81052Detaching bump connectors, e.g. after testing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119Arrangement of the bump connectors prior to mounting
    • H01L2224/81191Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81499Material of the matrix
    • H01L2224/8159Material of the matrix with a principal constituent of the material being a polymer, e.g. polyester, phenolic based polymer, epoxy
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598Fillers
    • H01L2224/81599Base material
    • H01L2224/816Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81601Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81609Indium [In] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598Fillers
    • H01L2224/81599Base material
    • H01L2224/816Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81601Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81611Tin [Sn] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598Fillers
    • H01L2224/81599Base material
    • H01L2224/816Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81601Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/81613Bismuth [Bi] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598Fillers
    • H01L2224/81599Base material
    • H01L2224/816Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81638Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81639Silver [Ag] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8138Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/81399Material
    • H01L2224/81498Material with a principal constituent of the material being a combination of two or more materials in the form of a matrix with a filler, i.e. being a hybrid material, e.g. segmented structures, foams
    • H01L2224/81598Fillers
    • H01L2224/81599Base material
    • H01L2224/816Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/81638Base material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/81647Copper [Cu] as principal constituent
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying
    • H01L2224/81815Reflow soldering
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/8193Reshaping
    • H01L2224/81935Reshaping by heating means, e.g. reflowing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81909Post-treatment of the bump connector or bonding area
    • H01L2224/81951Forming additional members, e.g. for reinforcing
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81986Specific sequence of steps, e.g. repetition of manufacturing steps, time sequence
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/831Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus
    • H01L2224/83104Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector the layer connector being supplied to the parts to be connected in the bonding apparatus by applying pressure, e.g. by injection
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8319Arrangement of the layer connectors prior to mounting
    • H01L2224/83192Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9211Parallel connecting processes
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10Bump connectors ; Manufacturing methods related thereto
    • H01L24/12Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/28Structure, shape, material or disposition of the layer connectors prior to the connecting process
    • H01L24/29Structure, shape, material or disposition of the layer connectors prior to the connecting process of an individual layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/00014Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0132Binary Alloys
    • H01L2924/01322Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/0133Ternary Alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/013Alloys
    • H01L2924/014Solder alloys
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30Technical effects
    • H01L2924/38Effects and problems related to the device integration
    • H01L2924/384Bump effects
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10621Components characterised by their electrical contacts
    • H05K2201/10734Ball grid array [BGA]; Bump grid array
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10977Encapsulated connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10992Using different connection materials, e.g. different solders, for the same connection
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2009Reinforced areas, e.g. for a specific part of a flexible printed circuit
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2036Permanent spacer or stand-off in a printed circuit or printed circuit assembly
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/20Details of printed circuits not provided for in H05K2201/01 - H05K2201/10
    • H05K2201/2045Protection against vibrations
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/3457Solder materials or compositions; Methods of application thereof
    • H05K3/3485Applying solder paste, slurry or powder
    • YGENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02PCLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a mounting structure in which a semiconductor package component is surface-mounted on a circuit board, and a manufacturing method thereof.
  • the SnAgCu solder paste 601 is printed on the second electrode 104 of the circuit board 105. Then, as shown in FIG. 6B, the bump 103 formed on the first electrode 102 of the semiconductor package 101 is mounted so as to hit the second electrode 104 via the SnAgCu solder paste 601.
  • the semiconductor package 101 having bumps formed on the lower surface thereof is used in mobile devices typified by mobile phone devices, and can withstand a drop impact as a function required for these products. Is required.
  • a countermeasure for example, when the BGA and the circuit board 105 are soldered together, an underfill 603 is provided between the semiconductor package 101 and the circuit board 105 after soldering with the SnAgCu solder 602 as shown in FIG. A method of filling and improving the drop resistance of the joint is used (Patent Document 1).
  • FIG. 7 shows a mounting structure described in Patent Document 2.
  • This mounting structure includes a semiconductor package 101 having a first electrode 102, a circuit board 105 having a second electrode 104, a bump 103 formed on the first electrode 102, and between the bump 103 and the second electrode 104.
  • a bonding member 106 that is disposed and electrically connects the first electrode 102 and the second electrode 104 through the bump 103, and a bonding portion between the bump 103 and the bonding material 106 and the periphery of each bonding member so as to cover the bonding member
  • the reinforcing resins 107 are arranged apart from each other so that the adjacent reinforcing resins 107 do not come into contact with each other.
  • the present invention solves the above-described conventional problems, and in a mounting structure in which a semiconductor package is electrically connected to a circuit board, the drop resistance characteristics of the joint can be improved, and curing when an underfill material is used.
  • An object is to provide an environment-friendly mounting structure that does not require a furnace and a method for manufacturing the same.
  • the mounting structure of the present invention is disposed between a semiconductor package having a first electrode, a circuit board having a second electrode, and a bump formed on the second electrode and the first electrode.
  • a paste in which a solder material and an uncured thermosetting resin are mixed is applied onto the second electrode on the circuit board, and the paste is mixed via the mixed paste.
  • a semiconductor package is mounted on the second electrode of the circuit board via bumps, a reinforcing resin is applied between the outer periphery of the semiconductor package and the circuit board, and the circuit board and the semiconductor package are heated.
  • a paste in which a solder material and an uncured thermosetting resin are mixed is applied onto the second electrode on the circuit board, and the semiconductor package on the circuit board is formed.
  • a reinforcing resin to the peripheral area to be mounted, mounting the semiconductor package on the second electrode of the circuit board via the bumps in the mixed paste, and heating the circuit board and the semiconductor package.
  • the solder material is separated from the thermosetting resin, and the solder material having a melting point lower than the melting point of the bump is used, so that the solder material melts and wets the bump, and then the thermosetting
  • the adhesive resin wets around the solder material and the bump, and then cures the thermosetting resin and the reinforcing resin.
  • the periphery of the bonding material is covered with the first reinforcing resin, and the outer peripheral portion of the semiconductor package and the circuit board are covered with the second reinforcing resin, whereby the drop resistance of the bonded portion is reduced.
  • the characteristics can be enhanced.
  • FIG. 1 Sectional view and (b) plan view of mounting structure in embodiment 1 of the present invention
  • FIG. 1 Sectional view and (b) plan view of mounting structure in embodiment 1 of the present invention
  • FIG. 1 Micrograph of cross section of mounting structure created under conditions of Example 1 of the same embodiment
  • Micrograph of cross section of mounting structure created under conditions of Comparative Example 2 is a manufacturing process diagram in Embodiment 2 of the present invention.
  • Sectional drawing of the mounting structure of Embodiment 3 of this invention The enlarged view of the principal part of the mounting structure of Embodiment 3 of this invention (A)-(d) is sectional drawing of the mounting structure in patent document 1
  • FIGS. 1A and 1B show a mounting structure 100 according to the first embodiment in which a semiconductor package 101 is mounted on a circuit board 105.
  • the first electrode 102 of the semiconductor package 101, the bump 103, the second electrode 104 of the circuit board 105, etc. are shown enlarged compared to the size of the semiconductor package 101.
  • the specific size of the semiconductor package 101 is, for example, ⁇ 11 mm, and the bump 103 is provided with 441 bumps at a pitch of 0.5 mm.
  • the circuit board 105 is made in accordance with the standard of JEDEC Semiconductor Technology Association (EJEDEC Solid Technology Association ⁇ ), has a length of 132mm, a width of 77mm, a thickness of 1.0mm, and the electrode material is copper.
  • the substrate material is a glass epoxy material.
  • FIG. 2A to 2D are views for explaining the manufacturing process of the mounting structure 100.
  • the mixed paste 301 is printed on the second electrode 104 of the circuit board 105.
  • the mixed paste 301 is composed of a solder material having an alloy composition composed of a combination of two or more elements selected from the group consisting of Sn and Bi, In, Ag, and Cu (which later becomes the bonding material 106) It is made of a cured thermosetting resin (which will later become the reinforcing resin 107).
  • the bump 103 formed on the first electrode 102 of the semiconductor package 101 and the mixed paste 301 printed on the circuit board 105 are brought into contact with the semiconductor package 101 on the circuit board 105. Mount.
  • a reinforcing resin 108 as a second reinforcing resin is applied by a dispenser 302 between the outer periphery of the semiconductor package 101 and the surface of the circuit board 105.
  • the mixed paste 301 and the reinforcing resin 108 are heated by using a reflow apparatus to melt the mixed paste 301, and from the mixed paste 301, the bonding material 106 and the first reinforcing resin are used.
  • the reinforcing resin 107 is separated.
  • the first electrode 102 and the second electrode 104 are coupled with the bump 103 and the bonding material 106, and the boundary between the bonding material 106 and the bump 103 is covered with the reinforcing resin 107.
  • the reinforcing resin 108 covers the outer peripheral portion of the semiconductor package 101 and forms a fillet with the circuit board 105.
  • FIG. 1A is an enlarged view of FIG.
  • the bump 103 formed on the first electrode 102 of the semiconductor package 101 and the second electrode 104 of the circuit board 105 are soldered by the melted and solidified bonding material 106 to be electrically conductive. is doing.
  • the bonding material 106 has an alloy composition having a melting point lower than that of the bump 103.
  • the periphery of the second electrode 104 of the circuit board 105 and the bump 103 are covered and joined with a reinforcing resin 107.
  • the outer peripheral portion of the semiconductor package 101 and the circuit board 105 are also joined by the reinforcing resin 108.
  • the reinforcing resin 108 connects between the semiconductor package 101 and the circuit board 105 and forms a fillet around the semiconductor package 101.
  • the reinforcing resin 108 is disposed so as to cover the outer peripheral portion of the semiconductor package 101 and the circuit board 105, but is formed on the reinforcing resin 108 and the first electrode of the semiconductor package 101.
  • the bumps 103 and the reinforcing resin 107 are arranged so as not to come into contact with each other.
  • the bonding material 106 that electrically connects the first electrode 102 and the second electrode 104 through the bump 103 is reinforced with both the reinforcing resin 107 and the reinforcing resin 108, and more specifically, the semiconductor package. 101 and the circuit board 105 are connected, and the fillet is formed of the reinforcing resin 107 around the semiconductor package, so that deformation of the circuit board 105 is suppressed even when subjected to a mechanical impact such as dropping.
  • the drop resistance of the joint can be improved as compared with the case where the joining material 106 is reinforced only with the reinforcing resin 107.
  • the bump 103 is preferably formed from a Sn-based alloy.
  • SnBi series, SnIn series, SnBiIn series, SnAg series, SnCu series, SnAgCu series, SnAgBi series, SnCuBi series, SnAgCuBi series, SnAgIn series, SnCuIn series, SnAgCuIn series, and an alloy consisting of SnAgCuBiIn series Can be used.
  • Sn-based is preferable.
  • Sn-based alloys have a low melting point of 231 ° C., are easily wetted with Cu electrodes, and are easy to make compounds with other alloys. It is also inexpensive and has low toxicity.
  • the bonding material 106 an alloy composition having a melting point lower than that of the bump 103 can be used.
  • both the bump 103 and the bonding material 106 are preferably the same system or the Sn system having the same main component.
  • the reinforcing resins 107 and 108 include a resin component as a main component and a curing agent, and optionally include a viscosity adjusting / thixotropic additive.
  • the reinforcing resin 107 is a thermosetting resin and includes various resins such as an epoxy resin, a urethane resin, an acrylic resin, a polyimide resin, a polyamide resin, a bismaleimide resin, a phenol resin, a polyester resin, a silicone resin, and an oxetane resin. be able to. These may be used alone or in combination of two or more. Of these, epoxy resins are preferred.
  • the reinforcing resin 108 is a thermosetting resin and includes various resins such as an epoxy resin, a urethane resin, an acrylic resin, a polyimide resin, a polyamide resin, a bismaleimide resin, a phenol resin, a polyester resin, a silicone resin, and an oxetane resin. be able to. These may be used alone or in combination of two or more. Of these, epoxy resins are preferred.
  • the reinforcing resin 107 and the reinforcing resin 108 are preferably the same type of resin such as an epoxy resin. Furthermore, it is preferable to change only the reaction start temperature between the two resins by changing only the curing agent to be contained with the same resin component.
  • an epoxy resin selected from the group of bisphenol type epoxy resin, polyfunctional epoxy resin, flexible epoxy resin, brominated epoxy resin, glycidyl ester type epoxy resin and polymer type epoxy resin can be used.
  • bisphenol A type epoxy resin, bisphenol F type epoxy resin, biphenyl type epoxy resin, naphthalene type epoxy resin, phenol novolac type epoxy resin, cresol novolak type epoxy resin, etc. are used. Epoxy resins obtained by modifying these are also used. These may be used alone or in combination of two or more.
  • thermosetting resin As a curing agent used in combination with the thermosetting resin as described above, a compound selected from the group of thiol compounds, amine compounds, polyfunctional phenol compounds, imidazole compounds, and acid anhydride compounds is used. Can do. These may be used alone or in combination of two or more.
  • inorganic or organic additives can be used as the viscosity adjusting / thixotropy imparting additive.
  • silica or alumina is used if it is inorganic, and if it is organic, Derivatives such as amide, polyester and castor oil are used. These may be used alone or in combination of two or more.
  • Example 2 As an example of the present invention, the type of the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed, the reinforcing resin 108, the reflow temperature is changed, and the effect of the pass / fail of the conduction and the drop resistance characteristics are examined. The results are shown in Table 1 below.
  • the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed is a bisphenol F type epoxy which is a thermosetting resin as the uncured thermosetting resin with respect to 88 parts by weight of the Sn58Bi solder. Resin (trade name “YDF-7510” manufactured by Nippon Steel Chemical Co., Ltd.) was used.
  • the viscosity modifier / thixotropic agent includes castor oil thixotropic agent (trade name “THIXCIN R” manufactured by Elementis Specialties, Inc.), an imidazole curing agent as a curing agent, and an organic acid having a flux action (“A mixture of 18 parts by weight of kneaded adipic acid (manufactured by Kanto Chemical Co., Ltd.) was used.
  • the imidazole curing agent as a curing agent was adjusted based on the following idea. In the case of preparing an uncured thermosetting resin in which the reaction start temperatures of the epoxy resin and the curing agent are 130 ° C., 140 ° C., and 155 ° C.
  • SnAgCu mixed paste 301 Sn3.0Ag0.5Cu (trade name “M705-GRN360-L60A” manufactured by Senju Metal Industry Co., Ltd.) was used.
  • semiconductor package 101 a semiconductor package mounted with Sn3.0Ag0.5Cu balls was used as the bumps 103 formed on the first electrode.
  • the melting point of Sn58Bi solder is 138 ° C.
  • the melting point of Sn3.0Ag0.5Cu solder is 217 ° C.
  • the reinforcing resin 108 is a bisphenol F type epoxy resin (trade name “YDF-7510” manufactured by Nippon Steel Chemical Co., Ltd.) for a thermosetting resin, and an imidazole curing agent capable of curing at 130 ° C. (Trade name “2MA-OK” manufactured by Shikoku Kasei Kogyo Co., Ltd.), imidazole curing agent capable of curing at 140 ° C.
  • Viscosity adjusting / thixotropy imparting additive is commonly used silica-based thixotropic agent (trade name “AEROSIL RY200” manufactured by Nippon Aerosil Co., Ltd.) did.
  • Each mounting structure was evaluated as follows. As the success or failure of conduction, the presence or absence of conduction was confirmed by a tester after the mounting structure was created. The success / failure of the continuity was indicated as “good” when the resistance value was in the range of 9.8 to 10 ⁇ , and indicated as “x” when the resistance value was out of the range.
  • the drop resistance life was evaluated. Specifically, according to the JEDEC standard, the mounting structure is dropped under the conditions of acceleration, 1500G, drop time, 0.5 seconds, and when the electrical connection is interrupted, the drop life is determined. The number of drops until occurrence was defined as the drop life. As for the judgment of pass / fail of instantaneous interruption, a voltage of 2.0 V was applied to the semiconductor package at the time of dropping, and the case where the voltage dropped by 10% or more was judged as unacceptable. The maximum number of drops at this time was 30.
  • the size of the semiconductor package used here is ⁇ 11 mm
  • the bump 103 formed on the first electrode is 0.5 mm pitch
  • the number of bumps is 441
  • the circuit board 105 is The length is 132 mm
  • the width is 77 mm
  • the thickness is 1.0 mm
  • the electrode material is copper
  • the substrate material is a glass epoxy material.
  • (Evaluation result 1: continuity test) 2 shows the results of evaluating the pass / fail of the mounting structure produced by the mounting method 1 shown in FIG. 2 under the conditions of Examples 1 to 3 and Comparative Examples 1 and 2 in Table 1.
  • Table 1 shows a mixed paste 301 in which the solder composition of the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed is Sn58Bi (melting point: 138 ° C.), and the solder material and the uncured thermosetting resin are mixed. Study the material characteristics required when creating the mounting structure of the present invention by changing the reaction start temperature of the curing agent of the uncured thermosetting resin included in 301 and the curing agent included in the reinforcing resin 108. Shows the results.
  • the mounting structure 100 was created using the mixed paste 301 in which the solder material and the uncured thermosetting resin were mixed.
  • the solder composition of the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed is Sn58Bi (solder melting point 138 ° C.), an imidazole curing agent capable of curing at 140 ° C. (trade name “2P4MHZ-PW” Shikoku Kasei Kogyo Co.
  • the mounting structure is made using the same curing agent for the reinforcing resin 108, the resistance value is 9.9 ⁇ , and electrical conductivity can be obtained with a tester. Was confirmed.
  • FIG. 3A is a photomicrograph of a cross section of the mounting structure created under the conditions of Example 1.
  • the semiconductor package 101 includes a first electrode 102, a bump 103 formed on the first electrode, a second electrode 104 formed on the circuit board 105, a bonding material 106, and a reinforcing resin 107.
  • the composition of the bump 103 formed on the first electrode at this time was Sn3.0Ag0.5Cu solder bump having a melting point of 217 ° C. Moreover, the reflow attainment temperature at the time of producing a mounting structure was 160 degreeC.
  • the reaction start temperature of the curing agent of the uncured thermosetting resin and the reinforcing resin is 140 ° C. with respect to the solder melting point of 138 ° C. of the mixed paste 301. High was found to be effective.
  • Example 2 an imidazole-based curing agent (trade name “2P4MHZ-PW” manufactured by Shikoku Kasei Kogyo Co., Ltd.) having a reaction initiation temperature higher than the melting point of Sn58Bi solder of 138 ° C. 155 ° C curing imidazole curing agent (trade name “2PHZ-PW” manufactured by Shikoku Kasei Kogyo Co., Ltd.) Solder material made with uncured thermosetting resin mixed with paste 301 or for reinforcement Even when a mounting structure was prepared using the resin 108, the same result as in Example 1 could be obtained.
  • an imidazole-based curing agent trade name “2P4MHZ-PW” manufactured by Shikoku Kasei Kogyo Co., Ltd.
  • reaction start temperature of the curing agent of the uncured thermosetting resin and the reinforcing resin 108 is higher than the solder melting point of the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed, This is important in creating the mounting structure of the present invention.
  • the reaction start temperature of the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed is imidazole capable of curing at 130 ° C. with respect to the conditions of Comparative Example 1 and the melting point 138 ° C. of the solder of the mixed paste 301.
  • Type curing agent (trade name “2MA-OK” manufactured by Shikoku Kasei Kogyo Co., Ltd.)
  • reinforcing resin 108 is an imidazole type curing agent (trade name “2P4MHZ-PW” manufactured by Shikoku Kasei Kogyo Co., Ltd.) capable of curing at 140 ° C.
  • a resistance value of 18 ⁇ was not confirmed to be conductive.
  • the difference from Example 1 is that the reaction start temperature of the curing agent of the uncured thermosetting resin is 130 ° C. and the reaction start temperature of the reinforcing resin 108 is 140 ° C. with respect to the melting point 138 ° C. of the solder. It is.
  • FIG. 3B shows a micrograph of a cross section of the mounting structure created under the conditions of Comparative Example 1.
  • the solder material included in the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed is around the bump 103 formed on the first electrode.
  • the uncured thermosetting resin wets around the bumps 103 formed on the first electrode and completes curing, so that it is found that conduction cannot be confirmed.
  • the reaction start temperature of the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed is imidazole based on the conditions of Comparative Example 2 and the melting point 138 ° C. of the solder of the mixed paste 301 corresponding to the curing at 140 ° C.
  • Curing agent (trade name “2P4MHZ-PW” manufactured by Shikoku Kasei Kogyo Co., Ltd.) with reinforcing resin 108 imidazole curing agent (trade name “2MA-OK” manufactured by Shikoku Kasei Kogyo Co., Ltd.) capable of curing at 130 ° C.
  • the difference from Example 1 is that the reaction start temperature of the curing agent of the uncured thermosetting resin is 140 ° C. and the reaction start temperature of the reinforcing resin 107 is 130 ° C. with respect to the melting point 138 ° C. of the solder. It is.
  • FIG. 3C shows a micrograph of a cross section of the mounting structure created under the conditions of Comparative Example 2.
  • an imidazole curing agent (trade name “2MA-OK”) capable of curing at 130 ° C. before the melting point (138 ° C.) of the solder material of the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed.
  • the reinforcing resin 108 made by Shikoku Kasei Kogyo Co., Ltd. was cured, and the semiconductor package 101 did not sink when the solder was melted. Therefore, the distance between the melted solder and the bump 103 formed on the first electrode is increased, and the melted solder cannot wet the bump 103 formed on the first electrode.
  • the reaction initiation temperature of the uncured thermosetting resin and the reinforcing resin is higher than the melting point of the solder material applied to the circuit board 105. Is preferable.
  • the solder material contained in the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed was melted and formed on the first electrode of the semiconductor package 101. After the solder material wets the bump 103, the uncured thermosetting resin wets around the bump 103, and the curing of the uncured thermosetting resin and the reinforcing resin starts and is completed.
  • the fact that it is useful as a process for creating a mounting structure can also be seen from the success or failure of conduction.
  • the points for creating the mounting structure of the present invention include the melting point of the bump 103 formed on the first electrode of the semiconductor package 101, the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed.
  • the relationship between the melting point of the contained solder material and the reaction start temperature of the thermosetting resin and the reinforcing resin 108 contained in the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed is as follows. desirable.
  • the reaction start temperature of the reinforcing resin 108 and the reaction start temperature of the thermosetting reinforcing resin 107) in the mixed paste 301 should be different from 5 ° C to 15 ° C. The reason is that the reinforcing resin 107 gains time for the solder bumps to wet up the bumps and a time for the reinforcing resin 107 to wet up to cover the periphery thereof. If there is too much temperature difference, heat treatment is required up to a high temperature.
  • the difference between the melting point of the solder material in the mixed paste 301 and the reaction start temperature of the two resins is, for example, 2 ° C. to 17 ° C., preferably 10 ° C. or more.
  • the reason why the temperature difference is necessary is that the solder material is melted and the self-alignment time between the semiconductor package 101 and the circuit board 105 is required.
  • the overall heat treatment temperature will be high as described above.
  • Example 1 is the mounting structure 100 shown in FIG. 1
  • Comparative Example 4 is the mounting structure shown in FIG. 6D
  • Comparative Example 3 is the mounting structure in the state shown in FIG. 6C.
  • the drop resistance test was evaluated based on the drop life. Specifically, according to the JEDEC standard, the mounting structure is dropped under the conditions of acceleration, 1500G, drop time, 0.5 seconds, and when the electrical connection is interrupted, the drop life is determined. The number of drops until occurrence was defined as the drop life. As for the judgment of pass / fail of instantaneous interruption, a voltage of 2.0 V was applied to the semiconductor package at the time of dropping, and the case where the voltage dropped by 10% or more was judged as unacceptable. The maximum number of drops at this time was 30.
  • the size of the semiconductor package used here is ⁇ 11 mm
  • the bump 103 formed on the first electrode is 0.5 mm pitch
  • the number of bumps is 441
  • the circuit board 105 is The length is 132 mm
  • the width is 77 mm
  • the thickness is 1.0 mm
  • the electrode material is copper
  • the substrate material is a glass epoxy material.
  • a mounting structure was created under the conditions of Example 1 and its drop life was evaluated.
  • the reflow attainment temperature at this time is 160 degreeC.
  • the composition of the bump 103 at this time was Sn3.0Ag0.5Cu solder bump having a melting point of 217 ° C.
  • the soldering temperature was 160 ° C. when the mounting structure was prepared, and the solder was prepared using an imidazole curing agent (trade name “2P4MHZ-PW” manufactured by Shikoku Kasei Kogyo Co., Ltd.) capable of curing at 140 ° C.
  • the mixed paste 301 in which the material and the uncured thermosetting resin were mixed was used, and the solder material was SnBi having a melting point of 138 ° C.
  • FIG. 6C includes a semiconductor package 101, a first electrode 102, a circuit board 105, a second electrode 104, and a SnAgCu solder paste 601.
  • the method for creating the mounting structure is as shown in FIG.
  • SnAgCu solder paste 601 is printed on the second electrode 104 of the circuit board 105 (FIG. 6A), and the bumps 103 formed on the first electrode of the semiconductor package 101 are mounted so as to hit ( FIG. 6 (b)).
  • Example 1 the mounting structure (mounting structure shown in FIG. 1) created under the conditions of Example 1 has the same connection reliability as the mounting structure created by soldering and joining the conventional semiconductor package component and the circuit board. It turns out that it is what you give.
  • the present invention provides a circuit between the semiconductor package 101 having the first electrode 102, the circuit board 105 having the second electrode 104, and the bump 103 formed on the second electrode 104 and the first electrode 102.
  • the bonding material 106 for electrically bonding the first electrode 102 and the second electrode 104 through the bump 103, the outer peripheral portion of the semiconductor package 101 disposed on the circuit board 105, and the circuit board 105 are used for reinforcement. It can be said that the mounting structure is expected to be improved in drop-proof characteristics by covering the periphery of each bonding material with a reinforcing resin so as to cover the bonding portion between the bump 103 and the bonding material 106, particularly with the resin.
  • this mounting structure can be used for mobile devices typified by mobile phone devices. Moreover, since the reflow reached temperature at the time of manufacture of this mounting structure is lower than the conventional one, it can be said that it is useful as a countermeasure against environmental problems, particularly global warming.
  • the points for creating the mounting structure of the present invention include the bump 103 formed on the first electrode 102 of the semiconductor package 101 and the mixed paste 301 in which the solder material and the uncured thermosetting resin are mixed.
  • the relationship between the reaction start temperature of the thermosetting resin and the reinforcing resin 108 is preferably the following relationship.
  • the relationship of the melting point of the bump 103 formed on the first electrode 102> the reaction starting temperature of the reinforcing resin 108> the reaction starting temperature of the thermosetting resin contained in the mixed paste 301> the melting point of the solder material is required.
  • the drop-proof property of the mounting structure created under these conditions is the conventional soldering method, that is, the BGA and the circuit board are fixed by filling the reinforcing resin material between the BGA and the circuit board after soldering.
  • the conventional soldering method that is, the BGA and the circuit board are fixed by filling the reinforcing resin material between the BGA and the circuit board after soldering.
  • the mounting structure and the manufacturing method thereof according to the present invention can improve the drop-proof property of the joint portion between the semiconductor package and the circuit board, which is conventionally applied to mobile devices such as mobile phone devices.
  • An SnBi solder material having a lower melting point than the SnAgCu solder that has been used can be used.
  • FIG. 2 In the manufacturing process of the first embodiment shown in FIG. 2, after the semiconductor package 101 is mounted on the circuit board 105 and before the reflow is performed, the reinforcing resin 108 is applied by the dispenser 302.
  • the second embodiment is different in that a reinforcing resin 108 is applied to the circuit board 105 before the semiconductor package 101 is mounted on the circuit board 105. The rest is the same as in the first embodiment.
  • the mixed paste 301 mixed is printed on the second electrode 104 of the circuit board 105. Thereafter, in FIG. 4B, the reinforcing resin 108 is applied to the peripheral region of the circuit board 105 where the semiconductor package 101 is mounted with the dispenser 302.
  • a semiconductor is formed on the circuit board 105 so that the bump 103 formed on the first electrode 102 of the semiconductor package 101 and the mixed paste 301 printed on the circuit board 105 are brought into contact with each other.
  • the package 101 is mounted.
  • the mixed paste 301 and the reinforcing resin 108 are heated using a reflow apparatus to melt the mixed paste 301, and the bonding material 106 and the reinforcing resin 107 are separated from the mixed paste 301. .
  • the first electrode 102 and the second electrode 104 are bonded with the bump 103 and the bonding material 106, and the boundary between the bonding material 106 and the bonding material 106 and the bump 103 is covered with the reinforcing resin 107.
  • the reinforcing resin 108 covers the outer peripheral portion of the semiconductor package 101 and forms a fillet with the circuit board 105.
  • the mounting structure 100 shown in FIG. 1 can also be manufactured by the manufacturing method shown in FIG. (Embodiment 3) 5A and 5B show a mounting structure according to Embodiment 3 of the present invention.
  • FIG. 5A is a cross-sectional view of the semiconductor package 101 of the mounting structure 100 obtained by the mounting method according to Embodiment 2 of the present invention
  • FIG. 5B is an enlarged view of the left end of FIG. 5A.
  • the inner periphery 110 of the reinforcing resin 108 is not in contact with the reinforcing resin 107 or the bump 103.
  • the reinforcing resin 108 is used as a semiconductor package. 101, a bump 103 formed on the first electrode, a reinforcing resin 107 that reinforces a bonding material 106 that electrically bonds the first electrode and the second electrode through the bump, and the circuit board 105.
  • the components of the reinforcing resin 108 and the reinforcing resin 107 are preferably the same.
  • the reinforcing resin 108 an epoxy resin is suitable.
  • the components of the reinforcing resin 108 and the reinforcing resin 107 are same, it is easy to adjust the reaction start temperature of the resin due to the action of heat during reflow, and at the time of curing, the reinforcing resin 108 and the bump Even if the component of the reinforcing resin 107 that reinforces the bonding material 106 that electrically bonds the first electrode and the second electrode is mixed, the physical properties of the cured resin can be easily maintained.
  • the mounting structure 100 according to the third embodiment can be manufactured by increasing the amount of the reinforcing resin 108 in the step shown in FIG. 2C or the step shown in FIG. 4B.
  • the drop resistance characteristics of the mounting structure according to the third embodiment are better than those according to the first embodiment.
  • the present invention it contributes to improving the reliability of mobile devices such as mobile phone devices.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

この実装構造体は、回路基板(105)の第2電極(104)と半導体パッケージ(101)のバンプ(103)とを接合する接合材料(106)の周囲を、第1補強用樹脂(107)によって覆っている。さらに、半導体パッケージ(101)の外周部分と回路基板(105)との間が、第2補強用樹脂(108)によって覆われている。接合材料(106)が従来よりも融点の低いはんだ材料を使用しても、耐落下特性が良好である。

Description

実装構造体とその製造方法
 本発明は、回路基板に半導体パッケージ部品を表面実装した実装構造体およびその製造方法に関するものである。
 従来のBGA(Ball Grid Array )やCSP( Chip Scale Package )のように下面
にバンプを有する半導体パッケージ部品は、図6(a)~(d)で説明する工程によって実装されている。
 図6(a)では、回路基板105の第2電極104にSnAgCuはんだペースト601が印刷される。そして図6(b)に示すように、半導体パッケージ101の第1電極102上に形成されたバンプ103が、SnAgCuはんだペースト601を介して第2電極104にあたるように実装される。
 図6(c)で、リフローをする。リフローすると第2電極104に印刷されたSnAgCuはんだペースト601と第1電極102上に形成されたバンプ103のはんだが、溶融し、セルフアライメント性によって半導体パッケージ101が適正な位置に移動する。その後、はんだの溶融温度以下に達するとはんだが凝固し、はんだ602となり半導体パッケージ101の回路基板105への電気接続が完了する。このときの、第2電極104に印刷されたSnAgCuはんだペースト601と半導体パッケージ101のバンプ103の組成は同一であり、一般的には、SnAgCu系のものが用いられる。
 また、BGAやCSPのように下面にバンプが形成されている半導体パッケージ101は、携帯電話装置に代表されるモバイル機器に利用されており、これらの商品に求められる機能として、落下衝撃に耐えることが求められている。この対策として、例えばBGAと回路基板105とをはんだ接合する場合には、図6(d)に示すように、SnAgCuはんだ602によるはんだ付け後に半導体パッケージ101と回路基板105の間にアンダーフィル603を充填して、接合部の耐落下特性を高める手法が用いられている(特許文献1)。
 また、近年、環境問題、特に地球温暖化の関心の高まりから、従来用いられてきたSnAgCu系のはんだよりも融点の低いSnBi系はんだ材料の使用が検討され始めている。ところが、低融点はんだを用いたBGA接続に関する接続信頼性は確立されていない。
 従来の低融点はんだを用いたBGA接続に関しては、以下のようなものがある。
 例えば、図7は特許文献2に記載された実装構造体である。
 この実装構造体は、第1電極102を有する半導体パッケージ101と第2電極104を有する回路基板105と、第1電極102上に形成されたバンプ103と、バンプ103と第2電極104の間に配置され、バンプ103を通じて第1電極102と第2電極104とを電気的に接続する接合部材106と、バンプ103と接合材料106との接合部分および接合部材を覆うように個々の接合部材の周囲に配置された補強用樹脂107とを備え、それぞれの補強用樹脂107が、隣接する補強用樹脂同士が接触しないように、互いに離間して配置されている。
特開平10-101906号公報 WO2010/050185号
 特許文献2のように補強用樹脂107を設けたことによって、従来のSnAgCu系のはんだと同等以上の耐落下特性を得ることが可能である。
 しかしながら、SnAgCu系はんだでのはんだ接合後、半導体パッケージ101と回路基板の間にアンダーフィル材603などを固着させた場合と比較すると、十分な耐落下特性を得ることができない。つまり、携帯電話装置に代表されるモバイル機器などに対して、従来用いられてきたSnAgCu系のはんだよりも融点の低いSnBi系はんだ材料を使用できないことを示している。
 また、アンダーフィル材を用いる場合、一度、SnAgCu系はんだでのはんだ接合後、ディスペンサーによるアンダーフィル材の塗布後、アンダーフィル材を硬化させるために硬化炉を用いて、硬化させることが必要である。このため、アンダーフィル材603を用いた実装構造体は、環境問題の点から好ましくない。
 本発明は、前記従来の課題を解決するもので、半導体パッケージを回路基板に電気的に接続した実装構造体において、接合部の耐落下特性を高めることができ、アンダーフィル材を用いる場合の硬化炉を必要としない環境に優しい実装構造体およびその製造方法を提供することを目的とする。
 本発明の実装構造体は、第1電極を有する半導体パッケージと、第2電極を有する回路基板と、前記第2電極と前記第1電極上に形成されたバンプとの間に配置され、前記バンプと第2電極とを電気的に接合するはんだを含む接合材料と、前記接合材料の周囲を覆う第1補強用樹脂と、前記回路基板に配置された前記半導体パッケージの外周部分と前記回路基板との間を覆う第2補強用樹脂とを含むことを特徴とする。
 また、本発明の実装構造体の製造方法は、回路基板上の第2電極上に、はんだ材料と未硬化状態の熱硬化性樹脂が混和したペーストを塗布し、前記混和したペーストを介して前記回路基板の第2電極上に、半導体パッケージをバンプを介してマウントし、前記半導体パッケージの外周部と前記回路基板との間にわたって補強用樹脂を塗布し、前記回路基板と前記半導体パッケージとを加熱することにより、前記はんだ材料と前記熱硬化性樹脂とを分離させ、前記バンプの融点より低い融点を有する前記はんだ材料を用いることで、前記はんだ材料が溶融し、前記バンプに濡れ上がり、その後、前記熱硬化性樹脂が前記はんだ材料と前記バンプの周囲に濡れ上がり、その後、前記熱硬化性樹脂と前記補強用樹脂が硬化することを特徴とする。
 また、本発明の実装構造体の製造方法は、回路基板上の第2電極上に、はんだ材料と未硬化状態の熱硬化性樹脂が混和したペーストを塗布し、前記回路基板における前記半導体パッケージがマウントされる周辺領域に補強用樹脂を塗布し、前記混和したペーストに前記半導体パッケージをバンプを介して回路基板の第2電極上にマウントし、前記回路基板と前記半導体パッケージとを加熱することにより、前記はんだ材料と前記熱硬化性樹脂とを分離させ、前記バンプの融点より低い融点を有する前記はんだ材料を用いることで、前記はんだ材料が溶融し、前記バンプに濡れ上がり、その後、前記熱硬化性樹脂が前記はんだ材料と前記バンプの周囲に濡れ上がり、その後、前記熱硬化性樹脂と前記補強用樹脂を硬化させることを特徴とする。
 本発明によれば、前記接合材料の周囲が第1補強用樹脂で覆われており、かつ、半導体パッケージの外周部分と前記回路基板を第2補強用樹脂によって覆うことにより、接合部の耐落下特性を高めることができる。
(a)本発明の実施の形態1における実装構造体の断面図と(b)平面図 (a)~(d)は同実施の形態の製造工程を説明する図 同実施の形態の実施例1の条件で作成した実装構造体の断面の顕微鏡写真 比較例1の条件で作成した実装構造体の断面の顕微鏡写真 比較例2の条件で作成した実装構造体の断面の顕微鏡写真 (a)~(d)は本発明の実施の形態2における製造の工程図 本発明の実施の形態3の実装構造体の断面図 本発明の実施の形態3の実装構造体の要部の拡大図 (a)~(d)は特許文献1における実装構造体の断面図 特許文献2における実装構造体の断面図
 以下、本発明の実施の形態について、図面を参照しながら説明する。
  (実施の形態1)
 図1(a)(b)は、回路基板105に半導体パッケージ101を実装した実施の形態1の実装構造体100を示す。
 半導体パッケージ101の第1電極102、バンプ103、回路基板105の第2電極104などは、半導体パッケージ101の大きさに比べて拡大して図示されている。半導体パッケージ101の具体的な大きさは、例えば、□11mmであり、バンプ103は0.5mmピッチでは441個のバンプが設けられている。回路基板105は、JEDEC半導体技術協会( JEDEC Solid State Technology Association )規格に準拠して作成されたもので、長手132mm、短手77mmの大きさで、厚み1.0mmで、電極材料が銅で、基板材質は、ガラスエポキシ材料である。
 図2(a)~(d)はこの実装構造体100の製造工程を説明する図である。
 図2(a)では、回路基板105の第2電極104上にそれぞれ混合ペースト301を印刷する。混合ペースト301は、SnとBi、In、Ag、およびCuの群から選ばれる2種類もしくは、それ以上の元素との組み合わせからなる合金組成のはんだ材料(後に接合材料106となるもの)と、未硬化状態の熱硬化性樹脂(後に補強用樹脂107となるもの)とからなる。
 図2(b)では、半導体パッケージ101の第1電極102上に形成されたバンプ103と、回路基板105上に印刷された混合ペースト301とを接触させるように、回路基板105上に半導体パッケージ101をマウントする。
 図2(c)では、半導体パッケージ101の外周と回路基板105の表面の間に、第2補強用樹脂としての補強用樹脂108をディスペンサー302で塗布する。その後、図2(d)では、リフロー装置を用い、混合ペースト301と補強用樹脂108を加熱して、混合ペースト301を溶融し、混合ペースト301から、接合材料106と第1補強用樹脂としての補強用樹脂107とを分離させる。その結果、第1電極102と第2電極104との間をバンプ103と接合材料106とで結合し、かつ、接合材料106とバンプ103との境目を補強用樹脂107で覆う。補強用樹脂108は、半導体パッケージ101の外周部分を覆うとともに、回路基板105との間にフィレットを形成する。図1(a)は図2(d)の拡大図である。
 この製造方法によると、半導体パッケージ101の第1電極102上に形成されたバンプ103と、回路基板105の第2電極104の間が、溶融固化した接合材料106によってはんだ接続されて電気的に導通している。接合材料106は、バンプ103より融点が低い合金組成である。回路基板105の第2電極104の周囲と、バンプ103との間は、補強用樹脂107で覆って接合されている。また、半導体パッケージ101の外周部と、回路基板105との間も、補強用樹脂108によって接合されている。補強用樹脂108は、半導体パッケージ101と回路基板105の間をつなぐとともに、半導体パッケージ101の周囲にフィレットを形成している。
 この実施の形態1では、補強用樹脂108は、半導体パッケージ101の外周部と回路基板105を覆うように配置されているが、補強用樹脂108と半導体パッケージ101の第1電極上に形成されたバンプ103や、補強用樹脂107とは接触しないように、配置されている。
 このように、バンプ103を通じて第1電極102と第2電極104を電気的に接続する接合材料106を、補強用樹脂107と補強用樹脂108の両方で補強することによって、さらに詳しくは、半導体パッケージ101と回路基板105の間をつなぐとともに、半導体パッケージの周囲にフィレットを補強用樹脂107で形成しているので、落下などの機械的衝撃を受けた場合においても、回路基板105の変形を抑制することができ、図7に示した従来例のように、接合材料106を補強用樹脂107だけで補強した場合に比べて、接合部の耐落下特性を高めることができる。
 さらに、アンダーフィル材を用いる場合の硬化炉を必要としない環境に優しい製造方法である。また、半導体パッケージ101と回路基板105の間の全部に補強用樹脂108が充填されているのではなく、補強用樹脂108が充填されていない空間109が形成されているため、図6に示した従来例に較べてアンダーフィル樹脂の使用量が少ない。
 ここで、半導体パッケージ101の実装構造体100の構成および材料仕様になどについて、さらに詳細に説明する。
 バンプ103は、Sn系合金から形成されていることが望ましい。例えば、SnBi系、SnIn系、SnBiIn系、SnAg系、SnCu系、SnAgCu系、SnAgBi系、SnCuBi系、SnAgCuBi系、SnAgIn系、SnCuIn系、SnAgCuIn系、およびSnAgCuBiIn系からなる群から選ばれる合金組成を用いることができる。
 特に、Sn系がよい。Sn系合金は融点が231℃と低くく、Cu電極に濡れ易く、他の合金と化合物を作りやすい。また安価で、毒性も低いためである。
接合材料106は、バンプ103より融点が低い合金組成を用いることができる。好ましい例としては、バンプ103と接合材料106ともに、同じ系、または、主成分が同じSn系が好ましい。
補強用樹脂107、108は、主成分の樹脂成分と、硬化剤とを含み、必要に応じて、粘度調整/チクソ性付与添加剤を含む。
補強用樹脂107は、熱硬化性樹脂であり、エポキシ樹脂、ウレタン樹脂、アクリル樹脂、ポリイミド樹脂、ポリアミド樹脂、ビスマレイミド樹脂、フェノール樹脂、ポリエステル樹脂、シリコーン樹脂、オキセタン樹脂など、さまざまな樹脂を含むことができる。これらは、単独で用いてもよく、2種類以上を組み合わせても良い。これらのうちでは、エポキシ樹脂が好適である。
 補強用樹脂108は、熱硬化性樹脂であり、エポキシ樹脂、ウレタン樹脂、アクリル樹脂、ポリイミド樹脂、ポリアミド樹脂、ビスマレイミド樹脂、フェノール樹脂、ポリエステル樹脂、シリコーン樹脂、オキセタン樹脂など、さまざまな樹脂を含むことができる。これらは、単独で用いてもよく、2種類以上を組み合わせても良い。これらのうちでは、エポキシ樹脂が好適である。
 補強用樹脂107と、補強用樹脂108とは、樹脂成分がともにエポキシ系などの同じ系の樹脂がよい。さらに、樹脂成分を同じにして、含有させる硬化剤のみを変えることで反応開始温度のみを2つの樹脂で変えるのが好ましい。
 エポキシ樹脂としては、ビスフェノール型エポキシ樹脂、多官能エポキシ樹脂、可とう性エポキシ樹脂、臭素化エポキシ樹脂、グリシジルエステル型エポキシ樹脂、高分子型エポキシ樹脂の群から選ばれるエポキシ樹脂を用いることができる。例えば、ビスフェノールA型エポキシ樹脂、ビスフェノールF型エポキシ樹脂、ビフェニル型エポキシ樹脂、ナフタレン型エポキシ樹脂、フェノールノボラック型エポキシ樹脂、クレゾールノボラック型エポキシ樹脂などが用いられる。これらを変性させたエポキシ樹脂も用いられる。これらは、単独で用いてもよく、2種類以上を組み合わせて用いても良い。
 上記のような熱硬化性樹脂と組み合わせて用いる硬化剤としては、チオール系化合物、アミン系化合物、多官能フェノール系化合物、イミダゾール系化合物、および酸無水物系化合物の群から選ばれる化合物を用いることができる。これらは、単独で用いてもよく、2種類以上を組み合わせてもよい。
 また、必要に応じ、粘度調整/チクソ性付与添加剤として、無機系あるいは、有機系のものを使用でき、例えば、無機系であれば、シリカやアルミナなどが用いられ、有機系であれば、アマイド、ポリエステル系、ひまし油などの誘導体などが用いられる。これらは、単独でもよく、2種類以上を組み合わせてもよい。
  (実施例)
 本発明の実施例として、はんだ材料と未硬化状態の熱硬化性樹脂が混和した混合ペースト301の種類と補強用樹脂108、リフロー到達温度を変化させ、導通の合否、耐落下特性の影響を調べ、下記の表1にその結果を示した。
Figure JPOXMLDOC01-appb-T000001
               - 材料 -
 はんだ材料と未硬化状態の熱硬化性樹脂が混和した混合ペースト301は、はんだ材料にSn58Biはんだ88重量部に対し、未硬化状態の熱硬化性樹脂として、熱硬化性樹脂であるビスフェノールF型エポキシ樹脂(商品名「YDF-7510」新日鐵化学株式会社製)を用いた。
 粘度調整剤/チクソ付与材には、ひまし油系チクソ剤(商品名「THIXCIN R」エレメンティスジャパン(ElementisSpecialties, Inc.)製)と硬化剤であるイミダゾール系硬化剤、フラックス作用を有する有機酸(「アジピン酸」関東化学株式会社製)を練り込んだものを18重量部混ぜたものを使用した。このとき、硬化剤であるイミダゾール系硬化剤に関しては、以下の考えで調整した。はんだ材料の融点が138℃のSn58Biに対して、エポキシ樹脂と硬化剤の反応開始温度が130℃、140℃、155℃となる未硬化状態の熱硬化性樹脂を作成する場合において、それぞれ、2,4-ジアミノ-6-(2’-メチルイミダゾリル-(1’))-エチル-s-トリアジンイソシアヌル酸付加物(商品名「2MA-OK」四国化成工業株式会社製)、2-フェニル-4-メチル-5-ヒドロキシメチルイミダゾール(商品名「2P4MHZ-PW」四国化成工業株式会社製)、2-フェニル-4,5-ジヒドロキシメチルイミダゾール(商品名「2PHZ-PW」四国化成工業株式会社製)を使用した。
 SnAgCu混合ペースト301には、Sn3.0Ag0.5Cu(商品名「M705-GRN360-L60A」千住金属工業株式会社製)を用いた。
 半導体パッケージ101には、第1電極上に形成されたバンプ103として、Sn3.0Ag0.5Cuボール搭載の半導体パッケージを用いた。
 Sn58Biはんだの融点は、138℃であり、Sn3.0Ag0.5Cuはんだの融点は、217℃である。
 補強用樹脂108には、熱硬化性樹脂には、ビスフェノールF型エポキシ樹脂(商品名「YDF-7510」新日鐵化学株式会社製)、硬化剤には、130℃硬化対応のイミダゾール系硬化剤(商品名「2MA-OK」四国化成工業株式会社製)、140℃硬化対応のイミダゾール系硬化剤(商品名「2P4MHZ-PW」四国化成工業株式会社製)、または、155℃硬化対応のイミダゾール系硬化剤(商品名「2PHZ-PW」四国化成工業株式会社製)粘度調整/チクソ性付与添加剤には、シリカ系チクソ剤(商品名「AEROSIL RY200」日本アエロジル株式会社製)を共通して使用した。
  (評価)
 それぞれの実装構造体の評価は、以下のように行った。
 導通の合否として、実装構造体作成後、テスターにて、導通の有無を確認した。導通の合否は、抵抗値が9.8~10Ωの範囲である場合を合格として、○で表記し、範囲外である場合を、×と表記した。
 耐落下試験としては、耐落下寿命で評価した。具体的には、JEDEC規格に準拠し、加速度、1500G、落下時間、0.5秒の条件で実装構造体を落下させ、電気的接続に瞬断が生じたときを耐落下寿命とし、瞬断発生までの落下回数を耐落下寿命とした。瞬断の合否判定としては、落下時に、半導体パッケージに2.0Vの電圧を印加し、電圧が10%以上低下したときを不合格と判断した。また、このときの最高落下回数を30回とした。
 なお、ここで用いた半導体パッケージの大きさは、□11mmサイズであり、第1電極上に形成されたバンプ103は、0.5mmピッチで、バンプ数は441個であり、回路基板105は、長手132mm、短手77mmの大きさで、厚み1.0mmで、電極材料が銅で、基板材質は、ガラスエポキシ材料である。
            (評価結果1:導通試験)
 表1の実施例1~3、比較例1~2の条件で、図2に示した実装方法1で作成した実装構造体の導通の合否について評価した結果を示す。
 表1は、はんだ材と未硬化状態の熱硬化性樹脂が混和した混合ペースト301のはんだ組成をSn58Bi(融点:138℃)とし、はんだ材と未硬化状態の熱硬化性樹脂が混和した混合ペースト301に含まれる未硬化状態の熱硬化性樹脂の硬化剤と補強用樹脂108に含まれる硬化剤の反応開始温度を変化させ、本発明の実装構造体を作成する際に求められる材料特性について検討した結果を示している。
 実施例1の条件は、はんだ材と未硬化状態の熱硬化性樹脂が混和した混合ペースト301を用いて、実装構造体100を作成した。
 はんだ材と未硬化状態の熱硬化性樹脂が混和した混合ペースト301のはんだ組成がSn58Bi(はんだ融点138℃)、140℃硬化対応のイミダゾール系硬化剤(商品名「2P4MHZ-PW」四国化成工業株式会社製)を用いて作成されたもので、補強用樹脂108の硬化剤にも同様のものを用いて実装構造体を作成したところ、抵抗値が、9.9Ωとテスターにて導通がとれることが確認された。
 図3Aは、実施例1の条件で作成した実装構造体の断面の顕微鏡写真である。半導体パッケージ101、第1電極102、第1電極上に形成されたバンプ103、回路基板105上に形成された第2電極104、接合材料106、補強用樹脂107から構成されている。
 このときの、第1電極上に形成されたバンプ103の組成は、融点が217℃のSn3.0Ag0.5Cuはんだバンプとした。また、実装構造体を作成する際のリフロー到達温度は、160℃とした。
 その結果、接合材料106が、バンプ103の周囲に破線部まで濡れ上がっており、更にその周囲を補強用樹脂107が破線部までフィレット形状を形成していることが確認された。
 これらの結果より、図3Aの構造体の作成には、混合ペースト301のはんだ融点の138℃に対し、未硬化状態の熱硬化性樹脂と補強用樹脂の硬化剤の反応開始温度が140℃と高いことが有効であることがわかった。
 また、実施例2、3の条件、Sn58Biはんだの融点138℃融点よりも反応開始温度が高い140℃硬化対応のイミダゾール系硬化剤(商品名「2P4MHZ-PW」四国化成工業株式会社製)、または、155℃硬化対応のイミダゾール系硬化剤(商品名「2PHZ-PW」四国化成工業株式会社製)を用いた作成したはんだ材料と未硬化状態の熱硬化性樹脂が混和した混合ペースト301や補強用樹脂108を用いて、実装構造体を作成した場合においても、実施例1と同様の結果を得ることができた。
 つまり、はんだ材と未硬化状態の熱硬化性樹脂が混和した混合ペースト301のはんだ融点より、未硬化状態の熱硬化性樹脂と補強用樹脂108の硬化剤の反応開始温度が、高いことが、本発明の実装構造体を作成するなかで重要となる。
 次に、比較例1の条件、混合ペースト301のはんだの融点138℃に対し、はんだ材料と未硬化状態の熱硬化性樹脂が混和した混合ペースト301の反応開始温度が、130℃硬化対応のイミダゾール系硬化剤(商品名「2MA-OK」四国化成工業株式会社製)で、補強用樹脂108が140℃硬化対応のイミダゾール系硬化剤(商品名「2P4MHZ-PW」四国化成工業株式会社製)のものを用いて実装構造体を作成したところ、抵抗値が、18Ωと導通の確認が得られなかった。
 つまり、実施例1との違いは、はんだの融点138℃に対して、未硬化状態の熱硬化性樹脂の硬化剤の反応開始温度が130℃、補強用樹脂108の反応開始温度が、140℃である。
 比較例1の条件で作成した実装構造体の断面の顕微鏡写真を図3Bに示す。これを観察したところ、補強用樹脂107が、バンプ103の周囲に破線部まで濡れ上がっているのが確認されたものの、接合材料106がバンプ103の周囲にまで濡れ上がらず、破線部の状態で留まっているのが確認された。
 つまり、比較例1の条件で実装構造体を作成すると、はんだ材料と未硬化状態の熱硬化性樹脂が混和した混合ペースト301に含まれるはんだ材料が第1電極上に形成されたバンプ103の周囲に濡れ上がる前に、未硬化状態の熱硬化性樹脂が第1電極上に形成されたバンプ103の周囲に濡れ上がり硬化が完了するために導通の確認が得られないことがわかった。
 また、比較例2の条件、混合ペースト301のはんだの融点138℃に対し、はんだ材料と未硬化状態の熱硬化性樹脂が混和した混合ペースト301の反応開始温度が、140℃硬化対応のイミダゾール系硬化剤(商品名「2P4MHZ-PW」四国化成工業株式会社製)で、補強用樹脂108が130℃硬化対応のイミダゾール系硬化剤(商品名「2MA-OK」四国化成工業株式会社製)のものを用いて実装構造体を作成したところ、抵抗値が、23Ωと、導通の確認は得られなかった。
 つまり、実施例1との違いは、はんだの融点138℃に対して、未硬化状態の熱硬化性樹脂の硬化剤の反応開始温度が140℃、補強用樹脂107の反応開始温度が、130℃である。
 比較例2の条件で作成した実装構造体の断面の顕微鏡写真を図3Cに示す。これを観察したところ、バンプ103の周囲に、補強用樹脂108は濡れ上がっているものの、接合材料106が濡れ上がっていないことが確認された。
 これは、はんだ材料と未硬化状態の熱硬化性樹脂が混和した混合ペースト301のはんだ材の融点(138℃)よりも先に、130℃硬化対応のイミダゾール系硬化剤(商品名「2MA-OK」四国化成工業株式会社製)からなる補強用樹脂108が硬化してしまい、はんだ溶融時に、半導体パッケージ101が沈み込まなかった。そのため、溶融したはんだと、第1電極上に形成されたバンプ103間の距離が長くなり、溶融したはんだが、第1電極上に形成されたバンプ103に濡れ上がることができなかった。
           - 導通試験の結果まとめ -
 これらの結果より、本発明の実装構造体を作成する場合において、回路基板105に塗布されるはんだ材料の融点に対し、未硬化状態の熱硬化性樹脂および補強用樹脂の反応開始温度が高いことが好ましいことがわかる。
 本発明の実装構造体の作成プロセスとしては、はんだ材料と未硬化状態の熱硬化樹脂が混和した混合ペースト301に含まれるはんだ材料が溶融し、半導体パッケージの101の第1電極上に形成されたバンプ103にはんだ材料が濡れ上がった後、その周囲に未硬化状態の熱硬化樹脂が濡れ上がり、未硬化状態の熱硬化樹脂と補強用樹脂の硬化が開始し、完了することが、本発明の実装構造体を作成するプロセスとして有用であることが、導通の合否からもわかる。
 つまり、本発明の実装構造体を作成するポイントとしては、半導体パッケージ101の第1電極上に形成されたバンプ103の融点、はんだ材料と未硬化状態の熱硬化性樹脂が混和した混合ペースト301に含まれるはんだ材の融点とはんだ材料と未硬化状態の熱硬化性樹脂が混和した混合ペースト301に含まれる熱硬化性樹脂と補強用樹脂108の反応開始温度の関係が下記の関係であることが望ましい。
 第1電極上に形成されたバンプ103の融点 > 補強用樹脂108が硬化を開始する反応開始温度 ≧ 混合ペースト301中の熱硬化性樹脂の反応開始温度 > 混合ペースト301中のはんだ材の融点の関係が必要である。
 補強用樹脂108の反応開始温度と混合ペースト301中の熱硬化性の補強用樹脂107)の反応開始温度は、5℃から15℃の差があった方がよい。
 その理由は、補強用樹脂107が、はんだのバンプへの濡れ上がるための時間と、その周囲を覆うための補強用樹脂107の濡れ上がりのための時間を稼ぐためである。温度差がありすぎると、高い温度まで熱処理が必要となる。
 混合ペースト301中のはんだ材料の融点と、2つの樹脂の反応開始温度との差は、例えば、2℃から17℃で、好ましくは、10℃以上がよい。
 温度差が必要な理由は、はんだ材料が溶けて、半導体パッケージ101と前記回路基板105とのセルフアライメントの時間が必要であることです。
 一方、温度差がありすぎると、上記同様全体の熱処理温度が高くなってしまうことである。
              - 落下試験 -
 実施例1と下記の表2に示す比較例3~4について、実装構造体の耐落下特性の合否を評価した。
Figure JPOXMLDOC01-appb-T000002
 実施例1は図1に示した実装構造体100、比較例4は図6(d)に示した実装構造体、比較例3は図6(c)に示す状態の実装構造体である。
 耐落下試験は、耐落下寿命で評価した。具体的には、JEDEC規格に準拠し、加速度、1500G、落下時間、0.5秒の条件で実装構造体を落下させ、電気的接続に瞬断が生じたときを耐落下寿命とし、瞬断発生までの落下回数を耐落下寿命とした。瞬断の合否判定としては、落下時に、半導体パッケージに2.0Vの電圧を印加し、電圧が10%以上低下したときを不合格と判断した。また、このときの最高落下回数を30回とした。
 なお、ここで用いた半導体パッケージの大きさは、□11mmサイズであり、第1電極上に形成されたバンプ103は、0.5mmピッチで、バンプ数は441個であり、回路基板105は、長手132mm、短手77mmの大きさで、厚み1.0mmで、電極材料が銅で、基板材質はガラスエポキシ材料である。
 実施例1の条件にて実装構造体を作成し、耐落下寿命を評価したところ、30回を示した。なお、このときのリフロー到達温度は、160℃である。
 このときのバンプ103の組成は、融点が217℃のSn3.0Ag0.5Cuはんだバンプとした。また、実装構造体を作成する際のリフロー到達温度は、160℃とし、140℃硬化対応のイミダゾール系硬化剤(商品名「2P4MHZ-PW」四国化成工業株式会社製)を用いて作成されたはんだ材と未硬化状態の熱硬化性樹脂とが混和した混合ペースト301を用い、はんだ材は、融点が138℃のSnBiとした。
 比較例3において、図6(c)に示す実装構造体を作成し、評価した。
 図6(c)は、半導体パッケージ101、第1電極102、回路基板105、第2電極104、SnAgCuはんだペースト601から構成されている。
 実装構造体の作成方法は、図6に示す通りである。図6では、回路基板105の第2電極104にSnAgCuはんだペースト601が印刷され(図6(a))、半導体パッケージ101の第1電極上に形成されたバンプ103があたるように実装される(図6(b))。
 図6(c)で、リフローをする。リフローすると第2電極104に印刷されたSnAgCuはんだペースト601と第1電極上に形成されたバンプ103のはんだが、溶融し、セルフアライメント性によって半導体パッケージ部品が適正な位置に移動する。その後、はんだの溶融温度以下に達すると、はんだを凝固させ、半導体パッケージ101の回路基板105への電気接続が完了する。このときの、第2電極104に印刷されたSnAgCuはんだペースト601と半導体パッケージ101のバンプ103の組成は同一である。また、このときのリフロー到達温度は、250℃である。
 この実装構造体(図6(c))について評価したところ、耐落下寿命が5回であり、実施例4の耐落下寿命に対して劣ることがわかる。
 比較例4の条件で作成した図6(d)のアンダーフィル603を用いた実装構造体を作成し、耐落下特性を評価した。この実装構造体(図6(d))は、比較例3の方法にて作成した実装構造体(図6(c))に、ディスペンサーにて、アンダーフィル603を塗布後、加熱にて硬化させたものである。
 この実装構造体(図6(d))について評価したころ、耐落下寿命が30回(最大落下回数)であり、実施例6と同等の接続信頼性が得られる実装構造体であることがわかった。
          - 落下試験の結果のまとめ -
 つまり、実施例1の条件で作成した実装構造体(図1に示す実装構造体)が、従来の半導体パッケージ部品と回路基板をはんだ付け接合して作成した実装構造体と同等の接続信頼性を与えるものであることがわかる。
 上述のように、本発明は、第1電極102を有する半導体パッケージ101と、第2電極104を有する回路基板105と、第2電極104と第1電極102上に形成されたバンプ103との間に配置され、バンプ103を通じて第1電極102と第2電極104とを電気的に接合する接合材料106と、前記回路基板105に配置された半導体パッケージ101の外周部分と前記回路基板105が補強用樹脂によって覆う、特にバンプ103と接合材料106との接合部を覆うように、個々の接合材料の周囲を補強用樹脂で覆うことにより、耐落下特性の向上が見込まれる実装構造体と言える。つまり、携帯電話装置に代表されるモバイル機器に利用可能ということである。また、この実装構造体の製造時の、リフロー到達温度が従来のものより低いことから、環境問題、特に地球温暖化の対策として有用であると言える。
 つまり、本発明の実装構造体を作成するポイントとしては、半導体パッケージ101の第1電極102上に形成されたバンプ103、はんだ材料と未硬化状態の熱硬化性樹脂が混和した混合ペースト301に含まれる熱硬化性樹脂と補強用樹脂108の反応開始温度の関係が下記の関係であることが望ましい。
 第1電極102上に形成されたバンプ103の融点 > 補強用樹脂108の反応開始温度 ≧ 混合ペースト301に含まれる熱硬化性樹脂の反応開始温度 > はんだ材料の融点という関係が必要である。
 また、この条件にて作成した実装構造体の耐落下特性は、従来のはんだ付け方法、つまり、はんだ付け後にBGAと回路基板の間に補強樹脂材料を充填してBGAと回路基板とを固着させることにより、接合部の耐落下特性を高める手法が用いられている(図6(d))(特許文献1)と同等であることがわかる。
 このように、本発明の実装構造体およびその製造方法は、半導体パッケージと回路基板との接合部の耐落下特性を高めることができ、携帯電話装置に代表されるモバイル機器などに対して、従来用いられてきたSnAgCu系のはんだよりも融点の低いSnBi系はんだ材料を使用可能にすることができる。
  (実施の形態2)
 図4(a)~(d)は、実装構造体100の別の製造方法を示す。
 図2に示した実施の形態1の製造工程では、回路基板105上に半導体パッケージ101をマウントした後で、リフローを実施する前のタイミングに、ディスペンサー302によって補強用樹脂108を塗布したが、この実施の形態2では、半導体パッケージ101を回路基板105上にマウントする前に、補強用樹脂108を回路基板105に塗布している点が異なっている。その他は実施の形態1と同じである。
 図4(a)では、回路基板105の第2電極104上に、混和した混合ペースト301を印刷する。
 その後、図4(b)では、回路基板105における半導体パッケージ101がマウントされる周辺領域に補強用樹脂108をディスペンサー302で塗布する。
 その後、図4(c)では、半導体パッケージ101の第1電極102上に形成されたバンプ103と、回路基板105上に印刷された混合ペースト301とを接触させるように、回路基板105上に半導体パッケージ101をマウントする。
 その後、図4(d)では、リフロー装置を用い、混合ペースト301と補強用樹脂108を加熱して、混合ペースト301を溶融し、混合ペースト301から接合材料106と補強用樹脂107とを分離させる。結果、第1電極102と第2電極104との間をバンプ103と接合材料106とで結合し、かつ、接合材料106と、接合材料106とバンプ103との境目を補強用樹脂107で覆う。補強用樹脂108は、半導体パッケージ101の外周部分を覆うとともに、回路基板105との間にフィレットを形成する。
 このように、図4に示した製造方法でも図1に示した実装構造体100を製造できる。
  (実施の形態3)
 図5Aと図5Bは本発明の実施の形態3の実装構造体を示す。
 図5Aは、本発明の実施の形態2における実装方法によって得られる実装構造体100の半導体パッケージ101の断面図であり、また、図5Bは、図5Aの左端を拡大したものである。
 実施の形態1の実装構造体100は、補強用樹脂108の内周110が補強用樹脂107やバンプ103に接触していなかったが、この実施の形態3では、補強用樹脂108が、半導体パッケージ101、第1電極上に形成されたバンプ103、バンプを通じて第1電極と第2電極を電気的に接合する接合材料106を補強する補強用樹脂107と回路基板105と接している。補強用樹脂108と補強用樹脂107の成分が同じであることが好適である。
 補強用樹脂108としてはエポキシ樹脂が好適である。補強用樹脂108と補強用樹脂107の成分を同じにすることにより、リフロー時の熱の作用による樹脂の反応開始温度を調整することが容易であり、また、硬化時に、補強用樹脂108とバンプを通じて第1電極と第2電極を電気的に接合する接合材料106を補強する補強用樹脂107の成分が混和したとしても、硬化物としての樹脂の物性を保持しやすい。
 この実施の形態3の実装構造体100は、図2(c)に示した工程または図4(b)に示した工程において、補強用樹脂108の量を増やすことで製造できる。
 この実施の形態3の実装構造体の耐落下特性は実施の形態1の場合よりも良好である。
 本発明によると、携帯電話装置に代表されるモバイル機器などの信頼性の向上に寄与する。
 100 実装構造体
 101 半導体パッケージ
 102 第1電極
 103 バンプ
 104 第2電極
 105 回路基板
 106 接合材料
 107 補強用樹脂(第1補強用樹脂)
 108 補強用樹脂(第2補強用樹脂)
 301 混合ペースト
 302 ディスペンサー

Claims (11)

  1.  第1電極を有する半導体パッケージと、
     第2電極を有する回路基板と、
     前記第2電極と前記第1電極上に形成されたバンプとの間に配置され、前記バンプと第2電極とを電気的に接合するはんだを含む接合材料と、
     前記接合材料の周囲を覆う第1補強用樹脂と、
     前記回路基板に配置された半導体パッケージの外周部分と前記回路基板との間を覆う第2補強用樹脂とを含む
    実装構造体。
  2.  前記第1補強用樹脂と前記第2補強用樹脂とが接触していることを特徴とする
    請求項1の実装構造体。
  3.  前記第1補強用樹脂と第2補強用樹脂との樹脂成分が同じ組成で、含まれる硬化剤が異なることを特徴とする
    請求項1記載の実装構造体。
  4.  前記バンプの合金組成と、前記接合材料とが、Sn系材料であることを特徴とする
    請求項1記載の実装構造体。
  5.  前記バンプの合金組成がSnAgCu系のはんだで形成され、前記接合材料が、SnBi系であることを特徴とする
    請求項1記載の実装構造体。
  6.  前記バンプの融点 > 前記第2補強用樹脂の反応開始温度 ≧ 前記第1補強用樹脂の反応開始温度 > 前記接合材料の融点
    である
    請求項1記載の実装構造体。
  7. 前記第1補強用樹脂の反応開始温度と前記第2補強用樹脂の反応開始温度とは、5℃から15℃の差がある
    請求項1記載の実装構造体。
  8. 前記第1補強用樹脂の反応開始温度と前記第2補強用樹脂の反応開始温度は、前記接合材料の融点との温度差が2℃から17℃である
    請求項1記載の実装構造体。
  9.  回路基板上の第2電極上に、はんだ材料と未硬化状態の熱硬化性樹脂が混和したペーストを塗布し、
     前記混和したペーストを介して前記回路基板の第2電極上に、半導体パッケージをバンプを介してマウントし、
     前記半導体パッケージの外周部と前記回路基板との間にわたって補強用樹脂を塗布し、
     前記回路基板と前記半導体パッケージとを加熱することにより、前記接合材料と前記熱硬化性樹脂とを分離させ、
     前記バンプの融点より低い融点を有する前記接合材料を用いることで、前記接合材料が溶融し、前記バンプに濡れ上がり、その後、前記熱硬化性樹脂が前記接合材料と前記バンプの周囲に濡れ上がり、その後、前記熱硬化性樹脂と前記補強用樹脂が硬化する
    実装構造体の製造方法。
  10.  回路基板上の第2電極上に、接合材料と未硬化状態の熱硬化性樹脂が混和したペーストを塗布し、
     前記回路基板における前記半導体パッケージがマウントされる周辺領域に補強用樹脂を塗布し、
     前記混和したペーストに前記半導体パッケージをバンプを介して回路基板の第2電極上にマウントし、
     前記回路基板と前記半導体パッケージとを加熱することにより、前記接合材料と前記熱硬化性樹脂とを分離させ、
     前記バンプの融点より低い融点を有する前記接合材料を用いることで、前記接合材料が溶融し、前記バンプに濡れ上がり、その後、前記熱硬化性樹脂が前記接合材料と前記バンプの周囲に濡れ上がり、その後、前記熱硬化性樹脂と前記補強用樹脂を硬化させる
    実装構造体の製造方法。
  11.  前記熱硬化性樹脂と前記補強用樹脂の反応開始温度が、前記接合材料の融点以上、かつ、前記バンプの融点以下であることを特徴とする
    請求項9または請求項10記載の実装構造体の製造方法。
PCT/JP2013/002354 2012-05-10 2013-04-05 実装構造体とその製造方法 WO2013168352A1 (ja)

Priority Applications (6)

Application Number Priority Date Filing Date Title
EP13787864.1A EP2849216B1 (en) 2012-05-10 2013-04-05 Mounting structure and method for manufacturing same
JP2014514363A JP6365841B2 (ja) 2012-05-10 2013-04-05 実装構造体とその製造方法
US14/396,297 US9795036B2 (en) 2012-05-10 2013-04-05 Mounting structure and method for manufacturing same
CN201380018441.8A CN104246997B (zh) 2012-05-10 2013-04-05 安装结构体及其制造方法
KR1020147024643A KR101975076B1 (ko) 2012-05-10 2013-04-05 실장 구조체와 그 제조 방법
US15/699,570 US10412834B2 (en) 2012-05-10 2017-09-08 Mounting structure and method for manufacturing same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2012-108063 2012-05-10
JP2012108063 2012-05-10

Related Child Applications (2)

Application Number Title Priority Date Filing Date
US14/396,297 A-371-Of-International US9795036B2 (en) 2012-05-10 2013-04-05 Mounting structure and method for manufacturing same
US15/699,570 Continuation US10412834B2 (en) 2012-05-10 2017-09-08 Mounting structure and method for manufacturing same

Publications (1)

Publication Number Publication Date
WO2013168352A1 true WO2013168352A1 (ja) 2013-11-14

Family

ID=49550422

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2013/002354 WO2013168352A1 (ja) 2012-05-10 2013-04-05 実装構造体とその製造方法

Country Status (7)

Country Link
US (2) US9795036B2 (ja)
EP (1) EP2849216B1 (ja)
JP (1) JP6365841B2 (ja)
KR (1) KR101975076B1 (ja)
CN (1) CN104246997B (ja)
TW (1) TWI582915B (ja)
WO (1) WO2013168352A1 (ja)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017094537A1 (ja) * 2015-12-03 2017-06-08 ソニー株式会社 半導体チップ及び電子機器
JP2023523954A (ja) * 2020-04-30 2023-06-08 ツェットカーヴェー グループ ゲーエムベーハー Smt部品の浮動に対するバリア

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9402321B2 (en) * 2012-10-15 2016-07-26 Senju Metal Industry Co., Ltd. Soldering method using a low-temperature solder paste
KR102396332B1 (ko) * 2015-09-22 2022-05-12 삼성전자주식회사 Led 디스플레이용 미세간격 코팅부재 및 이를 이용한 코팅방법
CN105914151B (zh) * 2016-04-18 2019-06-25 通富微电子股份有限公司 半导体封装方法
KR20180024099A (ko) * 2016-08-26 2018-03-08 삼성디스플레이 주식회사 접합 조립체 및 이를 포함하는 표시 장치
CN109195353A (zh) * 2018-09-17 2019-01-11 新华三技术有限公司 印制电路板、电子设备及其生产工艺
JP6914309B2 (ja) * 2019-10-31 2021-08-04 三菱電機株式会社 シート型絶縁ワニス及びその製造方法、電気機器、並びに回転電機
US11908784B2 (en) * 2020-09-23 2024-02-20 Nxp Usa, Inc. Packaged semiconductor device assembly
DE102021133746A1 (de) * 2021-12-17 2023-06-22 Endress+Hauser SE+Co. KG Verfahren zum Verlöten mindestens eines Bauteils mit mindestens einem Trägerelement

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10101906A (ja) 1996-10-03 1998-04-21 Shin Etsu Chem Co Ltd 液状エポキシ樹脂組成物の製造方法
JP2000188469A (ja) * 1998-12-22 2000-07-04 Nec Corp 半導体装置実装構造
JP2006199937A (ja) * 2004-12-15 2006-08-03 Tamura Kaken Co Ltd 導電性接着剤、これを用いた導電部及び電子部品モジュール
WO2010050185A1 (ja) 2008-10-27 2010-05-06 パナソニック株式会社 半導体の実装構造体およびその製造方法
JP2010272557A (ja) * 2009-05-19 2010-12-02 Panasonic Corp 電子部品実装方法および電子部品実装構造
WO2012042809A1 (ja) * 2010-09-27 2012-04-05 パナソニック株式会社 電子部品実装方法

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60100928A (ja) 1983-11-09 1985-06-04 松下電器産業株式会社 電気掃除機
JP4609617B2 (ja) * 2000-08-01 2011-01-12 日本電気株式会社 半導体装置の実装方法及び実装構造体
WO2002058108A2 (en) * 2000-11-14 2002-07-25 Henkel Loctite Corporation Wafer applied fluxing and underfill material, and layered electronic assemblies manufactured therewith
JP2003010811A (ja) 2001-07-03 2003-01-14 Ohbayashi Corp 廃棄物処分場における漏水検知方法
JP2004103928A (ja) * 2002-09-11 2004-04-02 Fujitsu Ltd 基板及びハンダボールの形成方法及びその実装構造
JP4413543B2 (ja) 2003-07-03 2010-02-10 パナソニック株式会社 電子部品用接着剤および電子部品実装方法
JP2008166377A (ja) * 2006-12-27 2008-07-17 Toshiba Corp プリント回路板の製造方法、プリント回路板及び補強電子部品
US20120017407A1 (en) 2009-03-31 2012-01-26 Ykk Corporation Side Release Buckle
JP2010263014A (ja) 2009-04-30 2010-11-18 Panasonic Corp 半導体装置
JP2012054417A (ja) * 2010-09-01 2012-03-15 Panasonic Corp 電子部品の実装構造体及びその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH10101906A (ja) 1996-10-03 1998-04-21 Shin Etsu Chem Co Ltd 液状エポキシ樹脂組成物の製造方法
JP2000188469A (ja) * 1998-12-22 2000-07-04 Nec Corp 半導体装置実装構造
JP2006199937A (ja) * 2004-12-15 2006-08-03 Tamura Kaken Co Ltd 導電性接着剤、これを用いた導電部及び電子部品モジュール
WO2010050185A1 (ja) 2008-10-27 2010-05-06 パナソニック株式会社 半導体の実装構造体およびその製造方法
JP2010272557A (ja) * 2009-05-19 2010-12-02 Panasonic Corp 電子部品実装方法および電子部品実装構造
WO2012042809A1 (ja) * 2010-09-27 2012-04-05 パナソニック株式会社 電子部品実装方法

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2017094537A1 (ja) * 2015-12-03 2017-06-08 ソニー株式会社 半導体チップ及び電子機器
US11048028B2 (en) 2015-12-03 2021-06-29 Sony Semiconductor Solutions Corporation Semiconductor chip and electronic apparatus for suppressing degradation of semiconductor chip
US11619772B2 (en) 2015-12-03 2023-04-04 Sony Semiconductor Solutions Corporation Semiconductor chip and electronic apparatus
JP2023523954A (ja) * 2020-04-30 2023-06-08 ツェットカーヴェー グループ ゲーエムベーハー Smt部品の浮動に対するバリア

Also Published As

Publication number Publication date
US9795036B2 (en) 2017-10-17
US20170374743A1 (en) 2017-12-28
CN104246997A (zh) 2014-12-24
JP6365841B2 (ja) 2018-08-01
KR20150023222A (ko) 2015-03-05
EP2849216A1 (en) 2015-03-18
CN104246997B (zh) 2017-09-08
TWI582915B (zh) 2017-05-11
US10412834B2 (en) 2019-09-10
US20150116970A1 (en) 2015-04-30
EP2849216B1 (en) 2018-10-24
EP2849216A4 (en) 2015-07-22
KR101975076B1 (ko) 2019-05-03
TW201401450A (zh) 2014-01-01
JPWO2013168352A1 (ja) 2015-12-24

Similar Documents

Publication Publication Date Title
JP6365841B2 (ja) 実装構造体とその製造方法
JP5204241B2 (ja) 半導体の実装構造体およびその製造方法
JP5093766B2 (ja) 導電性ボール等搭載半導体パッケージ基板の製造方法
JP6534122B2 (ja) 樹脂フラックスはんだペースト及び実装構造体
WO2016017076A1 (ja) 半導体実装品とその製造方法
JP2006186011A (ja) 電子部品実装方法および電子部品実装構造
JP2017080797A (ja) はんだペースト及びはんだ付け用フラックス及びそれを用いた実装構造体
JP2010272557A (ja) 電子部品実装方法および電子部品実装構造
JP5952849B2 (ja) フラックス及びソルダペースト
JP2010263014A (ja) 半導体装置
JP5560032B2 (ja) はんだ接合補強剤組成物、及びこれを用いた実装基板の製造方法
JP6124032B2 (ja) 実装構造体と実装構造体の製造方法
WO2018134860A1 (ja) 半導体実装品
JP2016087691A (ja) Pbフリーはんだ及び電子部品内蔵モジュール
JP4556631B2 (ja) 液状樹脂組成物、それを用いた半導体装置の製造方法及び半導体装置
JP6115762B2 (ja) 回路装置の製造方法
JP2007188943A (ja) はんだバンプ、はんだバンプの形成方法及び半導体装置
JP2010258173A (ja) 半導体パッケージ部品の実装方法と実装構造体
WO2021059851A1 (ja) 電子部品、電子部品の製造方法、実装構造体及び実装構造体の製造方法
JP2018181937A (ja) リペア性に優れる実装構造体
JP2010258172A (ja) 半導体パッケージ部品の実装方法と実装構造体

Legal Events

Date Code Title Description
121 Ep: the epo has been informed by wipo that ep was designated in this application

Ref document number: 13787864

Country of ref document: EP

Kind code of ref document: A1

ENP Entry into the national phase

Ref document number: 2014514363

Country of ref document: JP

Kind code of ref document: A

ENP Entry into the national phase

Ref document number: 20147024643

Country of ref document: KR

Kind code of ref document: A

WWE Wipo information: entry into national phase

Ref document number: 14396297

Country of ref document: US

WWE Wipo information: entry into national phase

Ref document number: 2013787864

Country of ref document: EP

NENP Non-entry into the national phase

Ref country code: DE