WO2013145765A1 - 撮像ユニット、撮像装置および撮像制御プログラム - Google Patents
撮像ユニット、撮像装置および撮像制御プログラム Download PDFInfo
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Definitions
- the present invention relates to an imaging unit, an imaging apparatus, and an imaging control program.
- Patent Literature Japanese Patent Application Laid-Open No. 2006-49361
- the dynamic range of the imaging unit has been limited to a narrow range.
- the imaging unit includes an imaging unit including a first group including one or more pixels and a second group including one or more pixels different from the pixels constituting the first group; And a control unit that causes the second group to perform charge accumulation a different number of times from the first group and output each pixel signal during a period in which the first group performs charge accumulation once.
- the imaging device includes the imaging unit described above.
- the imaging control program includes a first start step for starting charge accumulation in a first group including one or more pixels, and one or more pixels different from the pixels constituting the first group.
- a second start step for starting charge accumulation in the second group including, a second output step for terminating the charge accumulation of the second group and outputting a pixel signal before the first group completes charge accumulation;
- the computer After repeating the start step and the second output step a plurality of times, the computer is caused to execute a first output step for terminating the charge accumulation of the first group and outputting a pixel signal.
- An imaging device includes an imaging unit including a first group including one or more pixels and a second group including one or more pixels different from the pixels constituting the first group; A control unit for causing the second group to perform charge accumulation a plurality of times and outputting each pixel signal during a period in which the first group performs charge accumulation a plurality of times; and a pixel signal output from the first group And a calculation unit that calculates the pixel signal output from the second group differently.
- FIG. 1 is a cross-sectional view of a backside illuminating type MOS imaging device according to the present embodiment. It is a figure explaining the pixel arrangement
- FIG. 1 is a cross-sectional view of a back-illuminated image sensor 100 according to this embodiment.
- the imaging device 100 includes an imaging chip 113 that outputs a pixel signal corresponding to incident light, a signal processing chip 111 that processes the pixel signal, and a memory chip 112 that stores the pixel signal.
- the imaging chip 113, the signal processing chip 111, and the memory chip 112 are stacked, and are electrically connected to each other by a conductive bump 109 such as Cu.
- incident light is incident mainly in the positive direction of the Z axis indicated by the white arrow.
- the surface on the side where incident light is incident is referred to as a back surface.
- the left direction of the paper orthogonal to the Z axis is the X axis plus direction
- the front side of the paper orthogonal to the Z axis and the X axis is the Y axis plus direction.
- the coordinate axes are displayed so that the orientation of each figure can be understood with reference to the coordinate axes of FIG.
- the imaging chip 113 is a back-illuminated MOS image sensor.
- the PD layer 106 is disposed on the back side of the wiring layer 108.
- the PD layer 106 includes a plurality of PDs (photodiodes) 104 arranged two-dimensionally and a transistor 105 provided corresponding to the PD 104.
- a color filter 102 is provided on the incident light incident side of the PD layer 106 via a passivation film 103.
- the color filter 102 has a plurality of types that transmit different wavelength regions, and has a specific arrangement corresponding to each of the PDs 104. The arrangement of the color filter 102 will be described later.
- a set of the color filter 102, the PD 104, and the transistor 105 forms one pixel.
- a microlens 101 is provided on the incident light incident side of the color filter 102 corresponding to each pixel.
- the microlens 101 condenses incident light toward the corresponding PD 104.
- the wiring layer 108 includes a wiring 107 that transmits a pixel signal from the PD layer 106 to the signal processing chip 111.
- the wiring 107 may be multilayer, and a passive element and an active element may be provided.
- a plurality of bumps 109 are arranged on the surface of the wiring layer 108.
- the plurality of bumps 109 are aligned with the plurality of bumps 109 provided on the opposing surfaces of the signal processing chip 111, and the imaging chip 113 and the signal processing chip 111 are pressed and aligned.
- the bumps 109 are joined and electrically connected.
- a plurality of bumps 109 are arranged on the mutually facing surfaces of the signal processing chip 111 and the memory chip 112.
- the bumps 109 are aligned with each other, and the signal processing chip 111 and the memory chip 112 are pressurized, so that the aligned bumps 109 are joined and electrically connected.
- the bonding between the bumps 109 is not limited to Cu bump bonding by solid phase diffusion, and micro bump bonding by solder melting may be employed. Further, for example, about one bump 109 may be provided for one pixel group described later. Therefore, the size of the bump 109 may be larger than the pitch of the PD 104. Further, a bump larger than the bump 109 corresponding to the pixel region may be provided in a peripheral region other than the pixel region where the pixels are arranged.
- the signal processing chip 111 has TSVs (silicon through electrodes) 110 that connect circuits provided on the front and back surfaces to each other.
- the TSV 110 is preferably provided in the peripheral area.
- the TSV 110 may also be provided in the peripheral area of the imaging chip 113 and the memory chip 112.
- FIG. 2 is a diagram for explaining the pixel array and the unit group 131 of the imaging chip 113. In particular, a state where the imaging chip 113 is observed from the back side is shown. In the pixel area, 20 million or more pixels are arranged in a matrix. In the present embodiment, 16 pixels of adjacent 4 pixels ⁇ 4 pixels form one group. The grid lines in the figure indicate the concept that adjacent pixels are grouped to form a unit group 131.
- the unit group 131 includes four so-called Bayer arrays, which are composed of four pixels of green pixels Gb, Gr, blue pixels B, and red pixels R, vertically and horizontally.
- the green pixel is a pixel having a green filter as the color filter 102, and receives light in the green wavelength band of incident light.
- a blue pixel is a pixel having a blue filter as the color filter 102 and receives light in the blue wavelength band
- a red pixel is a pixel having a red filter as the color filter 102 and receiving light in the red wavelength band. Receive light.
- FIG. 3 is a circuit diagram corresponding to the unit group 131 of the imaging chip 113.
- a rectangle surrounded by a dotted line typically represents a circuit corresponding to one pixel. Note that at least some of the transistors described below correspond to the transistor 105 in FIG.
- the unit group 131 is formed of 16 pixels.
- the 16 PDs 104 corresponding to the respective pixels are respectively connected to the transfer transistors 302, and the gates of the transfer transistors 302 are connected to the TX wiring 307 to which transfer pulses are supplied.
- the TX wiring 307 is commonly connected to the 16 transfer transistors 302.
- each transfer transistor 302 is connected to the source of the corresponding reset transistor 303, and a so-called floating diffusion FD between the drain of the transfer transistor 302 and the source of the reset transistor 303 is connected to the gate of the amplification transistor 304.
- the drain of the reset transistor 303 is connected to a Vdd wiring 310 to which a power supply voltage is supplied, and the gate thereof is connected to a reset wiring 306 to which a reset pulse is supplied.
- the reset wiring 306 is commonly connected to the 16 reset transistors 303.
- each amplification transistor 304 is connected to a Vdd wiring 310 to which a power supply voltage is supplied.
- the source of each amplification transistor 304 is connected to the drain of each corresponding selection transistor 305.
- Each gate of the selection transistor is connected to a decoder wiring 308 to which a selection pulse is supplied.
- the decoder wiring 308 is provided independently for each of the 16 selection transistors 305.
- the source of each selection transistor 305 is connected to a common output wiring 309.
- the load current source 311 supplies current to the output wiring 309. That is, the output wiring 309 for the selection transistor 305 is formed by a source follower. Note that the load current source 311 may be provided on the imaging chip 113 side or on the signal processing chip 111 side.
- the PD 104 converts the incident light received into charges and accumulates them. Thereafter, when the transfer pulse is applied again without the reset pulse being applied, the accumulated charge is transferred to the floating diffusion FD, and the potential of the floating diffusion FD changes from the reset potential to the signal potential after the charge accumulation. .
- a selection pulse is applied to the selection transistor 305 through the decoder wiring 308, a change in the signal potential of the floating diffusion FD is transmitted to the output wiring 309 through the amplification transistor 304 and the selection transistor 305. Thereby, a pixel signal corresponding to the reset potential and the signal potential is output from the unit pixel to the output wiring 309.
- the reset wiring 306 and the TX wiring 307 are common to the 16 pixels forming the unit group 131. That is, the reset pulse and the transfer pulse are simultaneously applied to all 16 pixels. Therefore, all the pixels forming the unit group 131 start charge accumulation at the same timing and end charge accumulation at the same timing. However, the pixel signal corresponding to the accumulated electric charge is sequentially applied to each selection transistor 305 by a selection pulse, and is selectively output to the output wiring 309.
- the charge accumulation time can be controlled for each unit group 131.
- the other unit group 131 can be made to accumulate charges several times and output a pixel signal each time. Specific output control will be described later.
- FIG. 4 is a block diagram illustrating a functional configuration of the image sensor 100.
- the analog multiplexer 411 selects the 16 PDs 104 forming the unit group 131 in order, and outputs each pixel signal to the output wiring 309.
- the multiplexer 411 is formed on the imaging chip 113 together with the PD 104.
- the pixel signal output via the multiplexer 411 is supplied to the signal processing chip 111 by a signal processing circuit 412 that performs correlated double sampling (CDS) / analog / digital (A / D) conversion. D conversion is performed.
- CDS correlated double sampling
- a / D converted pixel signal is transferred to the demultiplexer 413 and stored in the pixel memory 414 corresponding to each pixel.
- Each of the pixel memories 414 has a capacity capable of storing a pixel signal corresponding to the maximum integration number described later.
- the demultiplexer 413 and the pixel memory 414 are formed in the memory chip 112.
- a / D conversion converts an input analog pixel signal into a 12-bit digital pixel signal.
- the signal processing circuit 412 connects 3-bit exponent digits corresponding to the number of integration described later, and delivers the 15-bit digital pixel signal to the demultiplexer 413 as a whole. Therefore, the pixel memory 414 stores a 15-bit digital pixel signal corresponding to one charge accumulation.
- the arithmetic circuit 415 processes the pixel signal stored in the pixel memory 414 and passes it to the subsequent image processing unit.
- the arithmetic circuit 415 may be provided in the signal processing chip 111 or may be provided in the memory chip 112.
- the connection for 1 group is shown in the figure, these actually exist for every group and operate
- the arithmetic circuit 415 may not exist for each group.
- one arithmetic circuit 415 may perform sequential processing while sequentially referring to the values of the pixel memory 414 corresponding to each group.
- FIG. 5 is a block diagram illustrating a configuration of the imaging apparatus according to the present embodiment.
- the imaging apparatus 500 includes a photographic lens 520 as a photographic optical system, and the photographic lens 520 guides a subject luminous flux incident along the optical axis OA to the imaging element 100.
- the photographing lens 520 may be an interchangeable lens that can be attached to and detached from the imaging apparatus 500.
- the imaging apparatus 500 mainly includes an imaging device 100, a system control unit 501, a drive unit 502, a photometry unit 503, a work memory 504, a recording unit 505, and a display unit 506.
- the photographing lens 520 is composed of a plurality of optical lens groups, and forms an image of a subject light flux from the scene in the vicinity of its focal plane.
- a single virtual lens arranged in the vicinity of the pupil is representatively shown.
- the drive unit 502 is a control circuit that executes charge accumulation control such as timing control and area control of the image sensor 100 in accordance with instructions from the system control unit 501. In this sense, it can be said that the drive unit 502 functions as an image sensor control unit that causes the image sensor 100 to perform charge accumulation and output a pixel signal.
- the driving unit 502 is combined with the imaging device 100 to form an imaging unit.
- the control circuit forming the driving unit 502 may be formed into a chip and stacked on the image sensor 100.
- the image sensor 100 delivers the pixel signal to the image processing unit 511 of the system control unit 501.
- the image processing unit 511 performs various image processing using the work memory 504 as a work space, and generates image data. For example, when generating image data in JPEG file format, compression processing is executed after white balance processing, gamma processing, and the like are performed.
- the generated image data is recorded in the recording unit 505, converted into a display signal, and displayed on the display unit 506 for a preset time.
- the photometric unit 503 detects the luminance distribution of the scene prior to a series of shooting sequences for generating image data.
- the photometry unit 503 includes, for example, an AE sensor having about 1 million pixels.
- the calculation unit 512 of the system control unit 501 receives the output of the photometry unit 503 and calculates the luminance for each area of the scene.
- the calculation unit 512 determines the shutter speed, aperture value, and ISO sensitivity according to the calculated luminance distribution.
- the arithmetic unit 512 further determines how many times charge accumulation is repeated in which pixel group region of the imaging chip 113 until the determined shutter speed is reached.
- the calculation unit 512 also executes various calculations for operating the imaging device 500.
- FIG. 6 is a diagram for explaining an example of a scene and area division.
- FIG. 6A shows a scene captured by the pixel area of the imaging chip 113. Specifically, this is a scene in which the shadow subject 601 and the intermediate subject 602 included in the indoor environment and the highlight subject 603 in the outdoor environment observed inside the window frame 604 are reflected simultaneously.
- charge accumulation is performed using the highlight part as a reference. When charge accumulation was performed with reference to the portion, whiteout occurred in the highlight portion.
- the dynamic range of the photodiode is insufficient for a scene having a large contrast between light and dark in order to output an image signal by charge accumulation uniformly in both the highlight portion and the shadow portion. Therefore, in this embodiment, the scene is divided into partial areas such as a highlight part and a shadow part, and the number of charge accumulations of the photodiodes corresponding to each area is made different from each other, thereby substantially expanding the dynamic range. Plan.
- FIG. 6B shows region division in the pixel region of the imaging chip 113.
- the calculation unit 512 analyzes the scene of FIG. 6A captured by the photometry unit 503, and divides the pixel region based on the luminance.
- the system control unit 501 causes the photometry unit 503 to execute a plurality of scene acquisitions while changing the exposure time, and the calculation unit 512 refers to the change in the distribution of the whiteout region and the blackout region, thereby changing the pixel region Determine the dividing line.
- the calculation unit 512 is divided into three areas, a shadow area 611, an intermediate area 612, and a highlight area 613.
- the division line is defined along the boundary of the unit group 131. That is, each divided area includes an integer number of groups. Then, the pixels of each group included in the same region perform charge accumulation and pixel signal output the same number of times within a period corresponding to the shutter speed determined by the calculation unit 512. If the region to which the region belongs is different, charge accumulation and pixel signal output are performed a different number of times.
- FIG. 7 is a diagram for explaining the charge accumulation control for each divided area according to the example of FIG.
- the calculation unit 512 determines the shutter speed T 0 from the output of the photometry unit 503. Further, as described above, the area is divided into the shadow area 611, the intermediate area 612, and the highlight area 613, and the number of charge accumulations is determined from the respective luminance information. The number of times of charge accumulation is determined so that the pixel is not saturated by charge accumulation per time. For example, the number of times of charge accumulation is determined based on the accumulation of 80% to 90% of charge that can be accumulated in one charge accumulation operation.
- the shadow area 611 is assumed to be once. That is, the determined shutter speed T 0 is matched with the charge accumulation time. Further, the number of charge accumulations in the intermediate region 612 is set to two. That is, once the charge storage time as T 0/2, to repeat charge accumulation twice during the shutter speed T 0. In addition, the number of charge accumulations in the highlight area 613 is four. That is, once the charge storage time as T 0/4, and repeats the charge storage 4 times during the shutter speed T 0.
- the driving unit 502 applies a transfer pulse to the pixels in the entire region. Then, a selection pulse is sequentially applied to the pixels in each group, and the respective pixel signals are output to the output wiring 309.
- the pixel memory 414 corresponding to the shadow area 611 stores one pixel signal
- the pixel memory 414 corresponding to the intermediate area 612 stores two pixel signals, respectively.
- the pixel memory 414 corresponding to 613 stores pixel signals for four times.
- the image processing unit 511 generates high dynamic range image data from this pixel signal. Specific processing will be described later.
- FIG. 8 is a diagram showing the relationship between the number of integrations and the dynamic range.
- a plurality of pixel signals corresponding to repeated charge accumulation are subjected to integration processing by the image processing unit 511 to form part of high dynamic range image data.
- the number of integrations is one, that is, based on the dynamic range of the region where charge accumulation is performed once, the dynamic range of the region where the number of integrations is two times, ie, where charge accumulation is performed twice and the output signal is integrated is expanded Is one stage. Similarly, if the number of integration is 4 times, it becomes 2 steps, and if it is 128 times, it becomes 7 steps. That is, in order to increase the dynamic range for n stages, 2 n output signals may be integrated.
- a 3-bit exponent digit indicating the number of integration is added to the image signal.
- the exponent digits are assigned in order, such as 000 for the integration number once, 001 for the second integration,.
- the image processing unit 511 refers to the exponent digit of each pixel signal received from the arithmetic circuit 415, and executes the integration process of the pixel signal when the referred result is an integration number of two or more. For example, when the number of integration is 2 (1 stage), the top 11 bits of the 12-bit pixel signals corresponding to the charge accumulation are added to the two pixel signals to obtain one 12-bit pixel signal. Generate. Similarly, when the number of integrations is 128 (7 stages), the upper 5 bits of the 12-bit pixel signals corresponding to charge accumulation are added to the 128 pixel signals to obtain one 12-bit pixel signal. Is generated. That is, the higher order bits obtained by subtracting the number of stages corresponding to the number of integrations from 12 are added together to generate one 12-bit pixel signal. Note that lower bits that are not subject to addition are removed.
- the luminance range giving gradation can be shifted to the high luminance side according to the number of integrations. That is, 12 bits are allocated to a limited range on the high luminance side. Therefore, a gradation can be given to an image area that has conventionally been overexposed.
- the image processing unit 511 performs re-quantization processing on the basis of the maximum luminance pixel and the minimum luminance pixel in order to make the entire region 12-bit image data while maintaining the obtained gradation as much as possible. Specifically, quantization is performed by performing gamma conversion so that gradation is maintained more smoothly. By processing in this way, high dynamic range image data can be obtained.
- the number of integrations is not limited to the case where a 3-bit exponent digit is added to the pixel signal as described above, and may be described as accompanying information separate from the pixel signal.
- the number of integrations may be acquired during the addition process by omitting the exponent digits from the pixel signals and counting the number of pixel signals stored in the pixel memory 414 instead.
- the number of output bits may be increased in accordance with the upper limit number of integrations with respect to the number of bits of the pixel signal.
- the upper limit number of times of integration is determined to be 16 times (4 stages)
- the entire area may be 16-bit image data for a 12-bit pixel signal.
- FIG. 9 is a flowchart showing processing of the photographing operation. The flow is started when the power of the imaging apparatus 500 is turned on.
- step S101 the system control unit 501 waits until the switch SW1, which is a shooting preparation instruction, is pressed down. If the depression of the switch SW1 is detected, the process proceeds to step S102.
- step S102 the system control unit 501 performs photometry processing. Specifically, the output of the photometry unit 503 is obtained, and the calculation unit 512 calculates the luminance distribution of the scene. Then, the process proceeds to step S103, and the shutter speed, the area division, the number of integrations, etc. are determined as described above.
- step S104 the process proceeds to step S104 and waits until the switch SW2 that is a photographing instruction is depressed. At this time, if the elapsed time exceeds a predetermined time Tw (YES in step S105), the process returns to step S101. If the depression of the switch SW2 is detected before exceeding Tw (NO in step S105), the process proceeds to step S106.
- step S106 the drive unit 502 that has received an instruction from the system control unit 501 executes the charge accumulation process and the signal read process described with reference to FIG. When all the signals have been read, the process proceeds to step S107, where the image processing described with reference to FIG. 8 is executed, and a recording process for recording the generated image data in the recording unit is executed.
- step S108 it is determined whether or not the power supply of the imaging apparatus 500 is turned off. If the power is not turned off, the process returns to step S101. If the power is turned off, the series of photographing operation processing is terminated.
- FIG. 10 is a block diagram showing a specific configuration as an example of the signal processing chip 111.
- the demultiplexer 413 and the pixel memory 414 are formed in the memory chip 112 .
- the signal processing chip 111 is formed.
- the signal processing chip 111 has a function of the driving unit 502.
- the signal processing chip 111 includes a sensor control unit 441, a block control unit 442, a synchronization control unit 443, a signal control unit 444 as a shared control function, and a drive control unit 420 that performs overall control of these control units.
- the drive control unit 420 converts an instruction from the system control unit 501 into a control signal that can be executed by each control unit, and delivers the control signal to each control signal.
- the sensor control unit 441 performs transmission control of control pulses that are transmitted to the imaging chip 113 and are related to charge accumulation and charge readout of each pixel. Specifically, the sensor control unit 441 controls the start and end of charge accumulation by sending a reset pulse and a transfer pulse to the target pixel, and sends a selection pulse to the readout pixel. A pixel signal is output to the output wiring 309.
- the block control unit 442 executes transmission of a specific pulse for specifying the unit group 131 to be controlled, which is transmitted to the imaging chip 113.
- the divided area can include a plurality of unit groups 131 adjacent to each other. These unit groups 131 belonging to the same area form one block. Pixels included in the same block start charge accumulation at the same timing and end charge accumulation at the same timing. Therefore, the block control unit 442 plays a role of blocking the unit group 131 by sending a specific pulse to the target unit group 131 based on the designation from the drive control unit 420.
- the transfer pulse and the reset pulse received by each pixel via the TX wiring 307 and the reset wiring 306 are the logical product of each pulse sent by the sensor control unit 441 and a specific pulse sent by the block control unit 442. In this way, the charge accumulation control described with reference to FIG. 7 is realized by controlling each region as an independent block. Blocking designation from the drive control unit will be described in detail later.
- the synchronization control unit 443 sends a synchronization signal to the imaging chip 113.
- Each pulse becomes active in the imaging chip 113 in synchronization with the synchronization signal. For example, by adjusting the synchronization signal, random control, thinning control, and the like that control only specific pixels of pixels belonging to the same unit group 131 are realized.
- the signal control unit 444 is mainly responsible for timing control for the A / D converter 412b.
- the pixel signal output via the output wiring 309 is input to the A / D converter 412b via the CDS circuit 412a and the multiplexer 411.
- the A / D converter 412b is controlled by the signal control unit 444 and converts the input pixel signal into a digital signal.
- the pixel signal converted into the digital signal is transferred to the demultiplexer 413 and stored as a pixel value of digital data in the pixel memory 414 corresponding to each pixel.
- the signal processing chip 111 stores block classification information about which unit group 131 is combined to form a block, and accumulation count information about how many times charge accumulation is repeated in each formed block. And a timing memory 430 as an accumulation control memory.
- the timing memory 430 is configured by a flash RAM, for example.
- which unit group is combined to form a block is determined by the system control unit 501 based on the detection result of the luminance distribution detection of the scene executed prior to a series of shooting sequences. .
- the determined block is divided into, for example, a first block, a second block, etc., and is defined by which unit group 131 each block includes.
- the drive control unit 420 receives this block division information from the system control unit 501 and stores it in the timing memory 430.
- the system control unit 501 determines how many times each block repeats charge accumulation based on the detection result of the luminance distribution.
- the drive control unit 420 receives this accumulation count information from the system control unit 501 and stores it in the timing memory 430 in pairs with the corresponding block division information.
- the drive control unit 420 can independently execute a series of charge accumulation control with reference to the timing memory 430 sequentially. That is, once the drive control unit 420 receives a shooting instruction signal from the system control unit 501 in one image acquisition control, thereafter, the drive control unit 420 accumulates without receiving an instruction from the system control unit 501 for each pixel control. Control can be completed.
- the drive control unit 420 receives from the system control unit 501 block classification information and accumulation count information that are updated based on photometric results (luminance distribution detection results) that are executed in synchronization with the imaging preparation instruction, and the timing memory 430.
- the stored contents are updated as appropriate.
- the drive control unit 420 updates the timing memory 430 in synchronization with the shooting preparation instruction or the shooting instruction.
- the drive control unit 420 refers not only to the charge accumulation control for the imaging chip 113 but also to the timing memory 430 in the execution of the read control.
- the drive control unit 420 refers to the accumulation count information of each block and stores the pixel signal output from the demultiplexer 413 at the corresponding address of the pixel memory 414.
- the drive control unit 420 reads the target pixel signal from the pixel memory 414 in accordance with a delivery request from the system control unit 501 and delivers it to the image processing unit 511.
- the pixel memory 414 has a memory space that can store a pixel signal corresponding to the maximum number of times of accumulation for each pixel, and stores each pixel signal corresponding to the number of times of accumulation as a pixel value. For example, when charge accumulation is repeated four times in a certain block, the pixels included in the block output pixel signals for four times, and therefore, the memory space of each pixel on the pixel memory 414 has four Pixel values are stored.
- the drive control unit 420 When the drive control unit 420 receives a delivery request for requesting a pixel signal of a specific pixel from the system control unit 501, the drive control unit 420 designates the address of the specific pixel on the pixel memory 414 and stores all the pixels stored therein. The signal is read and delivered to the image processing unit 511. For example, when four pixel values are stored, all four pixel values are sequentially transferred, and when only one pixel value is stored, the pixel values are transferred.
- the drive control unit 420 can read out the pixel signal stored in the pixel memory 414 to the arithmetic circuit 415 and cause the arithmetic circuit 415 to execute the above-described integration process.
- the integrated pixel signal is stored in the target pixel address of the pixel memory 414.
- the target pixel address may be provided adjacent to the address space before the integration process, or may be the same address so as to overwrite the pixel signal before the integration process. Moreover, you may provide the exclusive space which stores the pixel value of each pixel after an integration process collectively.
- the drive control unit 420 When receiving a delivery request for requesting a pixel signal of a specific pixel from the system control unit 501, the drive control unit 420 delivers the pixel signal after integration processing to the image processing unit 511 depending on the mode of the delivery request. Can do. Of course, the pixel signals before and after the integration process can be delivered together.
- the pixel memory 414 is provided with a data transfer interface that transmits pixel signals in accordance with a delivery request.
- the data transfer interface is connected to a data transfer line connected to the image processing unit 511.
- the data transfer line is constituted by a data bus of the bus lines, for example.
- the delivery request from the system control unit 501 to the drive control unit 420 is executed by address designation using the address bus.
- the pixel signal transmission by the data transfer interface is not limited to the addressing method, and various methods can be adopted. For example, when performing data transfer, a double data rate method in which processing is performed using both rising and falling edges of a clock signal used for synchronization of each circuit may be employed. Further, it is possible to adopt a burst transfer method in which data is transferred all at once by omitting a part of the procedure such as addressing and the like, and the speed is increased. Further, a bus system using a line in which a control unit, a memory unit, and an input / output unit are connected in parallel, or a serial system that transfers data one bit at a time can be combined.
- the image processing unit 511 can receive only the necessary pixel signals, so that image processing can be completed at high speed, particularly when a low-resolution image is formed.
- the image processing unit 511 does not have to execute the integration process, so that the image processing can be speeded up by the function sharing and the parallel processing.
- FIG. 11 is an explanatory diagram for explaining the flow of pixel signals transmitted from the imaging chip 113 to the signal processing chip 111.
- the unit group 131 is composed of 2048 pixels of one row of 32 pixels and one column of 64 pixels.
- one unit group 131 has one output wiring 309. However, in the example of FIG. One unit group 131 has 16 output wires. Each output wiring 309 branches into two output wirings 309 a and 309 b in the vicinity of the junction between the imaging chip 113 and the signal processing chip 111.
- connection portions On the signal processing chip 111 side, two input wirings 409a and 409b are provided corresponding to the branched output wirings 309a and 309b, respectively. Therefore, a bump 109a for joining the output wiring 309a and the input wiring 409a and a bump 109b for joining the output wiring 309b and the input wiring 409b are provided in the joint portion.
- the connection portions redundantly, it is possible to reduce the possibility of causing pixel defects due to poor bonding.
- the number of branches is not limited to two but may be plural.
- the electrical connection between the output wiring and the input wiring is not limited to the bump coupling, and when an electrical connection that may cause a connection failure is adopted, it is preferable to configure the connection portion in this manner in a redundant manner. .
- switches 461a and 461b are interposed before being input to the CDS circuit 412a.
- the switches 461a and 461b are controlled by the drive control unit 420 as switches 461 interlocking with each other. Specifically, the drive control unit 420 normally turns on the switch 461a to enable transmission of the pixel signal of the input wiring 409a, and turns off the switch 461b to disable transmission of the input wiring 409b.
- the drive control unit 420 determines that a connection failure has occurred in the bump 109a
- the switch 461a is turned off to disable transmission of the input wiring 409a
- the switch 461b is turned on to turn on the input wiring 409b. Is effective. In this way, it can be expected that only a normal pixel signal is input to the CDS circuit 412a by the interlocking operation of the switch 461 in which any wiring is connected and any wiring is not connected.
- the connection failure determination of the bump 109 can be performed by the drive control unit 420 or the system control unit 501.
- the connection failure determination is made based on the output result of the pixel signal that has passed through the input wiring 409. Specifically, for example, when the system control unit 501 determines that there is a difference equal to or greater than a predetermined threshold value compared with each pixel signal output from the output wiring 309 adjacent to both sides, Judge that a defect has occurred. Whether or not abnormal values continue in the column direction may be added to the criterion.
- the drive control unit 420 receives the determination result of the system control unit 501 and switches the switch 461 of the corresponding input wiring 409. The connection failure determination may not be performed sequentially in accordance with the photographing operation.
- the drive control unit 420 can store the determination result in the timing memory 430. In this case, the drive control unit 420 controls the switch 461 while referring to the timing memory 430 when reading out the pixel signal.
- the photometric unit 503 has been described as a configuration including an independent AE sensor.
- the photometry process can also be performed using a pre-image output from the image sensor 100 prior to the main photographing process performed upon receiving a photographing instruction from the user.
- One pixel for photometry may be provided in the unit group 131, for example.
- the pixel array of FIG. 2 by setting the color filter of the pixel at the left end and the upper end of the unit group 131 to be a transparent filter or no filter, the pixel can be used as a photometric pixel. Since such a pixel can receive visible light in a wide wavelength band, it is suitable for detecting the luminance distribution of a scene.
- the photometric pixels may be made independent of the unit group, and the photometric pixels may be gathered to form a unit group. If comprised in this way, the drive part 502 can control charge accumulation
- the example in which the determined shutter speed T 0 and the one-time charge accumulation time of the shadow area are matched has been described, but for example, for the shadow area during the determined shutter speed T 0 , However, it may be controlled to repeat charge accumulation twice.
- the luminance range that gives the gradation is shifted to the high luminance side according to the number of integrations.
- Such processing is not performed on the pixel signal from the shadow area. That is, the value of the pixel signal due to one charge accumulation in the shadow region (charge accumulation time is T 0/2 ) is small and does not saturate from the 12-bit range even if two times are added. It is not necessary.
- imaging element 101 microlens, 102 color filter, 103 passivation film, 104 PD, 105 transistor, 106 PD layer, 107 wiring, 108 wiring layer, 109 bump, 110 TSV, 111 signal processing chip, 112 memory chip, 113 imaging Chip, 131 unit group, 302 transfer transistor, 303 reset transistor, 304 amplification transistor, 305 selection transistor, 306 reset wiring, 307 TX wiring, 308 decoder wiring, 309 output wiring, 310 Vdd wiring, 311 load current source, 409 input wiring 411 multiplexer, 412 signal processing circuit, 413 demultiplexer, 414 pixel memory, 415 arithmetic circuit, 420 drive control Unit, 430 timing memory, 441 sensor control unit, 442 block control unit, 443 synchronization control unit, 444 signal control unit, 461 switch, 500 imaging device, 501 system control unit, 502 drive unit, 503 photometry unit, 504 work memory, 505 recording unit, 506 display unit, 511 image processing unit,
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Abstract
Description
[先行技術文献]
[特許文献]
[特許文献1] 特開2006-49361号公報
第1グループに複数回の電荷蓄積を実行させている期間に、第2グループに複数回の電荷蓄積を実行させて各々の画素信号を出力させる制御部と、第1グループから出力させた画素信号の処理と、第2グループから出力させた画素信号の処理とを異ならせて演算する演算部とを備える。
Claims (26)
- 1つ以上の画素を含む第1グループと、前記第1グループを構成する画素とは異なる画素を1つ以上含む第2グループとを含む撮像部と、
前記第1グループに1回の電荷蓄積を実行させている期間に、前記第2グループに前記第1グループとは異なる回数の電荷蓄積を実行させて各々の画素信号を出力させる制御部と
を備える撮像ユニット。 - 前記制御部は、前記第1グループに1回の電荷蓄積を実行させている期間に、前記第2グループに複数回の電荷蓄積を実行させて各々の画素信号を出力させる請求項1に記載の撮像ユニット。
- 前記制御部は、前記第1グループの電荷蓄積が開始されるよりも前に実行される測光結果に基づいて、前記第2グループに実行させる電荷蓄積の回数を決定する請求項1または2に記載の撮像ユニット。
- 前記制御部は、前記第2グループで実行される各々の電荷蓄積により前記第2グループを構成する画素が飽和しないように前記回数を決定する請求項3に記載の撮像ユニット。
- 前記画素信号は、電荷蓄積の回数に関するデータを含む請求項1から4のいずれか1項に記載の撮像ユニット。
- 前記撮像部は、前記第1グループを構成する画素の画素信号を順次出力する共通の第1出力配線と、前記第2グループを構成する画素の画素信号を順次出力する、前記第1出力配線とは独立した共通の第2出力配線を有する請求項1から5のいずれか1項に記載の撮像ユニット。
- 前記撮像部を含む撮像チップと、前記画素信号を処理する処理回路を含む信号処理チップとが、積層構造により電気的に接続されている請求項1から6のいずれか1項に記載の撮像ユニット。
- 前記信号処理チップは、前記第2グループを含む各グループに実行させる、予め決定された電荷蓄積の回数に関する情報を格納する蓄積制御メモリを有する請求項7に記載の撮像ユニット。
- 前記蓄積制御メモリに格納された前記情報は、測光結果に基づいて更新される請求項8に記載の撮像ユニット。
- 前記蓄積制御メモリに格納された前記情報は、ユーザによる撮像準備指示に同期して更新される請求項8または9に記載の撮像ユニット。
- 前記制御部は、前記蓄積制御メモリを参照しつつ前記撮像部の各グループに対する電荷蓄積および前記画素信号の読み出しを制御する請求項8から10のいずれか1項に記載の撮像ユニット。
- 前記信号処理チップは、前記画素信号を格納する画素メモリを有する請求項7から11のいずれか1項に記載の撮像ユニット。
- 前記画素信号を格納する画素メモリを含むメモリチップも積層構造により電気的に接続されている請求項7から11のいずれか1項に記載の撮像ユニット。
- 前記制御部は、前記第2グループを含むグループ群のうちの指定グループに対する外部回路からの引渡要求に従って、前記指定グループの画素信号を前記画素メモリから読み出して画像処理部へ引き渡す請求項12または13に記載の撮像ユニット。
- 前記引渡要求に従って前記画素信号を伝送するデータ転送インタフェースを備える請求項14に記載の撮像ユニット。
- 前記データ転送インタフェースによる前記画素信号の伝送は、ダブルデータレート方式、アドレス指定方式、バースト転送方式、バス方式、シリアル方式の少なくともいずれかを採用する請求項15に記載の撮像ユニット。
- 前記制御部は、複数回の電荷蓄積に対する各々の画素信号が前記画素メモリに格納されている場合には、当該各々の画素信号を前記画像処理部へ引き渡す請求項14から16のいずれか1項に記載の撮像ユニット。
- 前記信号処理チップは、複数回の電荷蓄積に対する各々の画素信号を積算処理する演算部を有し、
前記制御部は、複数回の電荷蓄積に対する各々の画素信号が前記画素メモリに格納されている場合には、前記演算部を用いて積算処理した画素信号を前記画像処理部へ引き渡す請求項14から16のいずれか1項に記載の撮像ユニット。 - 前記撮像チップは、前記画素信号を出力する出力配線を有し、
前記信号処理チップは、前記出力配線からの前記画素信号を受けて前記処理回路へ伝送する入力配線を有し、
前記出力配線と前記入力配線は、前記撮像チップと前記信号処理チップの接合部においてそれぞれ複数に分岐して互いに接合されている請求項7から18のいずれか1項に記載の撮像ユニット。 - 前記信号処理チップは、前記入力配線の複数に分岐した箇所に、いずれかの配線を接続状態とし、いずれかの配線を非接続状態とするスイッチを有する請求項19に記載の撮像ユニット。
- 前記制御部は、前記入力配線を通過した前記画素信号の出力結果に基づいて前記スイッチの接続状態および非接続状態を切り替える請求項20に記載の撮像ユニット。
- 前記処理チップは、相関二重サンプリング回路を有し、
前記スイッチを通過した前記画素信号は、前記相関二重サンプリング回路に入力される請求項20または21に記載の撮像ユニット。 - 前記出力配線は、前記第1グループおよび前記第2グループを含むグループ群のそれぞれに対して、複数設けられた請求項19から22のいずれか1項に記載の撮像ユニット。
- 請求項1から23のいずれか1項に記載の撮像ユニットを備える撮像装置。
- 1つ以上の画素を含む第1グループに電荷蓄積を開始させる第1開始ステップと、
前記第1グループを構成する画素とは異なる画素を1つ以上含む第2グループに電荷蓄積を開始させる第2開始ステップと、
前記第1グループが電荷蓄積を完了する以前に、前記第2グループの電荷蓄積を終了させて画素信号を出力させる第2出力ステップと、
前記第2開始ステップと前記第2出力ステップを複数回繰り返した後に、前記第1グループの電荷蓄積を終了させて画素信号を出力させる第1出力ステップと
をコンピュータに実行させる撮像制御プログラム。 - 1つ以上の画素を含む第1グループと、前記第1グループを構成する画素とは異なる画素を1つ以上含む第2グループとを含む撮像部と、
前記第1グループに複数回の電荷蓄積を実行させている期間に、前記第2グループに複数回の電荷蓄積を実行させて各々の画素信号を出力させる制御部と、
前記第1グループから出力させた前記画素信号の処理と、前記第2グループから出力させた前記画素信号の処理とを異ならせて演算する演算部と
を備える撮像装置。
Priority Applications (15)
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JP2014507447A JP6277954B2 (ja) | 2012-03-30 | 2013-03-28 | 撮像ユニット、撮像装置および撮像制御プログラム |
EP13768038.5A EP2833620B1 (en) | 2012-03-30 | 2013-03-28 | Image pickup unit, image pickup device and image pickup control program |
BR112014024330-1A BR112014024330B1 (pt) | 2012-03-30 | 2013-03-28 | Unidade de formação de imagem, aparelho de formação de imagem e programa de controle de formação de imagem |
CN201910490295.8A CN110149485B (zh) | 2012-03-30 | 2013-03-28 | 拍摄单元及拍摄装置 |
CN201380018222.XA CN104247401B (zh) | 2012-03-30 | 2013-03-28 | 拍摄元件以及拍摄装置 |
RU2014143824A RU2666761C2 (ru) | 2012-03-30 | 2013-03-28 | Модуль формирования изображений, устройство формирования изображений и управляющая программа для формирования изображений |
CN201910490680.2A CN110177227B (zh) | 2012-03-30 | 2013-03-28 | 拍摄单元、拍摄装置及拍摄控制程序 |
EP19151551.9A EP3490247B1 (en) | 2012-03-30 | 2013-03-28 | Imaging unit and imaging apparatus |
US14/500,030 US9571767B2 (en) | 2012-03-30 | 2014-09-29 | Imaging unit, imaging apparatus, and computer readable medium storing thereon an imaging control program |
IN8606DEN2014 IN2014DN08606A (ja) | 2012-03-30 | 2014-10-14 | |
US15/401,683 US9967480B2 (en) | 2012-03-30 | 2017-01-09 | Imaging unit, imaging apparatus, and computer readable medium storing thereon an imaging control program |
US15/946,168 US10652485B2 (en) | 2012-03-30 | 2018-04-05 | Imaging unit, imaging apparatus, and computer readable medium storing thereon an imaging control program |
US16/844,231 US11082646B2 (en) | 2012-03-30 | 2020-04-09 | Imaging unit, imaging apparatus, and computer readable medium storing thereon an imaging control program |
US17/371,751 US11743608B2 (en) | 2012-03-30 | 2021-07-09 | Imaging unit, imaging apparatus, and computer readable medium storing thereon an imaging control program |
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