WO2013127045A1 - 一种用于三维集成混合键合结构及其键合方法 - Google Patents

一种用于三维集成混合键合结构及其键合方法 Download PDF

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Publication number
WO2013127045A1
WO2013127045A1 PCT/CN2012/001558 CN2012001558W WO2013127045A1 WO 2013127045 A1 WO2013127045 A1 WO 2013127045A1 CN 2012001558 W CN2012001558 W CN 2012001558W WO 2013127045 A1 WO2013127045 A1 WO 2013127045A1
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bonding
substrate
metal
adhesion layer
dielectric adhesion
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PCT/CN2012/001558
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English (en)
French (fr)
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于大全
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江苏物联网研究发展中心
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Definitions

  • the present invention relates to a hybrid bonding structure and a bonding method thereof, and more particularly to a method for dimensionally integrating a hybrid bonding structure and a bonding method thereof, and belongs to the technical field of integrated circuits.
  • the core technologies of 3D integrated circuits include TSV (through-silicon via) fabrication, wafer thinning,
  • Bonding technologies include chip-to-chip, chip-to-wafer, and wafer-to-wafer bonding.
  • the electrical interconnection has two materials, one is a metal bump, such as Cu, Au, etc.; the other is a solder bump interconnect, such as Sn, In, etc.
  • the advantage of three-dimensional integrated circuits using metal bump interconnects is that a small interconnect pitch can be obtained, Cu-Cu bump bonding can achieve excellent electrical performance and reliability; the disadvantage is that metal bumps are required to be very high. Flatness usually requires a higher bonding temperature (>300 ° C) and a special surface treatment to remove oxides from the metal surface. The researchers have done a lot to reduce the bonding temperature. A representative study is Surface Activated Bonding (SAB) developed by the University of Tokyo, Japan. Through CMP (Chemical Mechanical Polishing) planarization, a clean metal surface is obtained by dry etching, and the bonding process is completed under high vacuum.
  • SAB Surface Activated Bonding
  • solder interconnects compared to metal bumps
  • the solder liquid/solid reaction can reduce the flatness of the bonding interface.
  • K. Sakuma, R S. Andry, CK Tsang, SL Wright, et al""3D Chip-Stacking Technology with Through-Silicon Vias and Low-Volume Lead-free Interconnections IBM J. RES. & DEV. 52(6), 2008, p611-631 o Plating bumps, special Because the copper pillar solder bump has good electrical performance and reliability, and can meet the fine pitch and low cost requirements, it is favored by the industry. Since 3D integration often requires multi-layer chip (wafer) stacking, it needs to be guaranteed.
  • transient liquid phase (TLP) bonding applications are valued.
  • TLP transient liquid phase
  • the so-called transient liquid phase bonding refers to low melting point.
  • ⁇ intermetallic compound
  • the object of the present invention is to overcome the deficiencies in the prior art, and to provide a three-dimensional integrated hybrid bonding structure and a bonding method thereof, which are compact in structure, convenient in process operation, and improved in bonding reliability.
  • the three-dimensional integrated hybrid bonding structure includes a first substrate; the first substrate is provided with a bonding interconnection metal electrically connected to the first substrate, The other end of the bonding interconnect metal corresponding to the first substrate is recessed to form a cavity, and the end of the bonding interconnect metal corresponding to the edge of the cavity forms a top edge of the bump; the first substrate correspondingly forms a bonding interconnection
  • the surface of the metal is covered with a first dielectric adhesion layer that surrounds the bond interconnect metal and the height of the first dielectric adhesion layer is lower than the height of the bond interconnect metal.
  • the bonding interconnect metal is a high temperature bonding metal.
  • the material of the high temperature bonding metal is one or more of Cu, Ni, Al, Pt, Pd or Au.
  • the bonding interconnect metal comprises a high temperature bonding metal and a low melting point solder at one end of the high temperature bonding metal, and the high temperature bonding metal in the bonding interconnection metal is correspondingly connected to the first substrate and has a low melting point
  • the end of the solder is recessed to form a cavity; the height of the first dielectric adhesion layer is lower than the height of the low melting point solder forming the end of the cavity.
  • the low melting point solder is a tin based alloy or an indium based alloy.
  • the material of the first dielectric adhesion layer includes BCB, SU-8, PI polymer or SiO 2 .
  • the first substrate is correspondingly coupled to the second bonding body by a bonding interconnection metal
  • the second bonding body includes a second substrate
  • the surface of the second substrate is provided with a soldering electrode electrically connected to the second substrate a second substrate corresponding to the surface of the second substrate to cover the second dielectric adhesion layer
  • the bonding interconnection metal is in contact with the pad through the top edge of the bump, and is tightly combined under the required temperature and pressure
  • the first dielectric adhesive layer is bonded to the second dielectric adhesive layer and joined together.
  • the material of the pad is a high temperature metal or a low melting point solder.
  • the material of the second dielectric adhesion layer includes BCB, SU-8, PI polymer or SiO 2 .
  • the material of the second substrate comprises silicon.
  • a bonding method for three-dimensionally integrating a hybrid bonding structure comprising the steps of: a, providing a first bonding body, the end of the first bonding body correspondingly bonding the interconnecting metal forms a concave Cavity and top edge of the bump;
  • the second bonding body includes a pad and a second dielectric adhesion layer; c. bonding the bonding metal to the end portion of the top edge of the bump and the second bonding body Pad positioning contact;
  • the end of the bonding interconnect metal corresponding to the top edge of the bump is in close contact with the pad, and the first dielectric adhesion layer and the second bond on the first bonding body The second dielectric adhesion layer on the body is bonded together.
  • the step a includes the following steps:
  • Al providing a first substrate, and fabricating a seed layer electrically connected to the first substrate on a surface of the first substrate;
  • A2 coating a surface of the first substrate corresponding to the surface of the seed layer with a first photoresist layer, and performing photolithography and development exposure to form a desired pattern
  • A3 forming a bump material of a desired twist and shape on the first substrate to form a bonding interconnect metal
  • A4 in addition to the first photoresist layer, and etching a corresponding bare seed layer on the first substrate; a5, forming a first dielectric adhesion layer on the first substrate, the first dielectric An adhesive layer covering a surface of the first substrate and covering a top edge of the bump of the bonding interconnect metal end;
  • A6 removing the first dielectric adhesion layer covering the top edge of the bump of the bonding interconnect metal end by ion etching, and making the first dielectric adhesion layer have a lower degree than the height of the top edge of the bump To form the desired first bond.
  • the second dielectric adhesion layer is overlaid on the first substrate and the bonding interconnect metal by silicone.
  • the shape and the bump material which are electroplated to form a desired height include a high temperature metal or a low melting point solder.
  • a first substrate is provided with a bonding interconnection metal electrically connected to the first substrate, and the bonding interconnection metal is recessed to form a cavity corresponding to the other end connected to the first substrate, and the key Forming a top edge of the bump corresponding to the edge of the interconnecting cavity; forming a surface of the first substrate corresponding to the bonding interconnect metal is covered with a first dielectric adhesive layer, the first dielectric adhesive layer Enclosing the bonding interconnect metal and the height of the first dielectric adhesion layer is lower than the height of the top edge of the bump; when bonding the bonding metal to the pad by bonding, the height of the first dielectric adhesion layer is lower than The top edge of the bump, when bonded under pressure, the top contact of the bump with the pad can block the dielectric adhesive layer from entering the surface of the bonding interconnect metal and the pad, thereby avoiding breakage and Reliability issues; compact structure and easy process operation.
  • Figure 1 is a schematic view of the structure of the present invention.
  • FIG. 2 is another schematic structural view of a bonded interconnect metal of the present invention.
  • FIG. 3 is a cross-sectional view showing a specific step of forming a bonding interconnection metal according to the present invention, wherein: FIG. 3 is a cross-sectional view after electroplating to form a bonding interconnection metal.
  • FIG 4 is a cross-sectional view after the photoresist layer is removed and the seed layer is etched.
  • Figure 5 is a cross-sectional view showing the first dielectric adhesion layer.
  • Fig. 6 is a cross-sectional view showing the first bonding body.
  • FIG. 7 to 9 are cross-sectional views showing specific steps of bonding the second bonding body of the present invention, wherein:
  • Fig. 7 is a cross-sectional view showing the first bonding body and the second bonding body.
  • Figure 8 is a cross-sectional view of the bump being brought into contact with the pad.
  • Fig. 9 is a cross-sectional view showing the bonding of the first bonding body and the second bonding body.
  • FIG. 10 to FIG. 12 are cross-sectional views showing specific steps of bonding the second bonding body of the present invention, wherein: FIG. 10 is a cross-sectional view showing the first bonding body and the second bonding body.
  • Figure 11 is a cross-sectional view of the bump being brought into contact with the disk.
  • Figure 12 is a cross-sectional view showing the first bonding body bonded to the second bonding body.
  • the present invention includes a first bonding body 1 including a first substrate 10;
  • the bottom 10 is provided with a bonding interconnection metal electrically connected to the first substrate 10, and the other end portion of the bonding interconnection metal corresponding to the first substrate 10 is recessed to form a cavity 31, that is, at the bonding
  • the end portion of the metal corresponding to the cavity 31 is formed with a bump top edge 60, and the surface of the first substrate 10 corresponding to the bonding interconnect metal is covered with the first dielectric adhesion layer 20, the first dielectric adhesion Layer 20 surrounds the bonding interconnect metal and the height of first dielectric adhesion layer 20 is lower than the height of the bonding interconnect metal ends; that is, the height of first dielectric adhesion layer 20 is lower than bump top edge 60.
  • FIG. 1 and 2 respectively show different structures of bonded interconnect metal, wherein the bonded interconnect metal in FIG. 1 all uses high temperature bonding metal 30, and the bonded interconnect metal in FIG. 2 includes high temperature bonded metal 30.
  • the low-melting-point material bonding body 40 located at the end of the high-temperature bonding metal 30 forms a cavity 31 by indentation at the end of the low-melting-point material bonding body 40.
  • the height of the first dielectric adhesive layer 20, the low melting point solder 40 forms the height of the end of the cavity 31.
  • the material of the high temperature bonding metal 30 is one or more of Cu, Ni, Al, Pt, Pd, or Au.
  • the low melting point solder 40 is a tin based alloy or an indium based alloy.
  • the material of the first dielectric adhesion layer 20 includes BCB, SU-8, PI polymer or SiO 2 .
  • the second bonding body 2 includes a second substrate 70, the surface of which is provided with pads 50, the pads 50 are electrically connected to the second substrate 70, and the material of the second substrate 70 comprises silicon.
  • the surface of the second substrate 70 corresponding to the pad 50 is covered with the second dielectric adhesion layer 25, and the height relationship between the pad 50 and the second dielectric adhesion layer 25 should be the same with the top edge 60 of the bump.
  • the height relationship between the dielectric adhesion layers 20 corresponds to avoid the first dielectric adhesion layer 20 or the second dielectric adhesion layer 25 when the bond between the top edge 60 of the bump and the pad 50 is bonded.
  • the first dielectric adhesion layer 20 or the second dielectric adhesion layer 25 is interposed therebetween so as not to cause an open circuit and reliability problem.
  • the height of the pad 50 is not higher than the height of the second dielectric adhesion layer 25, and FIG. 9 is that the height of the pad 50 is the same as the height of the second dielectric adhesion layer 25.
  • FIG. 12 is a structural diagram of the pad 50 having a height lower than that of the second dielectric adhesion layer 25.
  • the pad 50 may be a high temperature bonding metal, a low melting point solder or a combination of two materials, and the material of the second dielectric adhesion layer 25 may be the same as that of the first dielectric adhesion layer 20.
  • the first bonding body 1 is in contact with the pad 50 through the top edge 60 of the bump on the bonding interconnect metal, bonding the interconnect metal and soldering under the required bonding temperature and bonding pressure
  • the disk 50 is in intimate contact while the first dielectric adhesive layer 20 is bonded to the second dielectric adhesive layer 25 to be integrated.
  • the height of the first dielectric adhesion layer 20 is lower than the top edge 60 of the bump, and when bonded under pressure, the top edge 60 of the bump can The first dielectric adhesion layer 20 is blocked from entering the surface where the bonding interconnection metal is bonded to the pad 25, so that disconnection and reliability problems can be avoided.
  • the first substrate 10 and the second substrate 70 are electrically connected by bonding the interconnect metal and the pad 50.
  • the bonding method of the bonding structure includes the following steps: a. providing a first bonding body 1, and corresponding bonding interconnections on the first bonding body 1 The end of the metal forms a cavity 31 and a top edge 60 of the bump;
  • the preparation process of the first bonding body 1 includes the following steps:
  • the first substrate 10 is a conductor or a semiconductor material, and the seed layer and the first liner The bottom 10 is electrically connected;
  • A2 coating a surface of the first substrate (10) corresponding to the surface of the seed layer with a first photoresist layer (21), and forming a desired pattern after photolithography and development exposure;
  • A3 forming a bump material of a desired height and shape on the first substrate 10 to form a bonding interconnect metal
  • the shape and height of the bonding interconnect metal may be formed by electroplating, and the bonding interconnect metal may be the structure of FIG. 1 or FIG. 2; bonding the interconnect metal through the seed layer and the A substrate 10 is electrically connected; the bumps may be a combination of a high temperature bonding metal 30 or a high temperature bonding metal 30 and a low melting solder 40 to form a bonding interconnect metal.
  • A5 forming a first dielectric adhesion layer 20 on the first substrate 10, the first dielectric adhesion layer
  • the first dielectric adhesion layer 20 is formed by silicone or other means
  • A6 removing the first dielectric adhesion layer 20 covering the top edge 60 of the bonding interconnect metal end bump by ion etching, and making the height of the first dielectric adhesion layer 20 lower than the top edge of the bump a height of 60 to form a desired first bond body 1, as shown in FIG. 6;
  • the second bonding body 2 including a pad 50 and a second dielectric adhesion layer
  • the end of the bonding interconnect metal corresponding to the top edge 60 of the bump and the pad 50 on the second bonding body 2 d.
  • the end of the bond interconnect metal corresponding to the top edge 60 of the bump is in intimate contact with the pad 50, and the first dielectric adhesion layer 20 on the first bond body 1 It is bonded integrally with the second dielectric adhesive layer 25 on the second bonding body 2.
  • the bonding temperature and pressure are determined according to the material of the bonding interconnect metal and the pad 50, and the corresponding pressure has a corresponding relationship with the required temperature, which is consistent with the conventional bonding temperature and pressure, and is not detailed here. .
  • the pad 50 on the second bonding body 2 has a corresponding relationship with the height of the second dielectric adhesion layer 25, and the height of the pad 50 in the embodiment of the present invention is not higher than the height of the second dielectric adhesion layer 25.
  • the keys and steps of the first bonding body 1 and the second bonding body 2 are as shown in FIGS. 7 to 9; when the height of the pad 50 is When the height of the second dielectric adhesion layer 25 is lower than that of the second dielectric adhesion layer 25, the bonding step of the first bonding body 1 and the second bonding body 2 is as shown in FIGS. 10 to 12.
  • the height of the pad 50 is lower than the height of the second dielectric adhesion layer 25, the positioning of the bump top edge 60 in contact with the disk 50 is facilitated, and it is not easily misaligned during the bonding process.
  • the first substrate 10 of the present invention is provided with a bonding interconnection metal electrically connected to the first substrate 10, and the bonding interconnection metal is recessed to form a cavity 31 corresponding to the other end portion connected to the first substrate 10.
  • the edge of the bonding interconnect metal corresponding to the edge of the recess 31 forms a bump top edge 60;
  • the surface of the first substrate 10 corresponding to the bonding interconnect metal is covered with the first dielectric adhesion layer 20, the first The dielectric adhesion layer 20 surrounds the bonding interconnection metal and the height of the first dielectric adhesion layer 20 is lower than the height of the bonding interconnection metal;
  • the bump The top edge 60 is located at the end edge of the bond interconnect metal, and the height of the first dielectric adhesion layer 20 is lower than the top edge 60 of the bump.
  • the top edge 60 of the bump can block the first The dielectric adhesion layer 20 enters the surface where the bonding interconnection metal is bonded to

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Abstract

一种用于三维集成混合键合结构及其键合方法，其包括第一衬底（10）;第一衬底（10）上设有与第一衬底（10）电连接的键合互连金属，键合互连金属对应与第一衬底（10）相连的另一端部内陷形成凹腔（31）；第一衬底（10）上在键合互连金属的周围覆盖有第一介电粘附层（20），第一介电粘附层（20）包围键合互连金属且第一介电粘附层（20）的高度低于键合互连金属的边缘高度。第一介电粘附层（20）的高度低于凸点顶部边缘（60）的高度，当在压力作用下键合时，凸点顶部边缘（60）与第二衬底焊盘先键合，能够阻挡介电粘附层进入键合互连金属与焊盘结合的表面，从而能够避免造成断路及可靠性问题；结构紧凑，工艺操作方便。

Description

一种用于三维集成混合键合结构及其键合方法
技术领域
本发明涉及一种混合键合结构及其键合方法， 尤其是一种用于 维集成混 合键合结构及其键合方法， 属于集成电路的技术领域。
背景技术
三维集成电路的核心技术包括 TSV (硅通孔）制作、 晶圆减薄、
Figure imgf000003_0001
持以及键合技术等。 这些技术都存在极大的挑战性。 其中键合技术包括了芯片- 芯片 (chip-to-chip)、 芯片-晶圆 (chip-to-wafer)以及晶圆-晶圆 (wafer-to-wafer)键合 等三种方式。 对于上述三种键合技术， 电气互连有两种材料， 一是金属凸点， 如 Cu, Au等； 二是钎料凸点互连， 如 Sn， In等。
三维集成电路使用金属凸点互连的好处是可以获得很小的互连节距， Cu-Cu 凸点键合可以获得优良的电性能和可靠性； 其缺点是要求金属凸点具有很高的 平整度， 通常需要较高的键合温度（>300°C ), 以及特殊的表面处理以去除金属 表面的氧化物。 为降低键合温度， 研究人员做了很多努力。 具有代 性的研究 是日本东京大学开发的表面活化键合技术（SAB， Surface activated bonding)。 通 过 CMP (化学机械抛光）平整化， 利用干法刻蚀获得纯净金属表面， 并在高真 空下完成键合过程。 该方法虽然实现了了低温键合， 但是工艺复杂， 产率低， 成本高， 不适于大规模产业应用； 具体见参考文献 T. Suga, "Feasibility of surface activated bonding for ultra-fine pitch interconnection", Proc. 2000 IEEE Electronic Components and Technolgoy Conference (ECTC), 2000， pp.702-705.和 f.H. Kim, M.M.R. Howlader, et al.， "Room temperature Cu-Cu direct bonding using surface activated bonding method", J. Vac. Sci. Technol. A, 21(2), 2003, pp. 449-453。
与金属凸点相比， 钎料互连的主要优点是钎料液 /固反应可以减小对键合界 面平整度的要求， 具体见参考文献 K. Sakuma, R S. Andry, C. K. Tsang, S. L. Wright, et al" "3D Chip-Stacking Technology with Through-Silicon Vias and Low-Volume Lead-free Interconnections", IBM J. RES. & DEV. 52(6), 2008， p611-631 o 电镀凸点， 特别是铜柱钎料凸点具有较好的电性能和可靠性， 并能满 足细节距和低成本要求， 因而受到工业界青睐。 由于三维集成往往需要多层芯 片 （晶圆）堆叠， 因此需要保证后续的堆叠不影响已形成的互连结构 因此在 钎料凸点键合基础上，瞬态液相（TLP， transient liquid phase)键合应用受到重视。 所谓瞬态液相键合是指低熔点钎料键合后完全转变成金属间化合物（ψο， 可 以保证多层芯片堆叠的稳定性，具体见参考文献 R. Agarwal, W. Zhang, Limaye, R. Labie, B. Dimcic, A. Phommahaxay, and P. Soussan, "Cu/Sn Microbumps for 3D TSV Chip Stacking", Proc. 2010 IEEE Electronic Components and Technolgoy Conference (ECTC), 2010, pp. 858-8630
为解决超细节距凸点互连底部填充工艺难题， 提髙凸点互连的可靠性， 混 合键合 （hybrid bonding) 方法在 3D IC中日益受到重视。 混合键合即 在待键 合的衬底上下表面采用凸点和介电粘附层同时进行键合， 具体见参考文献 S. J. Koester, A. M. Young, R. R. Yu, S. Purrshothaman, et al.， "Wafer-level 3D Integration Technology," IBM J. RES. & DEV. 52(6), 2008， p583-597和 C. T. Ko， Z. C. Hsiao, H. C. Fu, K. N. Chen, W. C. Lo， Y. H. Chen, "Wafer-to-wafer Hybrid Bonding Technology for 3D IC"， 3rd Electronic System-Integration Technology Conference (ESTC), 2010, pp. 1 - 5。常用的介电粘附层为 BCB (干刻蚀型苯环丙 丁烯）、 SU-8 (近紫外负性光刻胶)， 以及 PI (聚酰亚胺） 等聚合物材料或者无 机物 Si02。 键合采用热压键合方式， 金属 /钎料凸点实现冶金互连， 芯片间和凸 点间的空隙则由介电粘附层通过热压固化填充， 从而提高芯片间键合的结合力。
混合键合研究也存在诸多问题， 材料与工艺需要优化， 缺乏可靠性研究。 介电粘附层， 特别是聚合物常常会挤压而流到金属键合界面， 造成断路和可靠 性问题。 需要改进键合技术来避免这个问题。 进一步地， 由于互连密度的增加， 键合所需的压力越来越大， 这对于三维集成， 特别是带有 TSV结构的薄芯片会 带来损坏。 因此， 需要低压力键合方法。
发明内容
本发明的目的是克服现有技术中存在的不足， 提供一种用于三维集成混合 键合结构及其键合方法， 其结构紧凑， 工艺操作方便， 提高键合的可靠性。
按照本发明提供的技术方案， 所述用于三维集成混合键合结构， 包括第一 衬底； 所述第一衬底上设有与第一衬底电连接的键合互连金属， 所述键合互连 金属对应与第一衬底相连的另一端部内陷形成凹腔， 键合互连金属对应设置凹 腔的端部边缘形成凸点顶部边缘； 第一衬底对应形成键合互连金属的表面覆盖 有第一介电粘附层， 所述第一介电粘附层包围键合互连金属且第一介电粘附层 的高度低于键合互连金属的高度。
所述键合互连金属为高温键合金属。 所述高温键合金属的材料为 Cu、 Ni、 Al、 Pt、 Pd或 Au中的一种或几种。
所述键合互连金属包括高温键合金属及位于所述高温键合金属一端的低熔 点钎料， 键合互连金属中的高温键合金属与第一衬底对应相连， 并在低熔点钎 料的端部内陷形成凹腔； 第一介电粘附层的高度低于低熔点钎料形成凹腔端部 的高度。
所述低熔点钎料为锡基合金或铟基合金。 所述第一介电粘附层的材料包括 BCB、 SU-8、 PI聚合物或 Si02。
所述第一衬底通过键合互连金属与第二键合体对应配合， 第二键合体包括 第二衬底， 所述第二衬底的表面上设有与第二衬底电连接的焊盘， 第二衬底对 应形成焊盘的表面覆盖第二介电粘附层； 键合互连金属通过凸点顶部边缘与焊 盘对应接触， 并在所需的温度及压力下紧密结合， 且第一介电粘附层与第二介 电粘附层粘结后连成一体。
所述焊盘的材料为高温金属或低熔点钎料。 所述第二介电粘附层的材料包 括 BCB、 SU-8、 PI聚合物或 Si02。
所述第二衬底的材料包括硅。 一种用于三维集成混合键合结构的键合方法， 所述键合方法包括如下步骤: a、 提供第一键合体， 所述第一键合体上相应键合互连金属的端部形成凹腔 及凸点顶部边缘；
b、 提供第二键合体， 所述第二键合体上包括焊盘及第二介电粘附层； c、 将键合互连金属对应形成凸点顶部边缘的端部与第二键合体上的焊盘定 位接触；
d、 在所需的键合温度及压力下， 键合互连金属对应形成凸点顶部边缘的端 部与焊盘紧密接触， 第一键合体上的第一介电粘附层与第二键合体上的第二介 电粘附层粘结成一体。
所述步骤 a中， 包括如下步骤：
al、 提供第一衬底， 并在所述第一衬底的表面制作与第一衬底电连接的种 子层；
a2、 在第一衬底对应形成种子层的表面涂覆第一光刻胶层， 并光刻、 显影 曝光后形成所需图形；
a3、 在上述第一衬底上电镀形成所需髙度与形状的凸点材料， 以形成键合 互连金属；
a4、 ^除上述第一光刻胶层， 并刻蚀第一衬底上对应裸露的种子层； a5、 在上述第一衬底上形成第一介电粘附层， 所述第一介电粘附层覆盖在 第一衬底的表面并覆盖键合互连金属端部的凸点顶部边缘；
a6、 通过离子刻蚀去除覆盖于键合互连金属端部凸点顶部边缘上的第一介 电粘附层， 并使得第一介电粘附层的髙度低于凸点顶部边缘的高度， 以形成所 需的第一键合体。
所述第二介电粘附层通过甩胶覆盖在第一衬底及键合互连金属上。 所述步 骤33中， 电镀形成所需高度的形状与凸点材料包括高温金属或低熔点钎料。
本发明的优点： 第一衬底上设有与第一衬底电连接的键合互连金属， 所述 键合互连金属对应与第一衬底相连的另一端部内陷形成凹腔， 键合互连金属对 应设置凹腔的端部边缘形成凸点顶部边缘； 第一衬底对应形成键合互连金属的 表面覆盖有第一介电粘附层， 所述第一介电粘附层包围键合互连金属且第一介 电粘附层的高度低于凸点顶部边缘的高度； 当通过键合互连金属与焊盘键合时， 第一介电粘附层的高度低于凸点顶部边缘， 当在压力作用下键合时， 凸点顶部 边缘与焊盘接触键合能够阻挡介电粘附层进入键合互连金属与焊盘结合的表 面， 从而能够避免造成断路及可靠性问题； 结构紧凑， 工艺操作方便。
附图说明
图 1为本发明的结构示意图。
图 2为本发明键合互连金属的另一种结构示意图。
图 3为〜图 6为本发明键合互连金属形成的具体步骤剖视图， 其中： 图 3为电镀形成键合互连金属后的剖视图。
图 4为去除光刻胶层并刻蚀种子层后的剖视图。
图 5为形成第一介质粘附层后的剖视图。 图 6为形成第一键合体后的剖视图。
图 7〜图 9为本发明与第二键合体键合的具体步骤剖视图， 其中：
图 7为提供第一键合体与第二键合体后的剖视图。
图 8为通过凸点与焊盘相接触的剖视图。
图 9为第一键合体与第二键合体键合后的剖视图。
图 10〜图 12为本发明与第二键合体键合的具体步骤剖视图， 其中： 图 10为提供第一键合体与第二键合体后的剖视图。
图 11为通过凸点与悍盘相接触的剖视图。
图 12为第一键合体与第二键合体键合后的剖视图。
附图标记说明： 1-第一键合体、 2-第二键合体、 10-第一衬底、 20-第一介电 粘附层、 21-第一光刻胶层、 22-键合互连孔、 25-第二介电粘附层、 30-高温键合 金属、 31-凹腔、 40-低熔点材料键合体、 50-焊盘、 60-凸点顶部边缘及 70-第二衬 底。
具^实施方式
下面结合具体附图和实施例对本发明作进一步说明。
如图 1和图 2所示： 为了避免现有键合过程中造成断路与可靠性问题， 本 发明包括第一键合体 1， 第一键合体 1包括第一衬底 10; 所述第一衬底 10上设 有与第一衬底 10电连接的键合互连金属，所述键合互连金属对应与第一衬底 10 相连的另一端部内陷形成凹腔 31，即在键合互连金属对应形成凹腔 31的端部形 成凸点顶部边缘 60，第一衬底 10对应形成键合互连金属的表面覆盖有第一介电 粘附层 20， 所述第一介电粘附层 20包围键合互连金属且第一介电粘附层 20的 高度低于键合互连金属端部的高度； 即第一介电粘附层 20的高度低于凸点顶部 边缘 60。 图 1和图 2分别示出了键合互连金属的不同结构， 其中， 图 1中键合 互连金属全部采用高温键合金属 30， 图 2中键合互连金属包括高温键合金属 30 及位于所述高温键合金属 30端部的低熔点材料键合体 40，在低熔点材料键合体 40端部通过内陷形成凹腔 31。第一介电粘附层 20的高度低熔点钎料 40形成凹 腔 31端部的高度。
所述高温键合金属 30的材料为 Cu、 Ni、 Al、 Pt、 Pd、 或 Au中的一种或几 种。 所述低熔点钎料 40为锡基合金或铟基合金。 所述第一介电粘附层 20的材 料包括 BCB、 SU-8、、 PI聚合物或 Si02。
如图 9和图 12所示： 为本发明第一键合体 1与第二键合体 2键合后的结构 示意图。 第二键合体 2包括第二衬底 70， 第二衬底 70的表面设有焊盘 50， 焊 盘 50与第二衬底 70电连接， 第二衬底 70的材料包括硅。 第二衬底 70对应形 成焊盘 50的表面覆盖有第二介电粘附层 25，悍盘 50与第二介电粘附层 25之间 的高度关系应与凸点顶部边缘 60与第一介电粘附层 20之间的高度关系相对应， 以避免通过凸点顶部边缘 60与悍盘 50之间键合连接时， 第一介电粘附层 20或 第二介电粘附层 25间压入第一介电粘附层 20或第二介电粘附层 25， 以不会造 成断路及可靠性问题为准。 本发明的实施例中， 焊盘 50的高度不高于第二介电 粘附层 25的高度， 图 9为焊盘 50的高度与第二介电粘附层 25高度相同键合后 的结构图，图 12为焊盘 50的高度低于第二介电粘附层 25高度键合后的结构图。 焊盘 50可以为高温键合金属， 也可以为低熔点钎料或两种材料的组合， 第 二介电粘附层 25的材料可以与第一介电粘附层 20的材料相同。 键合时， 第一 键合体 1通过键合互连金属上的凸点顶部边缘 60与焊盘 50相接触， 在所需的 键合温度与键合压力作用下， 键合互连金属与焊盘 50能紧密接触， 同时第一介 电粘附层 20与第二介电粘附层 25粘结后连成一体。 由于凸点顶部边缘 60位于 键合互连金属的端部边缘，第一介电粘附层 20的高度低于凸点顶部边缘 60， 当 在压力作用下键合时， 凸点顶部边缘 60能够阻挡第一介电粘附层 20进入键合 互连金属与焊盘 25结合的表面， 从而能够避免造成断路及可靠性问题。 键合连 接后， 第一衬底 10与第二衬底 70通过键合互连金属及焊盘 50电连接。
如图 7〜图 9及图 10〜图 12所示:上述键合结构的键合方方法包括如下步骤: a、 提供第一键合体 1， 所述第一键合体 1上相应键合互连金属的端部形成 凹腔 31及凸点顶部边缘 60;
如图 3〜图 6所示： 为本发明第一键合体 1的形成过程， 第一键合体 1的制 备过程包括如下步骤：
al、 提供第一衬底 10， 并在所述第一衬底 10的表面制作与第一衬底 10电 连接的种子层； 第一衬底 10为导体或半导体材料， 种子层与第一衬底 10电连 接；
a2、 在第一衬底（10)对应形成种子层的表面涂覆第一光刻胶层 （21 )， 并 光刻、 显影曝光后形成所需图形；
a3、 在上述第一衬底 10上电镀形成所需高度与形状的凸点材料， 以形成键 合互连金属；
如图 3 '所示： 所述键合互连金属的形状与高度可以通过电镀形成， 键合互 连金属的可以为图 1或图 2中的结构； 键合互连金属通过种子层与第一衬底 10 电连接； 凸点可以为高温键合金属 30或高温键合金属 30与低熔点钎料 40的组 合， 以形成键合互连金属 ·
a4、 去除上述第一光 ¾胶层 21， 并刻蚀第一衬底 10上对应裸露的种子层； 通过将裸露的种子层刻蚀， 能够避免第一衬底 10上键合互连金属间的绝缘 隔离， 如图 4所示；
a5、 在上述第一衬底 10上形成第一介电粘附层 20, 所述第一介电粘附层
20覆盖在第一衬底 10的表面并覆盖键合互连金属端部的凸点顶部边缘 60; 如图 5所示： 第一介电粘附层 20通过甩胶或其他方式形成；
a6、 通过离子刻蚀去除覆盖于键合互连金属端部凸点顶部边缘 60上的第一 介电粘附层 20，并使得第一介电粘附层 20的高度低于凸点顶部边缘 60的高度， 以形成所需的第一键合体 1， 如图 6所示；
b、提供第二键合体 2，所述第二键合体 2上包括焊盘 50及第二介电粘附层
25；
c、 将键合互连金属对应形成凸点顶部边缘 60的端部与第二键合体 2上的 焊盘 50定位接触； d、 在所需的键合温度及压力下， 键合互连金属对应形成凸点顶部边缘 60 的端部与焊盘 50紧密接触， 第一键合体 1上的第一介电粘附层 20与第二键合 体 2上的第二介电粘附层 25粘结成一体。所述键合温度及压力根据键合互连金 属及焊盘 50的材料来决定， 相应的压力与所需的温度具有对应关系， 与常规的 键合温度及压力相一致， 此处不在详述。
第二键合体 2上焊盘 50与第二介电粘附层 25的高度具有相应的关系， 本 发明的实施例中焊盘 50的高度不高于第二介电粘附层 25的高度。 当焊盘 50的 高度与第二介电粘附层 25的高度一致时， 第一键合体 1与第二键合体 2的键和 步骤参考图 7~图 9所示； 当焊盘 50的高度低于第二介电粘附层 25的高度时， 第一键合体 1与第二键合体 2的键合步骤参考图 10~图 12所示。当焊盘 50的高 度低于第二介电粘附层 25的高度时， 有利于凸点顶部边缘 60与悍盘 50接触时 的定位， 同时在键合过程中不容易错位。
本发明第一衬底 10上设有与第一衬底 10电连接的键合互连金属， 所述键 合互连金属对应与第一衬底 10相连的另一端部内陷形成凹腔 31 ,键合互连金属 对应设置凹腔 31的端部边缘形成凸点顶部边缘 60; 第一衬底 10对应形成键合 互连金属的表面覆盖有第一介电粘附层 20,所述第一介电粘附层 20包围键合互 连金属且第一介电粘附层 20的高度低于键合互连金属的高度； 当通过键合互连 金属与悍盘 50键合时， 凸点顶部边缘 60位于键合互连金属的端部边缘， 第一 介电粘附层 20的高度低于凸点顶部边缘 60， 当在压力作用下键合时， 凸点顶部 边缘 60能够阻挡第一介电粘附层 20进入键合互连金属与焊盘 25结合的表面， 从而能够避免造成断路及可靠性问题； 结构紧凑， 工艺操作方便。

Claims
I、 一种用于三维集成混合键合结构， 包括第一衬底 （10); 其特征是： 所 述第一衬底 （10) 上设有与第一衬底 （10) 电连接的键合互连金属， 所述键合 互连金属对应与第一衬底（10)相连的另一端部内陷形成凹腔（31 ), 键合互连 金属对应设置凹腔（31 ) 的端部边缘形成凸点顶部边缘（60); 第一衬底 （10) 对应形成键合互连金属的表面覆盖有第一介电粘附层（20)， 所述第一介电粘附 层 （20)包围键合互连金属且第一介电粘附层 （20) 的高度低于键合互连金属 的高度。
根据权利要求 1所述的用于三维集成混合键合结构， 其特征是： 所述键 合互连金属为高温键合金属 （30)。
3、 根据权利要求 2所述的用于三维集成混合键合结构， 其特征是： 所述高 温键合金属 （30) 的材料为 Cu、 Ni、 Al、 Pt、 Pd或 Au中的一种或几种。
4、 根据权利要求 1所述的用于三维集成混合键合结构， 其特征是： 所述键 合互连金属包括高温键合金属 （30)及位于所述高温键合金属 （30) —端的低 熔点钎料（40)， 键合互连金属中的高温键合金属 （30)与第一衬底（10)对应 相连， 并在低熔点钎料（40)的端部内陷形成凹腔（31 ); 第一介电粘附层（20) 的高度低于低熔点钎料 （40)形成凹腔 （31 )端部的高度。
5、 根据权利要求 4所述的用于三维集成混合键合结构， 其特征是： 所述低 熔点钎料（40) 为锡基合金或铟基合金。
6、 根据权利要求 1所述的用于三维集成混合键合结构， 其特征是： 所述第 一介电粘附层 （20) 的材料包括 BCB、 SU-8、 PI聚合物或 Si02。
7、 根据权利要求 1所述的用于三维集成混合键合结构， 其特征是： 所述第 一衬底 （10)通过键合互连金属与第二键合体（2)对应配合， 第二键合体（2) 包括第二衬底（70)， 所述第二衬底（70) 的表面上设有与第二衬底（70) 电连 接的焊盘（50)， 第二衬底（70)对应形成焊盘（50) 的表面覆盖第二介电粘附 层 （25); 键合互连金属通过凸点顶部边缘（60)与焊盘 （50)对应接触， 并在 所需的温度及压力下紧密结合，且第一介电粘附层（20)与第二介电粘附层（25) 粘结后连成一体。
8、 根据权利要求 7所述的用于三维集成混合键合结构， 其特征是： 所述焊 盘 （50) 的材料为高温金属或低熔点钎料。
9、 根据权利要求 7所述的用于三维集成混合键合结构， 其特征是： 所述第 二介电粘附层 （25) 的材料包括 BCB、 SU-8、 PI聚合物或 Si02。
10、 根据权利要求 7所述的用于三维集成混合键合结构， 其特征是： 所述 第二衬底 （70) 的材料包括硅。
I I、 一种用于三维集成混合键合结构的键合方法， 其特征是， 所述键合方 法包括如下步骤：
(a)、 提供第一键合体（1 )， 所述第一键合体（1 )上相应键合互连金属的 端部形成凹腔（31 )及凸点顶部边缘（60);
(b)、 提供第二键合体（2)， 所述第二键合体（2)上包括焊盘（50)及第 二介电粘附层 （25 );
(c)、 将键合互连金属对应形成凸点顶部边缘（60) 的端部与第二键合体 (2)上的焊盘 （50) 定位接触；
(d)、 在所需的键合温度及压力下， 键合互连金属对应形成凸点顶部边缘 (60)的端部与焊盘（50)紧密接触，第一键合体（1 )上的第一介电粘附层（20) 与第二键合体（2) 上的第二介电粘附层 （25 )粘结成一体。
12、 根据权利要求 11所述的用于三维集成混合键合结构的键合方法， 其特 征是， 所述步骤（a) 中， 包括如下步骤：
( al )、 提供第一衬底 （10)， 并在所述第一衬底 （10) 的表面制作与第一 衬底 （10) 电连接的种子层；
(a2)、 在第一衬底（10)对应形成种子层的表面涂覆第一光刻胶层 （21 )， 并光刻、 显影曝光后形成所需图形；
(a3 )、 在上述第一衬底 （10)上电镀形成所需高度与形状的凸点材料， 以 形成键合互连金属；
( a4)、 去除上述第一光刻胶层 （21 )， 并刻蚀第一衬底 （10) 上对应裸露 的种子层；
(a5)、 在上述第一衬底 （10)上形成第一介电粘附层 （20)， 所述第一介 电粘附层 （20) 覆盖在第一衬底 （10) 的表面并覆盖键合互连金属端部的凸点 顶部边缘（60);
(a6)、 通过离子刻蚀去除覆盖于键合互连金属端部凸点顶部边缘（60)上 的第一介电粘附层 （20)， 并使得第一介电粘附层 （20) 的高度低于凸点顶部边 缘（60) 的高度， 以形成所需的第一键合体（1 )。
13、 根据权利要求 12所述的用于三维集成混合键合结构的键合方法， 其特 征是： 所述第一介电粘附层 （20)通过甩胶覆盖在第一衬底 （10)及键合互连 金属上。
14、 根据权利要求 12所述的用于三维集成混合键合结构的键合方法， 其特 征是： 所述步骤 （a3 ) 中， 电镀形成所需高度的形状与凸点材料包括高温金属 或低熔点钎料。
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