TWI585930B - 封裝體結構及其製備方法 - Google Patents

封裝體結構及其製備方法 Download PDF

Info

Publication number
TWI585930B
TWI585930B TW104130803A TW104130803A TWI585930B TW I585930 B TWI585930 B TW I585930B TW 104130803 A TW104130803 A TW 104130803A TW 104130803 A TW104130803 A TW 104130803A TW I585930 B TWI585930 B TW I585930B
Authority
TW
Taiwan
Prior art keywords
layer
metal
connector
package structure
redistribution
Prior art date
Application number
TW104130803A
Other languages
English (en)
Other versions
TW201644032A (zh
Inventor
施信益
姜序
施能泰
Original Assignee
美光科技公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 美光科技公司 filed Critical 美光科技公司
Publication of TW201644032A publication Critical patent/TW201644032A/zh
Application granted granted Critical
Publication of TWI585930B publication Critical patent/TWI585930B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
    • H01L21/4814—Conductive parts
    • H01L21/4846—Leads on or in insulating or insulated substrates, e.g. metallisation
    • H01L21/4857—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5383—Multilayer substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L24/80 - H01L24/90
    • H01L24/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/93—Batch processes
    • H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
    • H01L2221/68331—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding of passive members, e.g. die mounting substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68345—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during the manufacture of self supporting substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68359—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used as a support during manufacture of interconnect decals or build up layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
    • H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
    • H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
    • H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
    • H01L2221/68381—Details of chemical or physical process used for separating the auxiliary support from a device or wafer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/11312—Continuous flow, e.g. using a microsyringe, a pump, a nozzle or extrusion
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1131—Manufacturing methods by local deposition of the material of the bump connector in liquid form
    • H01L2224/1132—Screen printing, i.e. using a stencil
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11462—Electroplating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
    • H01L2224/1146—Plating
    • H01L2224/11464—Electroless plating
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13111—Tin [Sn] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13139—Silver [Ag] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13144—Gold [Au] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
    • H01L2224/13147—Copper [Cu] as principal constituent
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16227—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/1701—Structure
    • H01L2224/1703—Bump connectors having different sizes, e.g. different diameters, heights or widths
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H01L2224/171—Disposition
    • H01L2224/1718—Disposition being disposed on at least two different sides of the body, e.g. dual array
    • H01L2224/17181—On opposite sides of the body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/81001—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus
    • H01L2224/81005—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector involving a temporary auxiliary member not forming part of the bonding apparatus being a temporary or sacrificial substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/8119—Arrangement of the bump connectors prior to mounting
    • H01L2224/81192—Arrangement of the bump connectors prior to mounting wherein the bump connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91—Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92—Specific sequence of method steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/93—Batch processes
    • H01L2224/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49811—Additional leads joined to the metallisation on the insulating substrate, e.g. pins, bumps, wires, flat leads
    • H01L23/49816—Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5385—Assembly of a plurality of insulating substrates
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/11—Manufacturing methods
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/10—Bump connectors ; Manufacturing methods related thereto
    • H01L24/15—Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L24/17—Structure, shape, material or disposition of the bump connectors after the connecting process of a plurality of bump connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
    • H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/18—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50—Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA

Description

封裝體結構及其製備方法
本發明是有關於一種封裝體結構及其製備方法，特別是有關於一種無穿孔之封裝體結構及其製備方法。
隨著半導體裝置之製造技術的演進，半導體裝置之功能密度隨著裝置尺寸的減少而上升，以達到更高的半導體裝置集成密度。結果，半導體裝置之尺寸減少以及密度增加，使得對封裝技術的要求更為嚴峻。近來，隨著對較小電子裝置之需求的增加，創新的封裝技術是必要的。
目前，於中介層(interposer)之中介基板層發展出穿孔(through via)，其具有額外的金屬層在中介基板層上，以提高半導體裝置之密度。然而，形成具有穿孔之中介基板層的製程極為複雜。
因此，目前需要發展一種改良的封裝體結構及其製備方法。
本揭露之一態樣係提供一種封裝體結構。封裝 體結構包含基板、第一連接件、重佈局層、第二連接件以及晶片。第一連接件設置於基板上。重佈局層直接設置於第一連接件上，並藉由第一連接件連接至基板。重佈局層包含阻擋層以及位於阻擋層上之金屬層。第二連接件直接設置於重佈局層上，且晶片藉由第二連接件連接至重佈局層。
在本揭露之多個實施方式中，金屬層包含介電層以及複數個金屬組件。金屬段係設置於介電層內。
在本揭露之多個實施方式中，第一連接件夾設於阻擋層中，並與金屬層連接。
在本揭露之多個實施方式中，阻擋層之材料為碳化矽、氮化矽或其組合。
在本揭露之多個實施方式中，封裝體結構包含複數個重佈局層。
在本揭露之多個實施方式中，這些金屬層係水平排列，且不同金屬層係藉由複數個導電柱連接，且導電柱係貫穿金屬層間之阻擋層。
在本揭露之多個實施方式中，第一連接件夾設於最底層之阻擋層中，並連接最底層之金屬層與基板。
在本揭露之多個實施方式中，第一連接件與第二連接件係獨立為焊料凸塊或焊球。
在本揭露之多個實施方式中，封裝體結構更包含鈍化層，位於基板與重佈局層之間，且第一連接件夾設於鈍化層中。
在本揭露之多個實施方式中，鈍化層之材料為氧化矽(silicon oxide)、氮化矽(silicon nitride)、苯並環丁烯(benzocyclobutene，BCB)、聚醯亞胺(polyimide，PI)、聚苯噁唑(polybenzoxazole，PBO)或其組合。
本揭露之另一態樣係提供一種製備封裝體結構的方法，包含以下步驟。形成重佈局層，包含形成金屬層，以及形成阻擋層於金屬層上。直接形成第一連接件於重佈局層之第一側上。直接形成第二連接件於重佈局層之相對於第一側之第二側上。藉由第二連接件連接重佈局層之第二側與晶片。藉由第一連接件連接重佈局層之第一側與基板。
在本揭露之多個實施方式中，形成重佈局層係形成於第一載體上。
在本揭露之多個實施方式中，方法更包含藉由第一連接件連接重佈局層之第一側與第二載體。然後，於形成第二連接件前，移除第一載體。
在本揭露之多個實施方式中，方法更包含於接合重佈局層之第二側與晶片後，移除第二載體。
在本揭露之多個實施方式中，方法更包含於移除第二載體前，形成暫時性黏合劑於晶片上。然後，於接合重佈局層之第一側與基板後，移除暫時性黏合劑。
在本揭露之多個實施方式中，形成金屬層係藉由鑲嵌製程進行。
在本揭露之多個實施方式中，形成金屬層包含沉積介電層。之後，蝕刻介電層以形成複數個開口。然後，以金屬材料填充開口，以形成複數個金屬段。
在本揭露之多個實施方式中，形成第一連接件夾設於阻擋層中，並與金屬層連接。
在本揭露之多個實施方式中，方法包含形成複數個重佈局層。
在本揭露之多個實施方式中，方法更包含形成鈍化層於重佈局層上，且第一連接件夾設於鈍化層中。
參照以下之說明以及所附之申請專利範圍，可更加理解本揭露之特徵、態樣以及優點。
應當理解的是，以上之一般敘述以及以下之詳細敘述係實例，並旨在對所要求保護發明提供進一步的解釋。
100‧‧‧封裝體結構
112‧‧‧第一鈍化層
114‧‧‧第二鈍化層
120‧‧‧金屬層
122‧‧‧介電層
124‧‧‧開口
126‧‧‧金屬組件
128‧‧‧導電柱
130‧‧‧阻擋層
140‧‧‧重佈局層
152‧‧‧第一連接件
154‧‧‧第二連接件
156‧‧‧第三連接件
160‧‧‧晶片
170‧‧‧基板
202‧‧‧第一載體
204‧‧‧第二載體
210‧‧‧黏合層
220‧‧‧暫時性黏合劑
為使本發明之特徵、優點與實施例能更明顯易懂，所附圖式之說明如下：第1A~1L圖係繪示根據本揭露一實施方式之製備封裝體結構於各個階段的剖視圖。
之後將以示例圖式以詳細描述本發明的各種實施方式，且在圖式和說明書中使用相同的元件符號以指代相 同或相似的部分。
以下將以圖式揭露本發明之複數個實施方式，為明確說明起見，許多實務上的細節將在以下敘述中一併說明。然而，應瞭解到，這些實務上的細節不應用以限制本發明。也就是說，在本發明部分實施方式中，這些實務上的細節是非必要的。此外，為簡化圖式起見，一些習知慣用的結構與元件在圖式中將以簡單示意的方式繪示之。
如前述之問題，製備具有矽穿孔(through-silicon-via，TSV)之中介基板層(interposer substrate layer)的中介層(interposer)以及額外的金屬層在中介基板層上的製程極為複雜。原因在於，形成具有矽穿孔之中介基板層具有數個製備步驟，其包含於中介基板層形成矽穿孔，以及執行晶背薄化(backside thinning)和化學氣相沉積(chemical vapor deposition，CVD)或化學機械平坦化(chemical mechanical planarization，CMP)。這些製備步驟增加了晶圓處理的困難度。因此，製備具有矽穿孔之中介基板層的過程係複雜且高成本的。
本揭露提供一種封裝體結構及其製備方法。本發明之製備方法消除矽穿孔模組(TSV module)，並略過矽基板之研磨製程。因此，本揭露所提供之方法具有較簡單的製備流程以及較低的製備成本。
請參照第1A~1L圖，其係繪示根據本發明一實施方式之製備封裝體結構100於各個階段的剖視圖。
如第1A圖所示，第一鈍化層112係形成於第一 載體202上。第一載體202可由矽(silicon)或玻璃製成。當第一載體202係由玻璃製成時，第一鈍化層112可藉由直接沉積於第一載體202上而形成，或者可在形成離型層(release layer)之後形成。在一些實施方式中，第一鈍化層112係由氧化矽(SiO2)、氮化矽(SiN)、苯並環丁烯(benzocyclobutene，BCB)、聚醯亞胺(polyimide，PI)、聚苯並噁唑(polybenzoxazole，PBO)或其組合所製成。
接著，形成重佈局層(redistribution layer)。重佈局層包含金屬層以及阻擋層，且金屬層包含介電層以及設置於介電層內之多個金屬組件。金屬層可藉由鑲嵌(damascene)製程而形成，例如單鑲嵌製程以及雙鑲嵌製程。由鑲嵌製程所形成之金屬層中的介電層與金屬組件係共平面。在一些實施方式中，金屬層120係藉由以下第1B至1D圖所示之製程而形成。
第1B圖顯示出於第一鈍化層112上沉積介電層122。在一些實施方式中，介電層122係由氧化矽(SiO2)、氮化矽(Si3N4)或其組合所製成。介電層122可藉由任何合適之沉積製程而形成。沉積之實例包含但不限於化學氣相沉積(chemical vapor deposition，CVD)、物理氣相沉積(physical vapor deposition，PVD)、原子層沉積(atomic layer deposition，ALD)以及其組合。
接著如第1C圖所示，蝕刻介電層122以形成多個開口124。在一些實施方式中，開口為線、通孔、洞或溝槽。蝕刻可為乾式蝕刻或濕式蝕刻。
接著如第1D圖所示，以金屬材料填充開口124以形成多個金屬組件126。在一些實施方式中，金屬組件126係藉由沉積而形成。在一些實施方式中，金屬組件126係由銅(copper，Cu)、鋁(aluminum，Al)或其組合所製成。在填充金屬材料前，可於開口124之側壁上形成隔離層。在以金屬材料填充開口124後，可進行化學機械平坦化(chemical-mechanical planarization，CMP)製程，以整平金屬組件126與介電層122。從而形成金屬層120。
請參照第1E圖，形成阻擋層130於金屬層120上。從而形成重佈局層140。阻擋層130可藉由沉積而形成，例如化學氣相沉積(CVD)、物理氣相沉積(PVD)、原子層沉積(ALD)或其它合適的製程。在一些實施方式中，阻擋層130係由碳化矽(silicon carbide，SiC)、氮化矽(SiN)或其組合所製成。
第1B至1E圖係顯示本發明多個實施方式之形成一層重佈局層140的製程。依據產品之需求，封裝體結構100可包含多個重佈局層140。第1F圖係顯示具有四層重佈局層140所形成之結構。值得注意的是，金屬層120間之阻擋層130並非連續的，且由多個導電柱128貫穿。導電柱128連接不同金屬層120中的金屬組件126。在一些實施方式中，金屬層120係藉由單鑲嵌製程或雙鑲嵌製程而形成，且部分之阻擋層130在此製程中會被移除。導電柱128可與金屬組件126一起形成。舉例而言，形成包含第一介電層以及多個第一金屬組件之第一金屬層。接著，於第一金屬層上形 成第一阻擋層。然後，藉由嵌製程形成第二金屬層，其係先於第一阻擋層上形成第二介電層。繼續進行製程以移除部份的第二介電層以及第一阻擋層，以形成開口。接著，以金屬材料填充開口以形成第二金屬組件以及貫穿第一阻擋層之導電柱。然後，於第二金屬層上形成第二阻擋層。前述之步驟可重複進行，直至達到重佈局層所需之層數。
接著如第1G圖所示，於形成多個重佈局層140後，形成第二鈍化層114於最頂層的重佈局層140上。另，移除部分之第二鈍化層114以及最頂層的阻擋層130，以暴露出部分之最頂層的金屬層120。接著，直接形成複數個第一連接件152於最頂層金屬層120之暴露部分上。也就是說，第一連接件152夾設於第二鈍化層114以及最頂層的阻擋層130中。第二鈍化層114之材料的實例可參照第一鈍化層112之對應部份，並不在此贅述。在一些實施方式中，第一連接件152係焊料凸塊(solder bump)或焊球(solder ball)。第一連接件152之材料可為銀、銅或錫基(tin-based)組合物。第一連接件152可使用電或非電鍍技術形成，或者使用網版印刷(screening printing)或噴墨印刷(jet printing)技術形成。第一連接件152亦可為其它種類之連接件，例如銅柱或金柱、導電螺柱(conductive stud)以及C4凸塊。
值得注意的是，此處所指之“最頂層”的金屬層120或阻擋層130表示金屬層120或阻擋層130與第一載體202之相對位置。也就是說，當第一載體202位於底部時， “最頂層”的金屬層120或阻擋層130係位於頂部，且為距離第一載體202最遠之金屬層120或阻擋層130。
在一些實施方式中，形成第一連接件包含形成凸塊底層金屬化(under-bump metallization，UBM)層於最頂層金屬層之暴露部分上，以及形成第一連接體於凸塊底層金屬化層上。凸塊底層金屬化層可為U型，且可覆蓋部份之第二鈍化層114。凸塊底層金屬化層之材料的實例包含但不限於氮化鈦(TiN)、鈦(Ti)、錫(Sn)、銀(Ag)、銅(Cu)、金(Ag)、鎳(Ni)、上述之合金以及上述之組合。
請參照第1H圖，第1G圖所示之結構藉由第一連接件152以及黏合層210接合至第二載體204上。黏合層210係在接合至第二載體204上之前，形成於第二鈍化層114上。
請繼續參照第1H圖，自第一鈍化層112移除第一載體202。從而暴露出第一鈍化層112。如上所述，第一載體202可由矽或玻璃製成。當第一載體202係由矽製成時，第一載體202可藉由研磨或濕式蝕刻移除。當第一載體202係由玻璃製成時，第一載體202可藉由雷射剝離(laser debonding)移除。
在與第二載體204接合以及剝離第一載體202之後，第1H圖係顯示以第二載體204為最底層元件之結構。以下第1H至1L圖相對於第1A至1G圖係倒置的。
接著如第1I圖所示，移除部分之第一鈍化層112以直接形成多個第二連接件154於最頂層的金屬層120 上。第二連接件154係與最頂層金屬層120之金屬組件126連接。第二連接件154之材料的實例可參照第一連接件152之對應部份，並不在此贅述。
值得注意的是，此處所指之“最頂層”的金屬層120表示金屬層120與第二載體204之相對位置。也就是說，當第二載體204位於底部時，“最頂層”的金屬層120係位於頂部，且為距離第二載體204最遠之金屬層120。另，第1I圖相對於第1G圖係倒置的。因此，此處所指之“最頂層的金屬層120”係與前述依據第1G圖之“最頂層的金屬層120”不同。
請參照第1J圖，安裝多個晶片160於第二連接件154上。晶片160係藉由第二連接件154連接至重佈局層140。具體而言，晶片160係藉由第二連接件154連接至最頂層的金屬層120。同樣地，此處所指之“最頂層的金屬層120”係表示金屬層120與第二載體204之相對位置。晶片160可為相同或不同種類的晶片。
接著如第1K圖所示，形成暫時性黏合劑220於晶片160上。暫時性黏合劑220係用以固定晶片160，並在後續製程中移除第二載體204時，維持整體結構。暫時性黏合劑220可為切割膠帶(dicing tape)。接著，移除第二載體204以及黏合層210。第二載體204可藉由任何合適之方式移除，例如暫時性接合/剝離(temporary bonding/debonding，TB/DB)技術。舉例而言，第二載體204係藉由機械性剝離(mechanical debonding)或雷射剝 離移除。
請參照第1L圖，對第1K圖所示之結構沿著虛線進行切割製程，以分離晶片160。接著，將切割後之結構安裝於基板170上，以形成第1L圖所示之封裝體結構100。基板170係藉由第一連接件152連接至重佈局層140。具體而言，基板170係藉由第一連接件152連接至最底層的金屬層120。從而形成封裝體結構100。基板170可為板(board)，例如印刷電路板(printed circuit board，PCB)。
值得注意的是，此處所指之“最底層”的金屬層120表示金屬層120與基板170之相對位置。也就是說，當基板170位於底部時，“最底層”的金屬層120為距離基板170最近之金屬層120。另，第1L圖相對於第1G圖係倒置的。因此，此處所指之“最底層的金屬層120”係與前述依據第1G圖之“最頂層的金屬層120”相同。
在一些實施方式中，封裝結構100更包含第三連接件156於基板170下。第三連接件156之材料的實例可參照第一連接件152之對應部份，並不在此贅述。
本揭露之製備封裝體結構的方法係無矽穿孔(TSV-less)且無矽基板(silicon-substrate-less)，也就是說本揭露之方法消除了形成具有矽穿孔之中介基板層(interposer substrate layer)的過程。封裝體結構中的重佈局層係直接與基板以及晶片連接。形成之封裝體結構包含鄰近於金屬層之阻擋層。因此，藉由消除矽穿孔模組以及略過矽研磨製程，本揭露之製備封裝體結構的方法包含較簡單 的製備流程，因而具有較低的成本。
由第1A至1L圖所繪示之製程所製備之封裝結構100包含基板170、多個第一連接件152、多個第二連接件154、多個第三連接件156、多個重佈局層140、第一鈍化層112、第二鈍化層114以及多個晶片160。基板170係設置於第三連接件156上。第一連接件152係設置於基板170上。第二鈍化層114係設置於最底層的重佈局層140下，且第一連接件152係夾設於第二鈍化層114中。重佈局層140係直接設置於第一連接件152上，且最底層的重佈局層140藉由第一連接件152與基板170連接。每一重佈局層140包含阻擋層130以及於阻擋層130上之金屬層120。每一金屬層120包含介電層122以及設置於介電層122內之金屬組件126。金屬層120係水平排列，且不同的金屬層120係藉由多個導電柱128連接，其貫穿不同的金屬層120間之阻擋層130。第一鈍化層112係設置於最頂層的重佈局層140上，且具有間隔，以使第二連接件154連接重佈局層140與晶片160。第二連接件154係直接設置於最頂層的重佈局層140上，且晶片160係藉由第二連接件154連接至重佈局層140。
具體而言，第一連接件152係夾設於最底層的阻擋層130中，並連接最頂層的金屬層120與基板170。
如前所述，此處所指之“最頂層”以及“最底層”係表示與基板170之相對位置。也就是說，當基板170位於底部時，“最頂層”係指距離基板170最遠的層，而“最底層”係指距離基板170最近的層。
本揭露之封裝體結構係無矽穿孔且無矽基板。封裝體結構中的重佈局層係直接與基板以及晶片連接，並提供電性互連(electrical interconnection)。本揭露之封裝體結構可藉由較簡單且較低成本的製程形成。
前面敘述之本揭露的實施方式相較於現有之封裝體結構及製程具有多個優點，其優點總結如下。製備具有矽穿孔之中介基板層的過程係複雜且高成本的。取而代之的，本揭露於封裝體結構中採用重佈局層，其係直接與基板以及晶片連接。重佈局層包含鄰近於金屬層之阻擋層。另，金屬層中的金屬組件可藉由單鑲嵌或雙鑲嵌製程編排，故所形成之金屬層中的介電層與金屬組件係共平面。本揭露提供一種較簡單且較低成本的製程以製備封裝體結構。
雖然已參照一些實施態樣來詳細說明本發明，其他的實施態樣亦是可實施的。因此，所檢附的申請專利範圍之精神及範疇應不以此處所包含的實施態樣之說明為限。
熟習此技藝可將可清楚知悉，可以對本發明的結構進行各種不同的修飾及變化而無背離本發明的範疇及精神。鑒於上述，本發明意欲涵蓋所提供的接露內容之修飾及變化，而其落入下面申請專利範圍的範疇中。
100‧‧‧封裝體結構
112‧‧‧第一鈍化層
114‧‧‧第二鈍化層
140‧‧‧重佈局層
152‧‧‧第一連接件
154‧‧‧第二連接件
156‧‧‧第三連接件
160‧‧‧晶片
170‧‧‧基板

Claims (19)

  1. 一種封裝體結構，包含：一基板；一第一連接件，設置於該基板上；複數個重佈局層，其中該些重佈局層直接相連，且該些重佈局層中之最底層的重佈局層係直接設置於該第一連接件上，並藉由該第一連接件連接至該基板，每一該些重佈局層包含：一阻擋層；以及一金屬層，位於該阻擋層上；一第二連接件，直接設置於該些重佈局層中之最頂層的重佈局層上；以及一晶片，藉由該第二連接件連接至該些重佈局層。
  2. 如申請專利範圍第1項所述之封裝體結構，其中該金屬層包含：一介電層；以及複數個金屬組件，設置於該介電層內。
  3. 如申請專利範圍第1項所述之封裝體結構，其中該第一連接件夾設於該阻擋層中，並與該金屬層連接。
  4. 如申請專利範圍第1項所述之封裝體結構，其中該阻擋層之材料為碳化矽、氮化矽或其組合。
  5. 如申請專利範圍第1項所述之封裝體結構，其中該些金屬層係水平排列，不同之該些金屬層係藉由複數個導電柱連接，且該些導電柱係貫穿該些金屬層間之該些阻擋層。
  6. 如申請專利範圍第1項所述之封裝體結構，其中該第一連接件夾設於最底層之該阻擋層中，並連接最底層之該金屬層與該基板。
  7. 如申請專利範圍第1項所述之封裝體結構，其中該第一連接件與該第二連接件係獨立為焊料凸塊或焊球。
  8. 如申請專利範圍第1項所述之封裝體結構，更包含一鈍化層，位於該基板與該重佈局層之間，且該第一連接件夾設於該鈍化層中。
  9. 如申請專利範圍第8項所述之封裝體結構，其中該鈍化層之材料為氧化矽、氮化矽、苯並環丁烯、聚醯亞胺、聚苯噁唑或其組合。
  10. 一種製備封裝體結構的方法，包含：形成一重佈局層，包含：形成一金屬層；以及 形成一阻擋層於該金屬層上；直接形成一第一連接件於該重佈局層之一第一側上；直接形成一第二連接件於該重佈局層之相對於該第一側之一第二側上；藉由該第二連接件連接該重佈局層之該第二側與一晶片；以及藉由該第一連接件連接該重佈局層之該第一側與一基板。
  11. 如申請專利範圍第10項所述之方法，其中形成該重佈局層係形成於一第一載體上。
  12. 如申請專利範圍第11項所述之方法，更包含：藉由該第一連接件連接該重佈局層之該第一側與一第二載體；以及於形成該第二連接件前，移除該第一載體。
  13. 如申請專利範圍第12項所述之方法，更包含於接合該重佈局層之該第二側與該晶片後，移除該第二載體。
  14. 如申請專利範圍第13項所述之方法，更包含：於移除該第二載體前，形成一暫時性黏合劑於該晶片 上；以及於接合該重佈局層之該第一側與該基板後，移除該暫時性黏合劑。
  15. 如申請專利範圍第10項所述之方法，其中形成該金屬層係藉由鑲嵌製程進行。
  16. 如申請專利範圍第10項所述之方法，其中形成該金屬層包含：沉積一介電層；蝕刻該介電層以形成複數個開口；以及以一金屬材料填充該些開口，以形成複數個金屬段。
  17. 如申請專利範圍第10項所述之方法，其中形成該第一連接件夾設於該阻擋層中，並與該金屬層連接。
  18. 如申請專利範圍第10項所述之方法，其中該方法包含形成複數個該重佈局層。
  19. 如申請專利範圍第10項所述之方法，更包含形成一鈍化層於該重佈局層上，且該第一連接件夾設於該鈍化層中。
TW104130803A 2015-06-04 2015-09-17 封裝體結構及其製備方法 TWI585930B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US14/731,380 US9916999B2 (en) 2015-06-04 2015-06-04 Methods of fabricating a semiconductor package structure including at least one redistribution layer

Publications (2)

Publication Number Publication Date
TW201644032A TW201644032A (zh) 2016-12-16
TWI585930B true TWI585930B (zh) 2017-06-01

Family

ID=57452036

Family Applications (1)

Application Number Title Priority Date Filing Date
TW104130803A TWI585930B (zh) 2015-06-04 2015-09-17 封裝體結構及其製備方法

Country Status (3)

Country Link
US (3) US9916999B2 (zh)
CN (2) CN106252322A (zh)
TW (1) TWI585930B (zh)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9916999B2 (en) 2015-06-04 2018-03-13 Micron Technology, Inc. Methods of fabricating a semiconductor package structure including at least one redistribution layer
KR101672641B1 (ko) * 2015-07-01 2016-11-03 앰코 테크놀로지 코리아 주식회사 반도체 디바이스의 제조 방법 및 이에 따른 반도체 디바이스
WO2017151055A1 (en) * 2016-02-29 2017-09-08 Nanyang Technological University Optical structure and method of forming the same
KR102412613B1 (ko) 2017-07-24 2022-06-23 삼성전자주식회사 반도체 패키지 및 이의 제조 방법
KR102530754B1 (ko) * 2018-08-24 2023-05-10 삼성전자주식회사 재배선층을 갖는 반도체 패키지 제조 방법
DE102018122515B4 (de) * 2018-09-14 2020-03-26 Infineon Technologies Ag Verfahren zum Herstellen eines Halbleiteroxid- oder Glas-basierten Verbindungskörpers mit Verdrahtungsstruktur
US11410968B2 (en) * 2019-10-18 2022-08-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device and method of forming the same
KR20220030051A (ko) 2020-09-02 2022-03-10 삼성전자주식회사 배선 구조체 및 이를 포함하는 반도체 패키지
US20230140738A1 (en) * 2021-10-30 2023-05-04 Raymond Won Bae Microelectronic test and package interface substrates, devices, and methods of manufacture thereof alignment improvement of interconnect on buildup redistribution layers

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201131719A (en) * 2010-01-20 2011-09-16 Taiwan Semiconductor Mfg Semiconductor device having conductive pads and a method of manufacturing the same
TW201411782A (zh) * 2012-09-10 2014-03-16 矽品精密工業股份有限公司 半導體封裝件及其製法與中介板結構

Family Cites Families (24)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7915744B2 (en) * 2005-04-18 2011-03-29 Mediatek Inc. Bond pad structures and semiconductor devices using the same
US8546189B2 (en) * 2008-09-22 2013-10-01 Stats Chippac, Ltd. Semiconductor device and method of forming a wafer level package with top and bottom solder bump interconnection
US8592992B2 (en) * 2011-12-14 2013-11-26 Stats Chippac, Ltd. Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
US8866258B2 (en) * 2009-10-06 2014-10-21 Broadcom Corporation Interposer structure with passive component and method for fabricating same
TWI401753B (zh) * 2009-12-31 2013-07-11 Advanced Semiconductor Eng 可堆疊式封裝結構之製造方法
US8508024B2 (en) * 2010-01-13 2013-08-13 Via Technologies, Inc Chip package structure and package substrate
US8518746B2 (en) * 2010-09-02 2013-08-27 Stats Chippac, Ltd. Semiconductor device and method of forming TSV semiconductor wafer with embedded semiconductor die
TW201216807A (en) 2010-10-14 2012-04-16 Unimicron Technology Crop Method for manufacturing coreless substrate and coreless substrate using the method
TWI475935B (zh) * 2011-07-08 2015-03-01 Unimicron Technology Corp 無核心層之封裝基板及其製法
TW201405758A (zh) * 2012-07-19 2014-02-01 矽品精密工業股份有限公司 具有防電磁波干擾之半導體元件
KR101411813B1 (ko) 2012-11-09 2014-06-27 앰코 테크놀로지 코리아 주식회사 반도체 디바이스 및 그 제조 방법
US9508674B2 (en) * 2012-11-14 2016-11-29 Taiwan Semiconductor Manufacturing Company, Ltd. Warpage control of semiconductor die package
US9299649B2 (en) * 2013-02-08 2016-03-29 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US8802504B1 (en) * 2013-03-14 2014-08-12 Taiwan Semiconductor Manufacturing Company, Ltd. 3D packages and methods for forming the same
US9764153B2 (en) * 2013-03-14 2017-09-19 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method of forming same
US8884427B2 (en) 2013-03-14 2014-11-11 Invensas Corporation Low CTE interposer without TSV structure
CN104051411B (zh) * 2013-03-15 2018-08-28 台湾积体电路制造股份有限公司 叠层封装结构
US9006030B1 (en) * 2013-12-09 2015-04-14 Xilinx, Inc. Warpage management for fan-out mold packaged integrated circuit
US9466560B2 (en) * 2014-05-28 2016-10-11 United Microelectronics Corp. Interposer fabricating process and wafer packaging structure
US9704735B2 (en) * 2014-08-19 2017-07-11 Intel Corporation Dual side solder resist layers for coreless packages and packages with an embedded interconnect bridge and their methods of fabrication
US10181410B2 (en) * 2015-02-27 2019-01-15 Qualcomm Incorporated Integrated circuit package comprising surface capacitor and ground plane
US10043769B2 (en) * 2015-06-03 2018-08-07 Micron Technology, Inc. Semiconductor devices including dummy chips
US9916999B2 (en) 2015-06-04 2018-03-13 Micron Technology, Inc. Methods of fabricating a semiconductor package structure including at least one redistribution layer
US10037961B2 (en) * 2016-05-17 2018-07-31 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated fan-out package and method of fabricating the same

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW201131719A (en) * 2010-01-20 2011-09-16 Taiwan Semiconductor Mfg Semiconductor device having conductive pads and a method of manufacturing the same
TW201411782A (zh) * 2012-09-10 2014-03-16 矽品精密工業股份有限公司 半導體封裝件及其製法與中介板結構

Also Published As

Publication number Publication date
TW201644032A (zh) 2016-12-16
US20180190531A1 (en) 2018-07-05
CN112185933A (zh) 2021-01-05
US10818536B2 (en) 2020-10-27
US10566229B2 (en) 2020-02-18
US20160358847A1 (en) 2016-12-08
US20200168497A1 (en) 2020-05-28
CN106252322A (zh) 2016-12-21
US9916999B2 (en) 2018-03-13

Similar Documents

Publication Publication Date Title
TWI585930B (zh) 封裝體結構及其製備方法
US10854567B2 (en) 3D packages and methods for forming the same
US10510556B2 (en) Integrated circuit package pad and methods of forming
US20210313196A1 (en) 3D Packages and Methods for Forming the Same
US11894309B2 (en) System on integrated chips (SoIC) and semiconductor structures with integrated SoIC
US8742583B2 (en) Seal ring in an integrated circuit die
US8674513B2 (en) Interconnect structures for substrate
US10163756B2 (en) Isolation structure for stacked dies
US8461045B2 (en) Bond pad connection to redistribution lines having tapered profiles
US8759949B2 (en) Wafer backside structures having copper pillars
US8691691B2 (en) TSV pillar as an interconnecting structure
US20130168850A1 (en) Semiconductor device having a through-substrate via
US8237272B2 (en) Conductive pillar structure for semiconductor substrate and method of manufacture
KR20130117329A (ko) 비아 라스트 관통 비아를 위한 방법 및 장치
KR20100100629A (ko) 3차원 ＳＩＰ(Ｓｙｓｔｅｍ―ｉｎ―Ｐａｃｋａｇｅ) 구조물
TW201611220A (zh) 方法與裝置
US9478509B2 (en) Mechanically anchored backside C4 pad
CN112086407A (zh) 集成电路封装及其形成方法
US20150048496A1 (en) Fabrication process and structure to form bumps aligned on tsv on chip backside
JP2016048743A (ja) 半導体装置及びその製造方法