CN112185933A - 包括重布局层的微电子装置 - Google Patents

包括重布局层的微电子装置 Download PDF

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Publication number
CN112185933A
CN112185933A CN202011050422.1A CN202011050422A CN112185933A CN 112185933 A CN112185933 A CN 112185933A CN 202011050422 A CN202011050422 A CN 202011050422A CN 112185933 A CN112185933 A CN 112185933A
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China
Prior art keywords
redistribution layer
microelectronic device
die
layer
metal
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CN202011050422.1A
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English (en)
Inventor
施信益
姜序
施能泰
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Micron Technology Inc
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Micron Technology Inc
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Publication of CN112185933A publication Critical patent/CN112185933A/zh
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Abstract

本发明公开了一种包括重布局层的微电子装置。该微电子装置包含基板、第一连接件、重布局层、第二连接件以及晶片。第一连接件设置于基板上。重布局层直接设置于第一连接件上，并借由第一连接件连接至基板。重布局层包含阻挡层以及位于阻挡层上的金属层。第二连接件直接设置于重布局层上，且晶片借由第二连接件连接至重布局层。借此，本发明的封装体结构及其制备方法去除硅穿孔，并省略硅基板的研磨工艺，故具有简单的制备流程以及低制备成本。

Description

包括重布局层的微电子装置
本申请为发明名称为“封装体结构及其制备方法”、申请号为201510607208.4、申请日为2015年9月22日的中国发明专利申请的分案申请。
技术领域
本发明涉及一种封装体结构及其制备方法，特别是涉及一种无穿孔的封装体结构及其制备方法。
背景技术
随着半导体装置的制造技术的演进，半导体装置的功能密度随着装置尺寸的减少而上升，以达到更高的半导体装置集成密度。结果，半导体装置的尺寸减少以及密度增加，使得对封装技术的要求更为严峻。近来，随着对较小电子装置的需求的增加，创新的封装技术是必要的。
目前，于中介层(interposer)的中介基板层发展出穿孔(through via)，其具有额外的金属层在中介基板层上，以提高半导体装置的密度。然而，形成具有穿孔的中介基板层的工艺极为复杂。
因此，目前需要发展一种改良的封装体结构及其制备方法。
发明内容
本发明的目的在于提供一种封装体结构及其制备方法，其包含较简单的制备流程，因而具有较低的成本。
本发明的一实施例是提供一种封装体结构。封装体结构包含基板、第一连接件、重布局层、第二连接件以及晶片。第一连接件设置于基板上。重布局层直接设置于第一连接件上，并借由第一连接件连接至基板。重布局层包含阻挡层以及位于阻挡层上的金属层。第二连接件直接设置于重布局层上，且晶片借由第二连接件连接至重布局层。
在本发明的多个实施方式中，金属层包含介电层以及多个金属组件。金属段是设置于介电层内。
在本发明的多个实施方式中，第一连接件夹设于阻挡层中，并与金属层连接。
在本发明的多个实施方式中，阻挡层的材料为碳化硅、氮化硅或其组合。
在本发明的多个实施方式中，封装体结构包含多个重布局层。
在本发明的多个实施方式中，这些金属层是水平排列，且不同金属层是借由多个导电柱连接，且导电柱是贯穿金属层间的阻挡层。
在本发明的多个实施方式中，第一连接件夹设于最底层的阻挡层中，并连接最底层的金属层与基板。
在本发明的多个实施方式中，第一连接件与第二连接件是独立为焊料凸块或焊球。
在本发明的多个实施方式中，封装体结构还包含钝化层，其位于基板与重布局层之间，且第一连接件夹设于钝化层中。
在本发明的多个实施方式中，钝化层的材料为氧化硅(silicon oxide)、氮化硅(silicon nitride)、苯并环丁烯(benzocyclobutene，BCB)、聚酰亚胺(polyimide，PI)、聚苯恶唑(polybenzoxazole，PBO)或其组合。
本发明的另一实施例是提供一种制备封装体结构的方法，其包含以下步骤。形成重布局层，包含形成金属层，以及在金属层上形成阻挡层。直接在重布局层的第一侧上形成第一连接件。直接在重布局层的相对于第一侧的第二侧上形成第二连接件。借由第二连接件连接重布局层的第二侧与晶片。借由第一连接件连接重布局层的第一侧与基板。
在本发明的多个实施方式中，形成重布局层是在第一载体上形成。
在本发明的多个实施方式中，制备封装体结构的方法还包含借由第一连接件连接重布局层的第一侧与第二载体。然后，在形成第二连接件前，移除第一载体。
在本发明的多个实施方式中，制备封装体结构的方法还包含在接合重布局层的第二侧与晶片后，移除第二载体。
在本发明的多个实施方式中，制备封装体结构的方法还包含在移除第二载体前，在晶片上形成暂时性粘合剂。然后，在接合重布局层的第一侧与基板后，移除暂时性粘合剂。
在本发明的多个实施方式中，形成金属层是借由镶嵌工艺进行。
在本发明的多个实施方式中，形成金属层包含沉积介电层。之后，蚀刻介电层以形成多个开口。然后，以金属材料填充开口，以形成多个金属段。
在本发明的多个实施方式中，形成第一连接件夹设在阻挡层中，并与金属层连接。
在本发明的多个实施方式中，制备封装体结构的方法包含形成多个重布局层。
在本发明的多个实施方式中，制备封装体结构的方法还包含在重布局层上形成钝化层，且第一连接件夹设于钝化层中。
与现有技术相比，本发明具有如下有益效果：本发明的封装体结构及其制备方法，借由去除硅穿孔模块以及省略硅研磨工艺，且包含较简单的制备流程，因而具有较低的成本。
参照以下的说明以及的权利要求，可更加理解本发明的特征、实施例以及优点。
应当理解的是，以上的一般叙述以及以下的详细叙述是实例，并旨在对所要求保护发明提供进一步的解释。
附图说明
为使本发明的特征、优点与实施例能更明显易懂，所附图式的说明如下：
图1A至图1L是绘示根据本发明一实施方式的制备封装体结构于各个阶段的剖视图。
具体实施方式
之后将以示例图式以详细描述本发明的各种实施方式，且在图式和说明书中使用相同的元件符号以指代相同或相似的部分。
以下将以图式公开本发明的多个实施方式，为明确说明起见，许多实务上的细节将在以下叙述中一并说明。然而，应了解到，这些实务上的细节不应用以限制本发明。也就是说，在本发明部分实施方式中，这些实务上的细节是非必要的。此外，为简化图式起见，一些现有惯用的结构与元件在图式中将以简单示意的方式绘示。
如前述的问题，制备具有硅穿孔(through-silicon-via，TSV)的中介基板层(interposer substrate layer)的中介层(interposer)以及额外的金属层在中介基板层上的工艺极为复杂。原因在于，形成具有硅穿孔的中介基板层具有多个制备步骤，其包含于中介基板层形成硅穿孔，以及执行晶背薄化(backside thinning)和化学气相沉积(chemical vapor deposition，CVD)或化学机械平坦化(chemical mechanicalplanarization，CMP)。这些制备步骤增加了晶圆处理的困难度。因此，制备具有硅穿孔的中介基板层的过程是复杂且高成本的。
本发明提供一种封装体结构及其制备方法。本发明的制备方法去除硅穿孔模块(TSV module)，并省略硅基板的研磨工艺。因此，本发明所提供的方法具有较简单的制备流程以及较低的制备成本。
请参照图1A至图1L，其是绘示根据本发明一实施方式的制备封装体结构100于各个阶段的剖视图。
如图1A所示，第一钝化层112是形成在第一载体202上。第一载体202可由硅(silicon)或玻璃制成。当第一载体202是由玻璃制成时，第一钝化层112可借由直接沉积于第一载体202上而形成，或者可在形成离型层(release layer)之后形成。在一些实施方式中，第一钝化层112是由氧化硅(SiO2)、氮化硅(SiN)、苯并环丁烯(benzocyclobutene，BCB)、聚酰亚胺(polyimide，PI)、聚苯并恶唑(polybenzoxazole，PBO)或其组合所制成。
接着，形成重布局层(redistribution layer)。重布局层包含金属层以及阻挡层，且金属层包含介电层以及设置于介电层内的多个金属组件。金属层可借由镶嵌(damascene)工艺而形成，例如单镶嵌工艺以及双镶嵌工艺。由镶嵌工艺所形成的金属层中的介电层与金属组件是共平面。在一些实施方式中，金属层120是借由以下图1B至图1D所示的工艺而形成。
图1B显示出在第一钝化层112上沉积介电层122。在一些实施方式中，介电层122是由氧化硅(SiO2)、氮化硅(Si3N4)或其组合所制成。介电层122可借由任何合适的沉积工艺而形成。沉积的实例包含但不限于化学气相沉积(chemical vapor deposition，CVD)、物理气相沉积(physical vapor deposition，PVD)、原子层沉积(atomic layer deposition，ALD)以及其组合。
接着如图1C所示，蚀刻介电层122以形成多个开口124。在一些实施方式中，开口为线、通孔、洞或沟槽。蚀刻可为干式蚀刻或湿式蚀刻。
接着如图1D所示，以金属材料填充开口124以形成多个金属组件126。在一些实施方式中，金属组件126是借由沉积而形成。在一些实施方式中，金属组件126是由铜(copper，Cu)、铝(aluminum，Al)或其组合所制成。在填充金属材料前，可于开口124的侧壁上形成隔离层。在以金属材料填充开口124后，可进行化学机械平坦化(chemical-mechanicalplanarization，CMP)工艺，以整平金属组件126与介电层122。从而形成金属层120。
请参照图1E，在金属层120上形成阻挡层130。从而形成重布局层140。阻挡层130可借由沉积而形成，例如化学气相沉积(CVD)、物理气相沉积(PVD)、原子层沉积(ALD)或其它合适的工艺。在一些实施方式中，阻挡层130是由碳化硅(silicon carbide，SiC)、氮化硅(SiN)或其组合所制成。
图1B至图1E是显示本发明多个实施方式的形成一层重布局层140的工艺。依据产品的需求，封装体结构100可包含多个重布局层140。图1F是显示具有四层重布局层140所形成的结构。值得注意的是，金属层120间的阻挡层130并非连续的，且由多个导电柱128贯穿。导电柱128连接不同金属层120中的金属组件126。在一些实施方式中，金属层120是借由单镶嵌工艺或双镶嵌工艺而形成，且部分的阻挡层130在此工艺中会被移除。导电柱128可与金属组件126一起形成。举例而言，形成包含第一介电层以及多个第一金属组件的第一金属层。接着，在第一金属层上形成第一阻挡层。然后，借由嵌工艺形成第二金属层，其是先在第一阻挡层上形成第二介电层。继续进行工艺以移除部分的第二介电层以及第一阻挡层，以形成开口。接着，以金属材料填充开口以形成第二金属组件以及贯穿第一阻挡层的导电柱。然后，在第二金属层上形成第二阻挡层。前述的步骤可重复进行，直至达到重布局层所需的层数。
接着如图1G所示，在形成多个重布局层140后，在最顶层的重布局层140上形成第二钝化层114。另外，移除部分的第二钝化层114以及最顶层的阻挡层130，以暴露出部分的最顶层的金属层120。接着，直接在最顶层金属层120的暴露部分上形成多个第一连接件152。也就是说，第一连接件152夹设于第二钝化层114以及最顶层的阻挡层130中。第二钝化层114的材料的实例可参照第一钝化层112的对应部分，并不在此赘述。在一些实施方式中，第一连接件152是焊料凸块(solder bump)或焊球(solder ball)。第一连接件152的材料可为银、铜或锡基(tin-based)组合物。第一连接件152可使用电或非电镀技术形成，或者使用网版印刷(screening printing)或喷墨印刷(jet printing)技术形成。第一连接件152也可为其它种类的连接件，例如铜柱或金柱、导电螺柱(conductive stud)以及C4凸块。
值得注意的是，此处所指的“最顶层”的金属层120或阻挡层130表示金属层120或阻挡层130与第一载体202的相对位置。也就是说，当第一载体202位于底部时，“最顶层”的金属层120或阻挡层130是位于顶部，且为距离第一载体202最远的金属层120或阻挡层130。
在一些实施方式中，形成第一连接件包含在最顶层金属层的暴露部分上形成凸块底层金属化(under-bump metallization，UBM)层，以及在凸块底层金属化层上形成第一连接体。凸块底层金属化层可为U型，且可覆盖部分的第二钝化层114。凸块底层金属化层的材料的实例包含但不限于氮化钛(TiN)、钛(Ti)、锡(Sn)、银(Ag)、铜(Cu)、金(Ag)、镍(Ni)、上述的合金以及上述的组合。
请参照图1H，图1G所示的结构借由第一连接件152以及粘合层210接合至第二载体204上。粘合层210是在接合至第二载体204上之前，在第二钝化层114上形成。
请继续参照图1H，自第一钝化层112移除第一载体202。从而暴露出第一钝化层112。如上所述，第一载体202可由硅或玻璃制成。当第一载体202是由硅制成时，第一载体202可借由研磨或湿式蚀刻移除。当第一载体202是由玻璃制成时，第一载体202可借由激光剥离(laser debonding)移除。
在与第二载体204接合以及剥离第一载体202之后，图1H是显示以第二载体204为最底层元件的结构。以下图1H至图1L相对于图1A至图1G是倒置的。
接着如图1I所示，移除部分的第一钝化层112以直接在最顶层的金属层120上形成多个第二连接件154。第二连接件154是与最顶层金属层120的金属组件126连接。第二连接件154的材料的实例可参照第一连接件152的对应部分，并不在此赘述。
值得注意的是，此处所指的“最顶层”的金属层120表示金属层120与第二载体204的相对位置。也就是说，当第二载体204位于底部时，“最顶层”的金属层120是位于顶部，且为距离第二载体204最远的金属层120。另外，图1I相对于图1G是倒置的。因此，此处所指的“最顶层的金属层120”是与前述依据图1G的“最顶层的金属层120”不同。
请参照图1J，在第二连接件154上安装多个晶片160。晶片160是借由第二连接件154连接至重布局层140。具体而言，晶片160是借由第二连接件154连接至最顶层的金属层120。同样地，此处所指的“最顶层的金属层120”是表示金属层120与第二载体204的相对位置。晶片160可为相同或不同种类的晶片。
接着如图1K所示，在晶片160上形成暂时性粘合剂220。暂时性粘合剂220是用以固定晶片160，并在后续工艺中移除第二载体204时，维持整体结构。暂时性粘合剂220可为切割胶带(dicing tape)。接着，移除第二载体204以及粘合层210。第二载体204可借由任何合适的方式移除，例如暂时性接合/剥离(temporary bonding/debonding，TB/DB)技术。举例而言，第二载体204是借由机械性剥离(mechanical debonding)或激光剥离移除。
请参照图1L，对图1K所示的结构沿着虚线进行切割工艺，以分离晶片160。接着，将切割后的结构安装在基板170上，以形成图1L所示的封装体结构100。基板170是借由第一连接件152连接至重布局层140。具体而言，基板170是借由第一连接件152连接至最底层的金属层120。从而形成封装体结构100。基板170可为板(board)，例如印刷电路板(printedcircuit board，PCB)。
值得注意的是，此处所指的“最底层”的金属层120表示金属层120与基板170的相对位置。也就是说，当基板170位于底部时，“最底层”的金属层120为距离基板170最近的金属层120。另外，图1L相对于图1G是倒置的。因此，此处所指的“最底层的金属层120”是与前述依据图1G的“最顶层的金属层120”相同。
在一些实施方式中，封装结构100还包含第三连接件156在基板170下。第三连接件156的材料的实例可参照第一连接件152的对应部分，并不在此赘述。
本发明的制备封装体结构的方法是无硅穿孔(TSV-less)且无硅基板(silicon-substrate-less)，也就是说本发明的方法去除了形成具有硅穿孔的中介基板层(interposer substrate layer)的过程。封装体结构中的重布局层是直接与基板以及晶片连接。形成的封装体结构包含邻近于金属层的阻挡层。因此，借由去除硅穿孔模块以及省略硅研磨工艺，本发明的制备封装体结构的方法包含较简单的制备流程，因而具有较低的成本。
由图1A至图1L所绘示的工艺所制备的封装结构100包含基板170、多个第一连接件152、多个第二连接件154、多个第三连接件156、多个重布局层140、第一钝化层112、第二钝化层114以及多个晶片160。基板170是设置于第三连接件156上。第一连接件152是设置于基板170上。第二钝化层114是设置于最底层的重布局层140下，且第一连接件152是夹设于第二钝化层114中。重布局层140是直接设置于第一连接件152上，且最底层的重布局层140借由第一连接件152与基板170连接。每个重布局层140包含阻挡层130以及在阻挡层130上的金属层120。每个金属层120包含介电层122以及设置在介电层122内的金属组件126。金属层120是水平排列，且不同的金属层120是借由多个导电柱128连接，其贯穿不同的金属层120间的阻挡层130。第一钝化层112是设置在最顶层的重布局层140上，且具有间隔，以使第二连接件154连接重布局层140与晶片160。第二连接件154是直接设置在最顶层的重布局层140上，且晶片160是借由第二连接件154连接至重布局层140。
具体而言，第一连接件152是夹设于最底层的阻挡层130中，并连接最顶层的金属层120与基板170。
如前所述，此处所指的“最顶层”以及“最底层”是表示与基板170的相对位置。也就是说，当基板170位于底部时，“最顶层”是指距离基板170最远的层，而“最底层”是指距离基板170最近的层。
本发明的封装体结构是无硅穿孔且无硅基板。封装体结构中的重布局层是直接与基板以及晶片连接，并提供电性互连(electrical interconnection)。本发明的封装体结构可借由较简单且较低成本的工艺形成。
前面叙述的本发明的实施方式相较于现有的封装体结构及工艺具有多个优点，其优点总结如下。制备具有硅穿孔的中介基板层的过程是复杂且高成本的。取而代之的，本发明在封装体结构中采用重布局层，其是直接与基板以及晶片连接。重布局层包含邻近于金属层的阻挡层。另外，金属层中的金属组件可借由单镶嵌或双镶嵌工艺编排，故所形成的金属层中的介电层与金属组件是共平面。本发明提供一种较简单且较低成本的工艺以制备封装体结构。
虽然已经参照一些实施例来详细说明本发明，其他的实施例也是可实施的。因此，所检附的权利要求的精神及范畴应不以此处所包含的实施例的说明为限。
本领域技术人员可将清楚知悉，可以对本发明的结构进行各种不同的修饰及变动而无背离本发明的范畴及精神。鉴于上述，本发明意欲涵盖所提供的公开内容的修饰及变动，而其落入权利要求的范畴中。

Claims (20)

1.一种微电子装置，其包括：
重布局层，其包括：
阻挡材料；
介电材料，其位于所述阻挡材料上方；及
金属段，其位于所述介电材料的开口内；
钝化材料，其位于所述重布局层上；
连接件，其直接位于所述重布局层上方，所述钝化材料直接位于最靠近所述连接件的重布局层的所述介电材料上，且所述连接件延伸穿过所述钝化材料中的开口，其中最靠近所述连接件的所述重布局层的所述介电材料和所述金属段彼此共面；及
至少一个裸片，其使用所述连接件连接到最靠近所述连接件的所述重布局层的所述金属段，所述连接件中的每一者包括与所述至少一个裸片和最靠近所述连接件的所述重布局层的所述金属段直接接触的单个导电材料。
2.根据权利要求1所述的微电子装置，其中邻近所述重布局层并且位于其相对侧上的电路仅通过所述重布局层电连接到所述至少一个裸片。
3.根据权利要求2所述的微电子装置，其还包括附加连接件，所述附加连接件延伸穿过位于所述重布局层的所述相对侧上的另一钝化材料中的开口。
4.根据权利要求3所述的微电子装置，其中所述附加连接件直接连接到最靠近所述附加连接件的重布局层的所述金属段。
5.根据权利要求3所述的微电子装置，其还包括位于所述附加连接件与最靠近所述附加连接件的重布局层的所述金属段之间的凸块底层金属化UBM材料。
6.根据权利要求1所述的微电子装置，其中位于邻近的重布局层的所述金属段之间的阻挡材料与延伸穿过所述阻挡材料的开口的通孔不连续。
7.根据权利要求1所述的微电子装置，其中最靠近所述至少一个裸片的所述重布局层的所述金属段的厚度相对大于位于所述至少一个裸片的远端的其余重布局层的所述金属段的厚度。
8.根据权利要求1所述的微电子装置，其中最靠近所述至少一个裸片的所述重布局层的所述金属段和所述介电材料中的每一者的厚度基本上彼此相等。
9.根据权利要求1所述的微电子装置，其中所述连接件包括焊料凸块或焊球，且所述重布局层的所述金属段包括铜、铝或它们的组合物。
10.根据权利要求1所述的微电子装置，其中所述钝化材料的材料组成不同于所述阻挡材料和所述介电材料中的每一者的组成。
11.根据权利要求1所述的微电子装置，其中所述微电子装置没有硅穿孔或硅基板。
12.一种微电子装置，其包括：
重布局层，其邻近基体材料，所述重布局层中的每一者包括横向邻近金属材料的介电材料；
至少一个裸片，其邻近所述重布局层，所述至少一个裸片仅通过所述重布局层电连接到所述基体材料，其中最靠近所述至少一个裸片的重布局层的所述介电材料和所述金属材料彼此共面；
钝化材料，其位于所述重布局层与所述至少一个裸片之间，所述钝化材料与最靠近所述至少一个裸片的所述重布局层的所述介电材料直接接触；及
连接件，其位于所述重布局层与所述至少一个裸片之间，所述连接件包括与所述至少一个裸片和最靠近所述至少一个裸片的所述重布局层的所述金属材料直接接触的单个元件。
13.根据权利要求12所述的微电子装置，其还包括：
另一钝化材料，其位于所述重布局层与所述基体材料之间；及
附加连接件，其位于所述重布局层和所述基体材料之间，所述附加连接件中的每一者包括将所述基体材料电连接到最靠近所述基体材料的重布局层的所述金属材料的单个元件。
14.根据权利要求13所述的微电子装置，其中所述另一钝化材料与最靠近所述基体材料的所述重布局层的所述介电材料直接接触，所述附加连接件延伸穿过所述另一钝化材料。
15.根据权利要求13所述的微电子装置，其中：
所述连接件提供所述至少一个裸片与最靠近所述至少一个裸片的所述重布局层的所述金属材料之间的直接物理连接；及
所述附加连接件提供所述基体材料的电路与最靠近所述基体材料的所述重布局层的所述金属材料之间的直接物理连接。
16.根据权利要求12所述的微电子装置，其中通过所述重布局层提供所述至少一个裸片与所述基体材料之间的电连接，而不使用硅穿孔。
17.根据权利要求12所述的微电子装置，其中所述重布局层中的每一者包括：
阻挡材料，其邻近所述介电材料和所述金属材料中的每一者；及
通孔，其延伸穿过所述阻挡材料并连接邻近的重布局层的所述金属材料。
18.根据权利要求12所述的微电子装置，其中所述钝化材料包括包含氧化硅、氮化硅、苯并环丁烯、聚酰亚胺、聚苯并恶唑或它们的组合物的材料的单个层。
19.根据权利要求12所述的微电子装置，其还包括位于所述介电材料和所述金属材料的邻近的侧壁之间的障碍物材料。
20.根据权利要求12所述的微电子装置，其还包括位于所述基体材料的相对侧上的互连结构，其中所述基体材料包括印刷电路板。
CN202011050422.1A 2015-06-04 2015-09-22 包括重布局层的微电子装置 Pending CN112185933A (zh)

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US20160358847A1 (en) 2016-12-08
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US9916999B2 (en) 2018-03-13

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