201216807 六、發明說明： 【發明所屬之技術領域】 本發明係關於一種無核心層基板及無核心層基板之製造 方法’特別是一種具有有機層之無核心層基板及無核心層基 之製造方法。 【先前技術】 石夕穿孔(Through Silicon Via，TSV)封裝，係透過以垂直導 通來整合晶圓堆疊的方式，以達到晶片間的電氣互連。這項技 術將大幅度提咼晶片的晶體管立體密度(非平面），使半導體產 業可以超越摩爾定律的發展速度。TSV封裝的等級是L/s〈 1^10使用矽(Silicon)載板使用是半導體製程，其製造成本過 高’約為覆晶球閘陣列封裝(FCBGA)之製造成本的4倍。 然而’積體電路載板(IC carrier)產業使用介電材料的熱膨 ，係數(coefficient of thermal expansion，CTE)與矽相差過大，可 月b會有可靠度上的問題。除此之外，積體電路載板亦有厚度較 厚之缺失，對厚度需求上要薄之產品，無法符合要求。 因此，有必要提供一種無核心層基板及無核心層基板之 製造方法，以克服先前技術所存在的問題。 【發明内容】 本發明之主要目的係在提供一種無核心層基板及無核心 層基板之製造方法。 本發明之無核心層基板之製造方法包括下列步驟··提供 ，，，於載板之表面形成圖案化之第一線路層；於第一線路層 ，成圖案化之有機層；於有機層上形成第二線路層；及移 载板。 在本發明之一實施例中，有機層之材質包括玻纖含浸兩 種不同樹脂的雙層介電材、包含兩種脂的雙層介電材、 201216807 模型塑料(molding compound)或聚亞醯胺(p〇iyimide，ρι)。 本發明之無核心層基板包括有機層、第一線路層及第二 線路層。其中有機層之材質包括玻纖含浸兩種不同樹脂的雙層 介電材、包含兩種不同樹脂的雙層介電材、模型塑料(m〇lding compound)或聚亞醯胺(p〇iyimide，PI)。第一線路層係設置於 有機層之表面。第二線路層係設置於有機層之另一表面°。、 在本發明之一實施例中，有機層包括至少一線路枰 少-穿孔，在於有機層上軸第二線路層之麵巾包括 槽或至少一穿孔内形成第二線路層；且至少一線路槽二 穿孔係以雷射在有機層上進行加工形成。 在本發明之-實施例中，第二線路層之線寬/線 (Line / Space ratio)實質上包括 4/4、5/5、6/6、7/7 广 9/)9或10/10;且至少一穿孔之深度實質上係35至幻微米以 【實施方式】 為讓本創作之上述和其他目的、特徵和優點能 顯易懂，下文特舉出較佳實施例，並配合所附圖 詳細說明如下。 、作 一本發明^實施例之示意圖均為簡化後之示意圖 以示意方式說明本發明之無核心層基板之製造 所顯示之元件非為實際實施時之態樣，其實際實施^ 元件數目、形狀及尺寸比例為一選擇性之設計，且< 件佈局型態可更為複雜。 A% 以下請參考圖1，關於依據本發明之一實施 核心層基板之製造方法之步驟流程圖。 “、、 如圖1所示，本發明之無核心層基板之製造 先進行步驟S71 :提供載板。 *首 如圖2所示，本發明提供載板1〇，在本發明之一 實施例中，载板10係使用銅箔基板，但本發明不以此 201216807 為限；舉例來說，載板10亦可使用玻璃纖維板(如FR_4 基板）、鋁板或聚對苯二甲酸乙二酯（PET)板。本發明之 載板10只要具有足夠之支撐強度和拉伸強度，亦不限 於上述之材料。 接著進行步驟S72 ··於載板之表面形成圖案化之第一 線路層。 在本發明之一實施例中，本發明可先將一金屬層貼 於載板10(如圖2所示）之表面，載板1〇與金屬層之間係貼 覆二層矽膠(圖未示），矽膠係用以提供載板1〇與金屬層間之 覆著力，但本發明不以此為限。在本發明之一實施例中，金屬 層之材質係銅或銅合金，但本發明不以此為限。如圖2所示， 此金屬層經蝕刻後形成圖案化之第一線路層2〇，但本發明不 以蝕刻之後製為限；舉例來說，亦可以直接增層之方法在載板 10之表面形成圖案化之第一線路層20。由於形成圖案化線路 之方法已經在相關技術領域中被廣泛使用，且並非本發明所要 改進之重點所在，故在此不再贅述其詳細的製作方式。 須注意的是，本發明係可同時在載板10之上、下表面同 時形成圖案化之線路層，上、下表面之圖案化之線路層之線路 佈設亦可不同，為了方便說明起見，故之後僅說明處理載板 10之上表面之圖案化之第一線路層2〇。 接著進行步驟S73 :於第一線路層上形成圖案化之有機 層。 如圖3所示，在本發明之一實施例中，本發明先於第一 線路層20上覆蓋一有機層30，有機層3〇之材質係聚亞醯胺 (polyimide，H)，但本發明不以此為限；舉例來說，有機層3〇 之材質亦可為模型塑料(molding compound)，譬如電木粉 (phenolic molding compound)、尿素粉（urea M〇ldin^ Compound)、玻璃纖維(bulk molding compound) ' 不飽合聚脂 (polyester molding compound)等；有機層30之材質亦可為^纖 含浸兩種不同樹脂的雙層介電材或包含兩種不同樹脂的雙層 201216807 介電材等。 本發明接著使用雷射在有機層30上進行加工以使有 機層形成圖案化之有機層30。在本發明之一實施例中，有機 層30包括複數線路槽31和複數穿孔32，各穿孔32係與第一 線路層20相連接，但本發明不以此為限。在本發明之一實施 例中’形成圖案化之有機層30之方式係以雷射在有機層30 上進行加工，雷射可為二氧化碳(C02)雷射、紫外光 (ultraviolet, UV)雷射或準分子雷射(excimer laser)，但本發明不 以此為限。在本發明之一實施例中，二氧化碳雷射或紫外光 雷射係用於成形穿孔32，準分子雷射係用於成形線路槽31， 但本發明不以此為限。在本發明之一實施例中，有機層30之 厚度實質上係不超過100微米（em)。 在本發明之一實施例中，線路槽31之線寬/線距比(Line / Space ratio, L/S)實質上包括 4/4、5/5、6/6、7/7、8/8、 9/9或10/10等’但本發明不以此為限。在本發明之一實 施例中，當各線路槽31之L/S為4/4或5/5時，線路槽31 之深度分別係3微米（em)至5微米（//m)或4微米（ym)至6 微米（/zm);當各線路槽31之L/S為6/6、7/7、8/8、9/9 或10/10時，線路槽31之深度分別係4微米（// m)至8微米（// m)、5微米（wm)至9微米〇m)、6微米（/zm)至1〇微米（/zm)、 7微米（/zm)至11微米（//m)或8微米Mm)至12微米（/zm)， 但本發明不以此為限。在本發明之一實施例中’穿孔32之深 度實質上可介於35微米（//m)至40微米（//m)之間，但本發明 不以此為限。 接著進行步驟S74 :於有機層上形成第二線路層。 本發明可先對線路槽31及穿孔32進行去污 (desmear)或除渣（smear-remove)，接著如圖4所示， 於有機層30之各線路槽31或各穿孔32内形成第二線路 層40 ,第二線路層40之材質實質上係銅或銅合金，但 本發明不以此為限。在本發明之一實施例中，可先在有 201216807 機層30及其線路槽31和穿孔32先化學鍍再電鍍之方式 形成第二線路層40，但本發明不以此為限。 接著進行步驟S75 :對第二線路層進行表面處理。 在本發明之一實施例中，表面處理包括化學機械研 磨（chemical-mechanical planarization, CMP)，以清潔第201216807 VI. Description of the Invention: [Technical Field] The present invention relates to a method for manufacturing a coreless substrate and a coreless substrate, in particular, a coreless substrate having an organic layer and a method for manufacturing a coreless layer . [Prior Art] The Through Silicon Via (TSV) package integrates the wafer stack by vertical conduction to achieve electrical interconnection between the wafers. This technology will significantly increase the transistor's stereo density (non-planar), allowing the semiconductor industry to surpass Moore's Law. The rating of the TSV package is L/s<1^10. The use of a silicon carrier is a semiconductor process, which is too expensive to manufacture, which is about four times the manufacturing cost of a flip-chip ball grid array package (FCBGA). However, the IC carrier industry uses a thermal expansion coefficient (CTE) of dielectric materials that is too large for 矽, which can cause reliability problems in the monthly b. In addition, the integrated circuit carrier board also has a lack of thick thickness, and the product with a thin thickness requirement cannot meet the requirements. Therefore, it is necessary to provide a method of manufacturing a coreless substrate and a coreless substrate to overcome the problems of the prior art. SUMMARY OF THE INVENTION A primary object of the present invention is to provide a method for manufacturing a coreless substrate and a coreless substrate. The method for manufacturing a coreless substrate of the present invention comprises the steps of: forming a patterned first circuit layer on a surface of a carrier; forming a patterned organic layer on the first circuit layer; and forming an organic layer on the organic layer; Forming a second circuit layer; and transferring the board. In an embodiment of the invention, the material of the organic layer comprises a double-layer dielectric material impregnated with two different resins by glass fiber, a double-layer dielectric material containing two kinds of fat, 201216807 molding compound or polyarylene. Amine (p〇iyimide, ρι). The coreless substrate of the present invention comprises an organic layer, a first wiring layer and a second wiring layer. The material of the organic layer includes a double-layer dielectric material impregnated with two different resins by glass fiber, a double-layer dielectric material containing two different resins, a m〇lding compound or a polydecylamine (p〇iyimide, PI). The first wiring layer is disposed on the surface of the organic layer. The second wiring layer is disposed on the other surface of the organic layer. In an embodiment of the present invention, the organic layer includes at least one line reduction-perforation, wherein the surface of the second circuit layer of the upper layer of the organic layer includes a groove or at least one perforation to form a second circuit layer; and at least one line The groove two perforations are formed by laser processing on the organic layer. In the embodiment of the invention, the line/space ratio of the second circuit layer substantially comprises 4/4, 5/5, 6/6, 7/7 wide 9/) 9 or 10/ The above and other objects, features and advantages of the present invention are apparent from the following description. The drawings are described in detail below. BRIEF DESCRIPTION OF THE DRAWINGS The schematic diagrams of the present invention are simplified to illustrate the schematic representation of the components of the coreless substrate of the present invention as shown in the actual implementation, and the actual implementation of the number and shape of components And the size ratio is a selective design, and the < piece layout type can be more complicated. A% Referring now to Figure 1, there is shown a flow chart of the steps of a method of fabricating a core layer substrate in accordance with one embodiment of the present invention. As shown in FIG. 1, the manufacturing of the coreless substrate of the present invention first proceeds to step S71: providing a carrier. * First, as shown in FIG. 2, the present invention provides a carrier board, in an embodiment of the present invention. In the middle, the carrier 10 is a copper foil substrate, but the invention is not limited to this 201216807; for example, the carrier 10 may also use a fiberglass board (such as an FR_4 substrate), an aluminum plate or polyethylene terephthalate ( The PET board is not limited to the above materials as long as it has sufficient supporting strength and tensile strength. Next, step S72 is performed to form a patterned first wiring layer on the surface of the carrier. In one embodiment of the present invention, the present invention may first attach a metal layer to the surface of the carrier 10 (shown in FIG. 2), and apply a two-layer adhesive between the carrier 1 and the metal layer (not shown). The silicone is used to provide the adhesion between the carrier and the metal layer, but the invention is not limited thereto. In one embodiment of the invention, the material of the metal layer is copper or copper alloy, but the invention does not This is limited. As shown in Figure 2, the metal layer is etched to form a patterned first line. The road layer is 2 〇, but the present invention is not limited to the post-etching process; for example, the patterned first wiring layer 20 may be formed on the surface of the carrier 10 by directly layering. Due to the method of forming the patterned circuit It has been widely used in the related art, and is not the focus of improvement of the present invention, so its detailed production method will not be described herein. It should be noted that the present invention can be simultaneously above and below the carrier 10. The patterned circuit layer is simultaneously formed on the surface, and the circuit layout of the patterned circuit layer on the upper and lower surfaces may be different. For the convenience of description, only the patterned first line for processing the upper surface of the carrier 10 will be described hereinafter. Step 2: Next, step S73 is performed to form a patterned organic layer on the first circuit layer. As shown in FIG. 3, in an embodiment of the present invention, the present invention is overlaid with an organic layer on the first circuit layer 20. The material of the layer 30 and the organic layer 3 is polyimide (H), but the invention is not limited thereto; for example, the material of the organic layer 3 can also be a molding compound, for example, Electric wood powder (pheno Lic molding compound), urea powder (urea M〇ldin^ Compound), glass molding compound 'polyester molding compound', etc.; organic layer 30 can also be made of two different types of fiber impregnation A double layer dielectric of resin or a double layer 201216807 dielectric material comprising two different resins, etc. The present invention then uses a laser to process the organic layer 30 on the organic layer 30 to form an organic layer 30. In one embodiment, the organic layer 30 includes a plurality of line trenches 31 and a plurality of vias 32. Each of the vias 32 is connected to the first circuit layer 20, but the invention is not limited thereto. In one embodiment of the invention, the manner in which the patterned organic layer 30 is formed is processed by laser on the organic layer 30. The laser may be a carbon dioxide (C02) laser or an ultraviolet (UV) laser. Or an excimer laser, but the invention is not limited thereto. In one embodiment of the invention, a carbon dioxide laser or ultraviolet laser is used to form the perforations 32, and an excimer laser is used to form the line grooves 31, but the invention is not limited thereto. In one embodiment of the invention, the thickness of the organic layer 30 is substantially no more than 100 microns (em). In an embodiment of the invention, the line/space ratio (L/S) of the line slot 31 substantially includes 4/4, 5/5, 6/6, 7/7, 8/. 8, 9/9 or 10/10, etc. 'But the invention is not limited thereto. In an embodiment of the present invention, when the L/S of each of the line grooves 31 is 4/4 or 5/5, the depth of the line groove 31 is 3 micrometers (em) to 5 micrometers (//m) or 4, respectively. Micrometer (ym) to 6 micrometers (/zm); when the L/S of each line slot 31 is 6/6, 7/7, 8/8, 9/9 or 10/10, the depth of the line slot 31 is respectively 4 micrometers (//m) to 8 micrometers (//m), 5 micrometers (wm) to 9 micrometers (m), 6 micrometers (/zm) to 1 micron (/zm), 7 micrometers (/zm) to 11 micrometers (//m) or 8 micrometers Mm) to 12 micrometers (/zm), but the invention is not limited thereto. In one embodiment of the invention, the depth of the perforations 32 may be substantially between 35 microns (//m) and 40 microns (//m), although the invention is not limited thereto. Next, step S74 is performed: forming a second wiring layer on the organic layer. In the present invention, the line groove 31 and the through hole 32 may be desmear or smear-remove, and then, as shown in FIG. 4, a second line is formed in each of the line grooves 31 or the perforations 32 of the organic layer 30. The material of the circuit layer 40 and the second circuit layer 40 is substantially copper or a copper alloy, but the invention is not limited thereto. In an embodiment of the present invention, the second wiring layer 40 may be formed by first electroless plating and replating the 201216807 layer 30 and its line grooves 31 and the through holes 32, but the invention is not limited thereto. Next, step S75 is performed: surface treatment is performed on the second circuit layer. In one embodiment of the invention, the surface treatment comprises chemical-mechanical planarization (CMP) to clean the surface
二線路層40及使第二線路層40平整，但本發明之表面 處理不以化學機械研磨為限。在本發明之一實施例中， 在對第二線路層40進行表面處理後，可在第二線路層 4〇以/外的f面上綠漆（圖未示），但本發明不以此為限二 須注意的是，在本發明之一實施例中，有機層30、 線路層20及第二線路層40實質上係成為一體，其 :第一線路層20及第二線路層4〇係分別位於有機層3〇 兩側。 與第錄鑛鄕-線闕，並將栽板 in圖5所不’將有機層30連同第一線路層20自載柄 ㈣3G翻面再貼回載板，須注意Ϊ 二實施例中，此時有機磨30、第4 id:S77:對第一線路層進行表面處理。 不在=面處理之實施方式已在上述實施例說明，故 «：後進行步驟S78:移除載板。 ^ 30 ^ 本發明之無核心層以1自載板1G移除後’即為 為銅羯基板，“二m明之—實施例中，若載板10 包括發r之-實施例中，本發明之無核心層基板1 20 2〇 40〇 係“又置於有機層3G之表面。第二線路層40係設置於有機 201216807 層30之另一表面。 兩層之無基f板1之製造方法雖以製造 層基板1為限。 旦本表明不以製造兩層之無核心 可形成-立體之積體雷丄i之中"層(mterposer) ’如此’ 電路6i間之_介声，核心層基板1若作為各積體 ίίί ’設置職之金屬歸(UBM)51;或在無核 與基板62電性相通處，設置對應 不以此為限。 z但本發明 綜上所陳，本發明無論就目的、手段及功效， =顯不其迥異於習知技術之特徵，懇請貴審查委 察，早曰賜准專利，俾嘉惠社會，實感德便。惟 的疋，上述諸多實施例僅係為了便於說明而舉例已二 ^發明所主張之權利範圍自應以申請專利範圍 _ 準’而非僅限於上述實施例。 …、 【圖式簡單說明】 圖1係關於本發明之無核心層基板之製造方法一 施例之步驟流程圖。 夏 圖2至圖6係關於本發明之無核心層基板之製 一實施例之流程剖視圖。 绝方法之 ^ J圖係關於本發明之無核心層基板之一實施例之應用 【主要元件符號說明】 無核心層基板1 載板10 第一線路層20 8 201216807 有機層30 線路槽31 穿孔32 第二線路層40 金屬墊層51 錫球焊墊52 積體電路61 基板62The second wiring layer 40 and the second wiring layer 40 are flattened, but the surface treatment of the present invention is not limited to chemical mechanical polishing. In an embodiment of the present invention, after the surface treatment of the second circuit layer 40, green paint (not shown) may be formed on the f-plane of the second circuit layer 4, but the present invention does not It should be noted that, in an embodiment of the present invention, the organic layer 30, the circuit layer 20, and the second circuit layer 40 are substantially integrated, and the first circuit layer 20 and the second circuit layer 4 They are located on both sides of the organic layer 3〇. And the first record of the miner-line 阙, and the board is not shown in Figure 5, the organic layer 30 together with the first circuit layer 20 self-loading handle (4) 3G turned over and back to the carrier board, it should be noted that in the second embodiment, this Time Organic Grinding 30, 4th id: S77: Surface treatment of the first wiring layer. The embodiment that is not in the face processing has been explained in the above embodiment, so «: after step S78: the carrier is removed. ^ 30 ^ The coreless layer of the present invention is removed from the carrier 1G, which is a copper germanium substrate, "two m Ming - in the embodiment, if the carrier 10 includes a hair - in the embodiment, the present invention The coreless substrate 1 20 2 〇 40 “ is placed on the surface of the organic layer 3G. The second wiring layer 40 is disposed on the other surface of the organic 201216807 layer 30. The manufacturing method of the two-layer non-base f-plate 1 is limited to the production of the layer substrate 1. It is indicated that the core layer substrate 1 is not used to form a two-layer core-free layer. 'Setting the metal back (UBM) 51; or in the non-core and the substrate 62 electrical connection, the setting is not limited to this. z However, the present invention has been comprehensively described. The present invention, regardless of its purpose, means, and efficacy, is not surprisingly different from the characteristics of the prior art, and is requested to review the examination, granting patents as early as possible, 俾嘉惠社会,实感德Will. However, the above-described embodiments are merely for convenience of description. The scope of the claims is intended to be within the scope of the patent application and not limited to the above embodiments. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a flow chart showing the steps of an embodiment of a method for manufacturing a coreless substrate of the present invention. Fig. 2 to Fig. 6 are cross-sectional views showing the flow of an embodiment of the coreless substrate of the present invention. The invention is applied to an embodiment of the coreless substrate of the present invention. [Main component symbol description] Coreless substrate 1 Carrier 10 First circuit layer 20 8 201216807 Organic layer 30 Line groove 31 Perforation 32 Second circuit layer 40 metal pad layer 51 solder ball pad 52 integrated circuit 61 substrate 62