KR101128584B1 - Manufacturing Method of Coreless Substrate for Package of Semiconductor, and Coreless Substrate Using the same - Google Patents

Abstract

The present invention relates to a method for manufacturing a coreless substrate for a semiconductor package and a coreless substrate using the same, a) a copper foil formed of an insulating material, a primer resin, and copper on a copper post on a carrier coated with a copper seed on an upper surface thereof. Lay-up (Lay-up); b) removing a portion of the copper foil and the insulating material protruding from the copper post through a polishing process; c) removing copper remaining on the surface by etching; d) forming roughness on top of the primer resin and applying a chemical copper seed; e) forming a circuit pattern in a region corresponding to the upper copper post of the top of the copper copper seed; can be secured by only the copper copper seed without a separate seed layer, such as Ti, Ni-Cr, Cr, Because of the application of the chemical copper seed, an additional etching process is not required and the effect of the process procedure can be simplified.

Description

Manufacturing Method of Coreless Substrate for Package of Semiconductor, and Coreless Substrate Using the Same

The present invention relates to a method for manufacturing a coreless substrate for a semiconductor package and a coreless substrate using the same, and more particularly, to a method for manufacturing a coreless substrate for a semiconductor package and a coreless using the same for improving adhesion reliability between layers in a multilayer substrate. It relates to a substrate.

With the miniaturization and density of electronic devices and semiconductor packages, the importance of interlayer connection that enables package substrates or high-density wiring, high-density multilayer technology, and the like is increasing.

As the number of chips and their density increase due to the increase in density, the printed circuit board stacks vias to increase heat dissipation characteristics of heat generated from the chips, thereby minimizing signal transmission distance and improving heat dissipation characteristics. Try to maximize it.

At this time, in order to stack vias, holes for conduction are formed by laser processing, and interlayer connection is performed through plating.

Currently, the above-described Build Up technology using a laser drill has been developed and applied to a general purpose.

In the via forming method, numerous interlayer connection methods have been proposed for the purpose of high density and low cost, including a method of forming a via using a laser, and a method of forming a via through exposure and development.

Among them, the typical drill process and plating process can be omitted by using a conductive paste bump as a via. Laser processing is performed by increasing the number of holes due to the recent increase in input / output (I / O). As costs are increasing, a number of measures are being developed to reduce them.

Meanwhile, a process for securing interlayer adhesion in a multilayer substrate includes Ti / Cu, Ni-Cr / Cu, Cr / Cu, etc., in order to secure adhesion with an insulating material whose pattern formed on a Cu Post Via is polished. A separate seed layer is required, and a process of removing an unnecessary seed layer after forming a pattern is separately required.

Accordingly, the present invention has been made to solve the above-described problems, the copper post (Cu Post) is formed through exposure and development, and the surface after removing the resin on the upper copper post in the polishing process for the interlayer connection after laminating the insulating layer It is an object of the present invention to provide a coreless substrate manufacturing method for a semiconductor package having an interlayer connection structure having excellent reliability and a coreless substrate using the same so as to secure close contact reliability.

In order to achieve the above object, a method of manufacturing a coreless substrate for a semiconductor package according to an embodiment of the present invention includes a) an insulating material, a primer resin, and a copper foil (Cu Foil) on an upper surface of a copper post on a carrier coated with a copper seed; Lay-up; b) flattening by removing a portion of the copper foil and the insulating material protruding from the copper post; c) removing copper remaining on the surface by etching; d) forming roughness on top of the primer resin and applying a chemical copper seed; e) forming a circuit pattern on a region corresponding to an upper portion of a copper post among the upper side of the chemical copper seed.

Here, it is preferable that the insulating material is made of glass and resin.

In addition, the primer resin is preferably made of a material for SAP (Semi Additive Process).

In addition, before the step a), a-1) laminating a dry film resist (DFR) on the carrier and forming a hole for copper post fill plating through an exposure and development process; It is preferable to include.

In addition, after the step a-1), a-2) forming a copper post by performing a copper post fill (Cu Post Fill) plating to the hole; preferably further comprises a.

In addition, in the step a-2), the copper post peel plating may be formed so that copper is over plated onto the DFR.

Further, after step a-2), the copper posts are polished to planarize the copper posts; Peeling the DFR; preferably further comprises.

In addition, after the step e), repeating the copper post formation to form a multi-layer substrate; After forming the seed on the last formed top layer, separating the substrate from the carrier; preferably further comprises.

In addition, after the step of separating the substrate,

Forming a circuit pattern on the uppermost layer and the lowermost layer, and performing a solder resist and surface treatment, it is preferable to further include.

Another coreless substrate for semiconductor packages of this invention is a copper post; An insulating layer formed on the same layer as the copper post except for the region where the copper post is disposed; A primer resin stacked on the insulating layer and formed to have the same height as that of the copper post; And a circuit pattern formed on the copper post, wherein the copper post, the insulating layer, the primer resin, and the circuit pattern may be formed of a plurality of layers.

Moreover, it is preferable that the said coreless board | substrate further forms a circuit pattern on the copper post of the uppermost layer and the lowermost layer of the said several layer.

In the coreless substrate, after forming a circuit pattern on the top and bottom copper posts, it is preferable to perform solder resist coating and surface treatment.

The method of manufacturing a coreless substrate for a semiconductor package and a coreless substrate using the same according to the present invention can secure adhesion by only chemical copper seed without a separate seed layer such as Ti, Ni-Cr, Cr, and the like. As a result, a separate etching process is not required and the effect of the process procedure can be simplified.

In addition, since the present invention polishes the upper portion of the copper foil, the polishing amount is smaller than that of the insulating material, and it is advantageous in that the insulation distance deviation can be reduced while only exposing the copper posts effectively, thereby improving strength in terms of impedance of SIP products compared to the existing method. The advantage is that it can have.

1 to 16 are cross-sectional views shown in accordance with the manufacturing process sequence of the coreless substrate according to the present invention.

Hereinafter, specific embodiments of the present invention will be described with reference to the drawings. However, this is only an example and the present invention is not limited thereto.

In describing the present invention, when it is determined that the detailed description of the known technology related to the present invention may unnecessarily obscure the subject matter of the present invention, the detailed description thereof will be omitted. The following terms are defined in consideration of the functions of the present invention, and may be changed according to the intention or custom of the user, the operator, and the like. Therefore, the definition should be based on the contents throughout this specification.

The technical spirit of the present invention is determined by the claims, and the following embodiments are merely means for efficiently explaining the technical spirit of the present invention to those skilled in the art.

1 to 16 are cross-sectional views shown in accordance with the manufacturing process sequence of the coreless substrate according to the present invention.

First, as shown in FIGS. 1 and 2, a dry film resist (DFR, hereinafter referred to as DFR) 120 on an upper surface of the carrier 110 on which the copper seed 111 is applied. May be stacked, and a hole for copper post fill plating may be formed through an exposure and development process.

In addition, as shown in FIG. 3, a copper post 130 may be formed on the hole to form a copper post fill plating.

Here, the copper post peel plating may be formed so that copper is over plated onto the DFR 120, as shown in FIG. 3.

4 to 6, the copper posts 130 may be polished to planarize the copper posts 130, and the DFR 120 may be peeled off.

For example, the polishing process is to perform polishing of a part of the DFR and the copper post overplated onto the DFR based on the line AA ′ of FIG. 4. In this case, the polishing method may be generally applied to a known technique.

In addition, as shown in FIG. 7, the insulating material 140, the primer resin 150, and the copper foil 160 are laid up on the copper post on the carrier on which the copper seed is coated on the upper surface. (Lay-up)

Here, the insulating material 140 may be made of glass and resin.

In addition, the primer resin may be made of a material for Semi Additive Process (SAP).

As illustrated in FIGS. 8 and 9, the insulating material and the copper foil protruding from the upper portion of the copper post 130 (FIG. 8B) and the copper foil may be removed and planarized.

For example, the protrusions (insulation material and copper foil) protruding due to the copper posts 130 are removed based on C-C 'of FIG. 9.

Here, the laminated subsidiary material with a cushion may be further laminated on the upper surface of the copper foil 160. Due to the laminated subsidiary material, some insulating material remains on top of the copper posts, which can be removed with a portion of the copper foil through a polishing process.

10 to 11, the copper 160 remaining on the surface can be removed through etching.

In addition, as shown in FIG. 12, roughness may be formed on the primer resin and the chemical copper seed 170 may be applied. Here, the roughness may use roughness of the copper foil mat surface.

In addition, the circuit pattern 180 may be formed in a region corresponding to the upper portion of the copper post 130 among the upper side of the chemical copper seed 170.

Thereafter, as shown in FIG. 13, copper post formation can be repeated to form a multilayer substrate.

For example, it may be formed of a multilayer substrate of L4 as shown in FIG. 13.

In addition, as shown in FIG. 14, after the seed 190 is formed on the last uppermost layer, the substrate may be separated from the carrier 110.

In addition, as illustrated in FIGS. 15 and 16, the circuit pattern 200 may be formed on the uppermost layer and the lowermost layer, and the coreless substrate 300 may be completed by performing solder resist and surface treatment 210. .

As described above, when the insulating material and the SAP material are laminated on the copper post, a part of the insulating material on the copper post may protrude. After removing part of the copper foil by polishing while the primer resin, which is an SAP material, is left, the primer resin remains in the rough form when the copper foil is etched.

At this time, since the copper foil mat (Cu Foil Matte) has a roughness, the interlayer adhesion of the substrate can be increased.

Hereinafter, a coreless substrate according to the method for manufacturing a coreless substrate for a semiconductor package will be described.

As shown in FIG. 16, the coreless substrate 300 includes an insulating layer 140 and an insulating layer formed on the same layer as the copper post 130 except for a region where the copper post 130 and the copper post 130 are disposed. A primer resin 150 may be stacked on the copper post 130 to have the same height as the upper surface of the copper post 130, and a circuit pattern 200 formed on the copper post 130.

The coreless substrate 300 may have a structure of a multilayer substrate in which the copper post 130, the insulating layer 140, the primer resin 150, and the circuit pattern 200 having the above-described configuration are formed of a plurality of layers. .

In addition, the coreless substrate 300 may further form a circuit pattern 200 on a plurality of uppermost and lowermost copper posts.

In addition, the coreless substrate 300 may form a circuit pattern on the top and bottom copper posts, and then perform solder resist coating and surface treatment 210.

The present invention can secure the interlayer adhesion of the substrate without the formation of a separate seed layer made of a material such as Ti, Ni-Cr, Cr, and can be expected that the seed etching process is not required additionally.

While the present invention has been particularly shown and described with reference to exemplary embodiments thereof, it is clearly understood that the same is by way of illustration and example only and is not to be construed as limiting the scope of the present invention. I will understand.

Therefore, the scope of the present invention should not be limited to the described embodiments, but should be defined by the claims below and equivalents thereof.

110: carrier
111: copper seed
120: DFR (Dry Film Resist)
130: copper post
140: insulation material
150: primer resin
160: Cu Foil
200: circuit pattern
300 coreless substrate

Claims (12)

a) laying up an insulating material, a primer resin (Primer Resin) and a copper foil (Cu Foil) on top of a copper post on a carrier coated with a copper seed;
b) flattening by removing a portion of the copper foil and the insulating material protruding from the copper post;
c) removing copper remaining on the surface by etching;
d) forming roughness on top of the primer resin and applying a chemical copper seed;
e) forming a circuit pattern on an area corresponding to an upper copper post of the upper part of the chemical copper seed;
Coreless substrate manufacturing method for a semiconductor package comprising a.
The method of claim 1,
The insulating material is a method for manufacturing a coreless substrate for a semiconductor package, characterized in that the glass (glass) and resin (Resin).
The method of claim 2,
The primer resin is a method for manufacturing a coreless substrate for a semiconductor package, characterized in that the material is made of SAP (Semi Additive Process) material.
The method of claim 3,
Before step a),
a-1) laminating a dry film resist (DFR) on the carrier and forming a hole for copper post fill plating through an exposure and development process;
A method for manufacturing a coreless substrate for a semiconductor package, further comprising.
The method of claim 4, wherein
After step a-1),
a-2) forming a copper post by performing copper post fill plating on the hole;
A method for manufacturing a coreless substrate for a semiconductor package, further comprising.
The method of claim 5,
In step a-2),
The copper post peel plating is a method of manufacturing a coreless substrate for a semiconductor package, characterized in that the copper is formed over plating (Over Plating) over the DFR.
The method of claim 6,
After step a-2),
Polishing the copper posts to planarize the copper posts;
Stripping the DFR;
A method for manufacturing a coreless substrate for a semiconductor package, further comprising.
The method of claim 3,
After step e),
Repeating copper post formation to form a multilayer substrate;
Forming a seed on the last formed top layer, then separating the substrate from the carrier;
A method for manufacturing a coreless substrate for a semiconductor package, further comprising.
The method of claim 8,
After the step of separating the substrate,
Forming a circuit pattern on the uppermost layer and the lowermost layer, and performing solder resist and surface treatment;
A method for manufacturing a coreless substrate for a semiconductor package, further comprising.
Copper posts;
An insulating layer formed on the same layer as the copper post except for the region where the copper post is disposed;
A primer resin stacked on the insulating layer and formed to have the same height as that of the copper post, and having roughness formed thereon;
A circuit pattern formed on the copper post;
The copper post, the insulating layer, the primer resin and the circuit pattern are formed of a plurality of layers, wherein the roughness of the primer resin is formed by the roughness of the copper foil which is attached to the top of the primer resin and then removed by etching. Coreless substrate.
The method of claim 10,
The coreless substrate,
And forming a circuit pattern on the uppermost and lowermost copper posts of the plurality of layers.
The method of claim 11,
The coreless substrate,
Forming a circuit pattern on the uppermost and lowermost copper posts, and then applying a solder resistor and surface treatment.

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