TWI494033B - Methods of forming coreless package structure and coreless package substrate - Google Patents

Description

Method for manufacturing coreless package structure and method for manufacturing coreless package substrate

The invention relates to a method for manufacturing a coreless package structure and a method for manufacturing a coreless package substrate, in particular to a method for manufacturing a coreless package structure and a method for manufacturing a coreless package substrate.

The conventional semiconductor package substrate uses a core layer of FR-4, and a copper foil is pressed on both surfaces thereof, and then a patterned circuit layer is formed through exposure and development, and the patterned circuit layer is formed on the patterned circuit layer. Pressing a dielectric layer thereon, and performing laser drilling on the dielectric layer to expose a portion of the patterned circuit layer; and then repeating the foregoing steps to form a plurality of circuit layers on the patterned circuit layer, Further coating a layer of green lacquer on the outermost circuit layer and forming a plurality of openings to expose the pads of the circuit layer to form a general build-up substrate; however, since it is manufactured by the foregoing method The substrate includes a core layer, so the thickness of the entire package substrate cannot be reduced.

Therefore, a coreless package substrate technology has been developed. As shown in the cross-sectional view of FIG. 1, another copper foil 11 is laminated on a core plate 10 containing a copper foil 101, and the copper foil 101 and copper foil are bonded. A vacuum is formed between the layers 11, and after the plurality of circuit layers 12 and the green lacquer 13 are formed on the copper foil 11, the core plate 10 is peeled off along the interface (arrow) between the core plate 10 and the copper foil 11 to be broken. Vacuum to complete a coreless package substrate.

However, the method for manufacturing the coreless package substrate described above is not easy to accurately align the interface between the core board 10 and the copper foil 11, and is also likely to cause peeling of the circuit layer 12 or delamination of the green paint 13, thereby causing reliability of subsequent products. Not good.

Therefore, how to avoid the various problems in the above-mentioned prior art, and solve the problem that it is difficult to accurately peel off the core board, in order to improve the reliability of the product, has become a problem that is currently being solved.

In view of the above-mentioned shortcomings of the prior art, the present invention provides a method for manufacturing a coreless package substrate, comprising: providing a carrier plate on which a metal layer is formed, a circuit layer is formed on the metal layer, and the carrier layer is The side surface protrudes from a side surface of the metal layer; and the carrier plate is removed along an interface between the carrier plate and the metal layer.

The invention provides a method for manufacturing a coreless package structure, comprising: providing a carrier plate on which a metal layer is formed, a circuit layer is formed on the metal layer, and a semiconductor wafer is disposed and packaged on the circuit layer, and The side surface of the carrier plate protrudes from a side surface of the metal layer; and the carrier plate is removed along an interface between the carrier plate and the metal layer.

The invention provides a method for manufacturing a coreless package substrate, comprising: providing a carrier board, the carrier board comprising a dielectric layer and a metal foil on a surface thereof, the metal foil is formed with a metal layer, the metal layer A wiring layer is formed thereon, and a side surface of the metal foil and a side surface of the metal layer are recessed on a side surface of the dielectric layer; and the carrier board is removed along an interface between the carrier board and the metal layer.

The invention further provides a method for manufacturing a coreless package structure, comprising: providing a carrier board, the carrier board comprising a dielectric layer and a metal foil on a surface thereof, the metal foil is formed with a metal layer, the metal Forming a circuit layer on the layer, and disposing and packaging the semiconductor wafer on the circuit layer, and recessing a side surface of the metal foil and a side surface of the metal layer on a side surface of the dielectric layer; and along the carrier plate and the metal The interface between the layers removes the carrier.

In the above method, the two surfaces of the carrier sheet have a metal foil, and the metal foil is made of copper. According to the method for manufacturing the coreless package substrate, the side surface of the carrier plate protrudes from the side surface of the metal layer by making the initial layout area of the metal layer smaller than the layout area of the carrier layer, or Removing a portion of the metal layer from the side etching, or removing a portion of the metal layer and the wiring layer on the periphery of the carrier plate; further, both surfaces of the carrier plate have a metal foil, and the metal layer is partially etched from the side A portion of the metal foil adjacent to the metal layer is removed from the side etching.

In the method of the present invention, the metal layer is removed, and the metal layer is made of copper.

In the manufacturing method, the carrier board is removed along the interface between the carrier board and the metal layer by a metal wire, a plastic wire, a roller or a wind knife; in addition, the circuit layer is double-connected. A semiconductor wafer is formed on the wiring layer with a packaging material covering the semiconductor wafer.

According to the method described above, the carrier layer comprises a dielectric layer and a metal foil, and the metal layer is formed on the metal foil, and the material of the dielectric layer is ABF (Ajinomoto Build-up Film), BCB. (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene), FR4, FR5, BT (Bismaleimide Triazine), aromatic Aramide, or mixed epoxy fiberglass.

As can be seen from the above, since the method for manufacturing the coreless package structure and the method for manufacturing the coreless package substrate of the present invention make the exposed end of the interface to be stripped non-flat, the interface can be easily found, which is advantageous for the subsequent stripping step. Furthermore, the manufacturing efficiency and reliability of the coreless package structure and the coreless package substrate are improved.

The other embodiments of the present invention will be readily understood by those skilled in the art from this disclosure.

It is to be understood that the structure, the proportions, the size, and the like of the present invention are intended to be used in conjunction with the disclosure of the specification, and are not intended to limit the invention. The conditions are limited, so it is not technically meaningful. Any modification of the structure, change of the proportional relationship or adjustment of the size should remain in this book without affecting the effects and the objectives that can be achieved by the present invention. The technical content disclosed in the invention can be covered. In the meantime, the terms "side", "upper" and "one" are used in this specification to describe the scope of the invention, and not to limit the scope of the invention, the relative relationship may be changed or Adjustments, where there is no material change, are considered to be within the scope of the invention.

First embodiment

Please refer to FIGS. 2A and 2B, which are respectively a cross-sectional view and a plan view of a first embodiment of the method for manufacturing a coreless package structure of the present invention.

As shown in FIGS. 2A and 2B, a carrier 20 is provided having a metal foil 201 on both surfaces thereof, and a metal layer 21 is formed on the metal foil 201. The metal layer 21 is vacuum-pressed in this embodiment. On the metal foil 201, the layout area of the metal layer 21 is smaller than the layout area of the carrier board 20, that is, the side surface of the carrier board 20 protrudes from the side surface of the metal layer 21 to form a step S. Then, a circuit layer 22 of the build-up layer is formed on the metal layer 21, and the circuit layer 22 can be formed by using the metal layer 21 as a plated conductive layer, which can be formed by first forming a dielectric layer on the metal layer 21. And exposing the metal layer 21 through the laser opening, forming a conductive seed layer on the dielectric layer, and forming a conductive layer on the opening of the dielectric layer and the partial dielectric layer via the conductive seed layer. Materials to form conductive lines. The circuit layer 22 of this embodiment may be a single layer structure, and the above-described fabrication method may be repeated to form a multilayer wiring structure. Alternatively, the circuit layer 22 may be fabricated by another circuit. The dielectric layer and a thin copper layer may be laminated on the metal layer 21 to expose the metal layer 21 via a laser opening. Then, an electroplating and patterning process is performed to form a conductive material on the opening of the dielectric layer and a portion of the dielectric layer to form a conductive line. After the circuit layer 22 is formed, a solder resist layer may be selectively disposed on the circuit layer 22 to complete the package substrate structure of the present invention. Then, using the package substrate structure, the semiconductor wafer 23 is connected to the circuit layer 22 and electrically connected to the circuit layer 22, and the electrical connection manner may be a wire bonding or flip chip method; The encapsulation material 24 of the semiconductor wafer 23. In the present embodiment, the encapsulating material 24 is flush with the side surface of the metal layer 21, and the metal layer 21 and the side surface of the encapsulating material 24 and the side surface of the carrying board 20 together form a step S.

Finally, the metal layer 21 can be further removed (this is not shown). The manner of removing the metal layer 21 may be etching in this embodiment, and removing a portion of the metal layer 21 via etching to form a patterned line, and selectively forming a protective layer on the patterned line. Solder layer.

In the manufacturing method of the embodiment, the metal foil 201 and the metal layer 21 are made of copper.

At this time, due to the existence of the step S, the interface between the carrier 20 and the metal layer 21 can be easily found, and the carrier 20 is peeled off via the jig, which is the metal wire 25 in this embodiment ( Or plastic wire) moves through the interface between the carrier plate 20 and the metal layer 21 to separate and remove the carrier plate 20, as shown in FIG. 2B. Under the same implementation concept, the fixture can also be a wind knife or a roller.

Second embodiment

Please refer to FIG. 3, which is a cross-sectional view showing a second embodiment of the method for manufacturing a coreless package structure of the present invention.

As shown in FIG. 3, this embodiment is substantially the same as the previous embodiment, and the main difference is that the carrier board 20 of the embodiment includes a dielectric layer 200 and metal foils 201 on both surfaces thereof. A metal layer 21 is formed on the metal foil 201. The metal layer 21 does not need to be smaller than the layout area of the carrier 20, but is etched away from the side portion of the metal layer 21 and a portion adjacent to the metal layer 21. The metal foil 201 is such that the side surface of the metal foil 201 and the side surface of the metal layer 21 are recessed on the side surface of the dielectric layer 200. In this embodiment, the metal layer 21 and the metal foil on the side of the package structure. A recess 26 is formed at 201, and then the interface between the carrier 20 and the metal layer 21 can be easily found, and the metal wire 25 (or plastic wire) is moved between the carrier 20 and the metal layer 21. Interface to separate and remove the carrier plate 20.

It should be noted that the metal foil 21 may not be removed, but only a portion of the metal layer 21 is etched away from the side, but it is not known to those of ordinary skill in the art to which the present invention pertains. Repeat them.

In the manufacturing method of the embodiment, the material of the metal foil 201 and the metal layer 21 is copper, and the material of the dielectric layer 200 is ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), and LCP (Liquid). Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), or mixed epoxy Glass fiber.

Third embodiment

Please refer to FIGS. 4A and 4B, which are cross-sectional views showing a third embodiment of the method for manufacturing a coreless package structure of the present invention.

As shown in FIG. 4A, a carrier board 40 is provided which includes a dielectric layer 401 and a metal foil 402 on both surfaces thereof. The metal foil 402 is formed with a metal layer 41 on which a wiring layer 42 is formed. The circuit layer 42 is connected with a semiconductor wafer 43 on which the encapsulation material 44 covering the semiconductor wafer 43 is formed, and then the periphery of the carrier plate 40 is removed by, for example, cutting with a cutter 45. The upper portion of the metal layer 41 and the wiring layer 42 are such that a portion of the metal foil 402 is exposed.

As shown in FIG. 4B, at this time, the side surface of the carrier plate 40 protrudes from the side surface of the metal layer 41 and the circuit layer 42 to form a step S, which is easy due to the existence of the step S. The interface between the carrier plate 40 and the metal layer 41 is found, and the metal wire 46 (or plastic wire) is moved through the interface between the carrier plate 40 and the metal layer 41 to separate and remove the carrier plate 40.

Finally, the metal layer 41 can be further removed (this is not shown).

In the manufacturing method of the embodiment, the metal foil 402 and the metal layer 41 are made of copper, and the dielectric layer 401 is made of ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), and LCP (Liquid). Crystal Polymer), PI (Poly-imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), or mixed epoxy Glass fiber.

It should be noted that in all of the foregoing embodiments, the peeling is performed by means of a wire or a wind knife in addition to the metal wire (or plastic wire) mentioned; in addition, in the present invention The stripping step may be performed to complete the coreless package substrate, except that the semiconductor wafer is formed and packaged after the package material is formed to complete the coreless package structure as in the embodiment, before the semiconductor wafer is formed and the package material is formed.

In summary, compared with the prior art, the method for manufacturing the coreless package structure of the present invention and the method for manufacturing the coreless package substrate make the exposed end of the interface to be stripped non-flat, so that the interface can be easily found. It is beneficial to the subsequent stripping step, thereby improving the manufacturing efficiency and reliability of the coreless package structure and the coreless package substrate.

The above embodiments are intended to illustrate the principles of the invention and its effects, and are not intended to limit the invention. Any of the above-described embodiments may be modified by those skilled in the art without departing from the spirit and scope of the invention. Therefore, the scope of protection of the present invention should be as set forth in the appended claims.

10. . . Core board

101,11. . . Copper foil

12,22,42. . . Circuit layer

13. . . Green paint

20,40. . . Carrier board

200,401. . . Dielectric layer

201,402. . . Metal foil

21,41. . . Metal layer

23,43. . . Semiconductor wafer

24,44. . . Packaging material

25,46. . . metal wires

26. . . Concave

45. . . Tool

S. . . ladder

1 is a cross-sectional view showing a conventional method for manufacturing a coreless package substrate;

2A and 2B are respectively a cross-sectional view and a plan view of a first embodiment of the method for manufacturing a coreless package structure of the present invention;

Figure 3 is a cross-sectional view showing a second embodiment of the method of manufacturing the coreless package structure of the present invention;

4A and 4B are cross-sectional views showing a third embodiment of the method of manufacturing the coreless package structure of the present invention.

20. . . Carrier board

201. . . Metal foil

twenty one. . . Metal layer

twenty two. . . Circuit layer

twenty three. . . Semiconductor wafer

twenty four. . . Packaging material

25. . . metal wires

S. . . ladder

Claims (16)

A method for manufacturing a coreless package structure includes: providing a carrier board on which a metal layer is formed, the metal layer contacting the carrier board, a circuit layer is formed on the metal layer, and a semiconductor wafer is disposed on the circuit layer And causing a side surface of the carrier plate to protrude from a side surface of the metal layer; and removing the carrier plate along an interface between the carrier plate and the metal layer. A method for manufacturing a coreless package substrate, comprising: providing a carrier plate on which a metal layer is formed, the metal layer contacting the carrier plate, the circuit layer is formed on the metal layer, and the side surface of the carrier plate is protruded from a side surface of the metal layer; and removing the carrier plate along an interface between the carrier plate and the metal layer. A method for manufacturing a coreless package structure includes: providing a carrier board, the carrier board comprising a dielectric layer and a metal foil on a surface thereof, the metal foil is formed with a metal layer, and the metal layer is formed with a line And arranging a semiconductor wafer on the wiring layer and encapsulating, and recessing a side surface of the metal foil and a side surface of the metal layer on a side surface of the dielectric layer; and between the carrier layer and the metal layer The interface removes the carrier board. A method for manufacturing a coreless package substrate, comprising: providing a carrier board, the carrier board comprising a dielectric layer and a metal foil on a surface thereof, the metal foil is formed with a metal layer, and the metal layer is formed with a line a layer, and recessing a side surface of the metal foil and a side surface of the metal layer on a side surface of the dielectric layer; The carrier plate is removed along the interface between the carrier plate and the metal layer. The method of claim 1 or 2, wherein the two surfaces of the carrier sheet have a metal foil. The method of claim 3, wherein the metal foil is made of copper. The method of claim 5, wherein the metal foil is made of copper. The method of claim 1 or 2, wherein the side surface of the carrier sheet protrudes from the side surface of the metal layer by: making the initial layout area of the metal layer smaller than the layout of the carrier layer area. The method of claim 1 or 2, wherein the side surface of the carrier sheet protrudes from the side surface of the metal layer by removing a portion of the metal layer and the line on the periphery of the carrier sheet. Floor. The method of claim 3, wherein the side surface of the metal foil and the side surface of the metal layer are recessed on the side surface of the dielectric layer by etching away a portion of the metal from the side. Foil and metal layer. The method of claim 1, wherein the metal layer is removed. The method of claim 1, 2, 3 or 4, wherein the metal layer is made of copper. The method of claim 1, 2, 3 or 4, wherein the manner of removing the carrier along the interface between the carrier and the metal layer It is made of metal wire, plastic wire, roller or air knife. The method of claim 1 or 2, wherein the carrier sheet comprises a laminated dielectric layer and a metal foil, and the metal layer is formed on the metal foil. The method of claim 3, wherein the material of the dielectric layer is ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly) -imide), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), or mixed epoxy fiberglass (Glass fiber) . The method of claim 14, wherein the material of the dielectric layer is ABF (Ajinomoto Build-up Film), BCB (Benzocyclo-buthene), LCP (Liquid Crystal Polymer), PI (Poly-imide). ), PPE (Poly (phenylene ether)), PTFE (Poly (tetra-fluoroethylene)), FR4, FR5, BT (Bismaleimide Triazine), aromatic nylon (Aramide), or mixed epoxy glass fiber (Glass fiber).