JP7336845B2 - Method for manufacturing printed wiring board - Google Patents

Description

The present disclosure relates to a method of manufacturing a printed wiring board.

There is a laminated board that enables high-density wiring with a high degree of freedom by using a plurality of conductor layers stacked with an insulating layer interposed therebetween. In a laminate, different conductor layers are electrically connected by using through conductors in holes such as through holes and via holes that penetrate insulating layers.

There is a technique for obtaining a printed wiring board in which a fine wiring pattern is formed on the thin conductor layer of this laminate by a modified semi-additive process (MSAP). On the other hand, in order to obtain reliable electrical connection, it is required to thicken the plated layer on the inner wall surface of the through-hole, which serves as a through conductor. In order to solve these problems, there is a technique of thinning the conductor layer and the plated layer by polishing or soft etching after plating the inner wall surface of the through hole and the conductor layer (Patent Documents 1 and 2).

JP-A-2002-16357 JP-A-2002-76613

However, when the conductor and the resin filled in the through-hole are polished, the resin is scraped more easily than the conductor, resulting in depressions. Accordingly, more of the conductor near the corner, which is the connecting portion between the through-hole and the conductor layer, is removed than the surrounding portion, ensuring electrical connection at the connecting portion between the conductor layer and the plating inside the through-hole. However, there is a problem that the quality is lowered.

An object of this disclosure is to provide a method of manufacturing a printed wiring board that can appropriately achieve both the thinness of the conductor layer and the reliability of electrical connection.

The contents of this disclosure for achieving the above purpose are:
A step of forming through-holes penetrating through the laminate having a plurality of conductor layers separated by insulating layers in the laminating direction of the insulating layers and the conductor layers;
forming a plating resist in a predetermined range in contact with the through-hole on the outer surface of the laminate in the lamination direction;
electroplating the outer surface and the inner wall surface of the through-hole;
a step of stripping the plating resist;
filling the interior of the through-hole with a resin so as to protrude into the predetermined range;
polishing and smoothing the outer surface;
thinning a portion of the conductor not covered with the resin on the outer surface;
polishing the resin protruding from the thinned conductor;
A method for manufacturing a printed wiring board comprising :

According to the contents of the present disclosure, there is an effect that it is possible to appropriately achieve both the thinness of the conductor layer in the printed wiring board and the reliability of electrical connection.

It is a figure which shows a part of cross section of the printed wiring board of embodiment. FIG. 4 is a cross-sectional view showing a manufacturing process of through holes in the core substrate; FIG. 4 is a cross-sectional view showing a manufacturing process of through holes in the core substrate; FIG. 4 is a cross-sectional view showing a manufacturing process of through holes in the core substrate; FIG. 4 is a cross-sectional view showing a method of manufacturing a printed wiring board including a laminate; FIG. 4 is a cross-sectional view showing a method of manufacturing a printed wiring board including a laminate; FIG. 4 is a cross-sectional view showing a method of manufacturing a printed wiring board including a laminate; 5 is a diagram showing a cross section of a printed wiring board of Modification 1; FIG. FIG. 11 is a diagram showing a cross section of a printed wiring board of modification 2;

Several embodiments of the present disclosure will be described below based on the drawings.
FIG. 1 is a diagram showing a part of a cross section of printed wiring board 100 of the embodiment.
In this printed wiring board 100, buildup layers 40 and 50 are positioned on both sides of a core substrate 10 having four wiring layers between flat insulating layers 11 and on both outer exposed surfaces (outer surfaces). . The insulating layer 11 is a resin substrate or the like. The internal wiring 12 located in the wiring layer between the insulating layers 11 is formed inside the core substrate 10 .

The insulating layer 11 is, for example, an insulating resin such as epoxy resin, bismaleimide-triazine resin, polyimide resin, polyphenylene ether (PPE) resin, phenol resin, polytetrafluoroethylene (PTFE) resin, silicone resin, and polybutadiene resin. , polyester resins, melamine resins, urea resins, polyphenylene sulfide (PPS) resins, polyphenylene oxide (PPO) resins, etc., or mixtures of two or more of these.

The core substrate 10 has a through-hole 20 penetrating the core substrate 10 (laminated plate 10a to be described later, see FIG. 2) in the stacking direction of the insulating layer 11 and the wiring layers (here, this direction is the vertical direction). . The inner wall surface of the through hole 20 is covered with a conductor layer 21 (conductor). The inside of the through hole 20 is filled with a resin 22 that is an insulating material. The conductor layer 21 includes an electroless plated layer 211 and an electrolytic plated layer 212 .

The core substrate 10 is partially covered with a conductor layer 13 and wiring conductors 14 on one side of the outer surface (upper surface) and the opposite side of the outer surface (lower surface) when viewed in the stacking direction. The conductor layer 13 is a seed layer, and copper foil is used here. Any other conductor metal or the like may be used as long as it reflects the laser beam in the laser processing described below.

In printed wiring board 100 of the present disclosure, the thickness of conductor layer 13 differs between the predetermined range in contact with through hole 20 and the other portion. That is, the conductor layer 13 is formed between the inside of the range A including the through hole 20 (here, within a circle with a predetermined radius centered on the center of the through hole 20 in a plan view) and the outside of the range A. A portion of the conductor layer 13 that has a step in between and does not overlap the through hole 20 in a plan view inside the range A (the above predetermined range) is thicker than the conductor layer 13 outside the range A (a portion other than the predetermined range). It's becoming The difference in thickness inside and outside the boundaries of area A (there may be some transition regions) should be at least 1 μm, eg 1-20 μm. Also, the range A is at least 10 μm or more, for example, 10 to 50 μm from the edge of the through hole 20 (resin 22). The thickness outside the range A (thin portion) is, for example, 1 to 10 μm. On the other hand, having the thickness difference described above maintains the electrical connection more reliably.

The conductor layer 13 within the area A has a cavity at the resin 22 portion of the through hole 20, and the edge of the cavity is outside the part where the conductor layer 21, here, the electroless plated layer 211, protrudes vertically from the insulating layer 11. in contact with the sides. That is, the height of this contact portion corresponds to the thickness of range A, and the electrical connection is reliably maintained at the upper and lower ends of through hole 20 .

The upper and lower ends of the through holes 20 are connected to the wiring conductors 14 respectively. The wiring conductors 14 are circuit wirings provided in the wiring layers on the upper and lower surfaces of the core substrate 10, and have appropriate wiring patterns so as to be electrically connected to the vias 42, 52 penetrating the buildup layers 40, 50 and the like. is overlaid on the conductor layer 13 by . The wiring conductor 14 is a pattern plated layer formed by pattern plating as described later.

A buildup layer 50 is positioned in contact with the upper surface side of core substrate 10 , and a buildup layer 40 is positioned in contact with the lower surface side of core substrate 10 . Although the number of stacks of the buildup layers 40 and 50 is not particularly limited, here, two sets of insulating layers and wiring layers overlap each other. Each of the two insulating layers 41 and 51 is an insulating resin. The insulating layers 41 and 51 are penetrated by vias 42 and 52, respectively. These vias 42 and 52 electrically connect upper and lower wirings of the insulating layers 41 and 51, respectively. The vias 42 and 52 are filled vias here, and conductors, here copper, are embedded in the pilot holes of the vias by electroplating.

A part of the wiring conductor including the via 42 in the insulating layer 41 of the lowest layer (furthest downward from the core substrate 10) in the buildup layer 40, here, the part immediately below the via 42, serves as a connection pad with the outside. and the exposed surface is covered with a plating layer 43 . Similarly, a portion of the wiring conductor including the via 52 in the uppermost insulating layer 51 in the buildup layer 50, here, the portion immediately above the via 52, serves as a connection pad with the outside, and the exposed surface is plated. It is covered by layer 53 . Portions other than the pads are covered and insulated with solder resists 60 and 70, respectively.

Next, a method for manufacturing printed wiring board 100 will be described. Here, the circuit wiring of the core substrate 10 and each buildup layer 40, 50 is formed by a modified semi-additive process (MSAP).
2 to 4 are cross-sectional views showing the manufacturing process of through holes in core substrate 10 of printed wiring board 100. First, as shown in FIG. This cross section is the same as the cross section shown in FIG.

A through hole 201 to be the through hole 20 is provided in the laminated plate 10a having the internal wiring 12 separated by the insulating layer 11 and the conductor layer 13 on the exposed surface (FIG. 2(a)). The through holes 201 are formed by, for example, drilling.

Electroless plating is applied to the conductor layer 13 and the inner wall surface of the through hole 20 to form an electroless plated layer 211 (FIG. 2(b)). This electroless plated layer 211 is thin enough to be easily removed by polishing (second polishing) described later, for example, about 1 μm.

A plating resist 31 is provided in a predetermined range surrounding the edge of the through hole 20 (in contact with the through hole 20) on the upper and lower surfaces of the laminate 10a (FIG. 2(c)). The plating resist 31 is, for example, a photosensitive dry film, which is exposed and developed so as to remain within the predetermined range (range A) after being entirely laminated on the upper and lower surfaces. Electrolytic plating is performed on the laminate 10a to form an electrolytic plating layer 212 on the conductive layer 13 and the electroless plating layer 211 on the inner wall surfaces of the through holes 201 (the range where the plating resist 31 is not formed) (FIG. 3). (a)). The electrolytic plated layer 212 is sufficiently thick (for example, 15 times or more) thicker than the electroless plated layer 211 . Also, the electroplating layer 212 has a thickness equal to or greater than that of the conductor layer 13, for example. As a result, electrical connection between different wiring layers using the through holes 20 can be reliably performed with low resistance.

The plating resist 31 is stripped and removed (FIG. 3(b)). As a result, around the through-hole 201, a portion recessed one step below the portion where the electrolytic plating layer 212 is formed is formed.

A resin 22 is filled inside the through-hole 201 to be the through-hole 20 (FIG. 3(c)). The resin 22 is filled so as to protrude slightly from the through-hole 201 and spread over a range including the recessed portion (range A) that is one step lower on the upper and lower surfaces. The upper and lower surfaces (outer surfaces) of the laminate 10a are polished to remove the protruding resin 22 together with a part of the electrolytic plating layer 212, thereby smoothing (FIG. 4(a)). For polishing, for example, buffing is used. As a result, the resin 22 remains in the interior of the through-hole 201 and the recessed portion around it where the plating resist 31 was provided.

Etching (soft etching) is performed to remove the conductors (electrolytic plated layer 212, electroless plated layer 212, electroless plated layer 211 and conductor layer 13) are thinned (FIG. 4(b)). The amount of etching is controlled by the etching time or the like, and is made sufficiently thinner than the original thickness of the conductor layer 13, so that it can be sufficiently removed in a short period of time without adversely affecting the wiring conductor 14 during flash etching, which will be described later. is defined as That is, the electrolytic plated layer 212 and the electroless plated layer 211 on the outer surface are all removed except for the portion covered with the resin 22 . As a result, the thickness of the conductor layer (the electroless plated layer 211 and the electrolytic plated layer 212) covering the inner wall surface of the through hole 20 is greater than the thickness of the conductor layer 13 in the portion other than the area A.

The upper and lower surfaces are polished again to remove the resin protruding from the thinned conductor. At this time, the thin electroless plated layer 211 is also removed, and the conductor layer 13 is also slightly scraped. However, the polishing is stopped so that the thickness of the conductor layer 13 that remains without being scraped is greater than the thickness of the thinned portion of the conductor layer 13 . That is, the conductor layer 13 is formed thicker in the vicinity of the through-hole 20 (area A) in a step-like manner with respect to the outside thereof. For the polishing, for example, buffing is used, like the polishing of the protruding resin 22 in FIG. 3(c).

In this polishing process, the resin 22 is actually polished more preferentially than the conductor surface, so that the inner range of the through-hole 20 tends to be recessed. Correspondingly, the electroless plated layer 211 and the conductor layer 13 in contact with the edge of the resin 22 also tend to be slightly thinner than their surroundings. However, as described above, since the polishing is finished in a state where the conductor layer 13 is thicker than the outside thereof in the area A, no discontinuity occurs in the connection between the conductor layers 21 and 13 .

5 to 7 are cross-sectional views showing a method of manufacturing printed wiring board 100 including laminate 10a in which through-holes 20 are formed by the manufacturing process described above. Various well-known techniques may be applied to subsequent processing.
A plating resist 32 is formed on the upper and lower surfaces of the laminate 10a (FIG. 5(a)). This plating resist 32 is, for example, a dry film like the plating resist 31 described above, and is exposed and developed using a mask corresponding to the wiring patterns provided on the upper and lower surfaces.

Electrolytic plating is applied to the upper and lower surfaces of the laminate 10a to form the wiring conductors 14 by plating in the wiring pattern portions not covered with the plating resist 32 (FIG. 5(b)). After forming the wiring conductor 14, the plating resist 32 is removed (FIG. 5(c)). The conductor layer 13 remaining between the wiring conductors 14 is removed by micro-thickness etching (flash etching) (FIG. 6A).

An insulating layer 51 is formed on the upper surface of the laminated plate 10a (that is, the core substrate 10) on which the wiring conductors 14 are formed, and an insulating layer 41 is formed on the lower surface of the core substrate 10. As shown in FIG. At this time, a seed layer is provided on the surface as needed. Also, pilot via holes 421 and 521 are formed through the insulating layers 41 and 51, respectively (FIG. 6(b)). The via pilot holes 421 and 521 are provided by laser processing, for example. As the laser, for example, a carbon dioxide laser is used.

Using a plating resist (not shown), pattern plating is performed by electrolytic plating on the upper and lower insulating layers 41 and 51 (seed layers) and inside the via pilot holes 421 and 521 to form wiring conductors including the vias 42 and 52 ( FIG. 6(c)). The formation of the plating resist, the pattern plating of the wiring conductor, the stripping of the plating resist, and the flash etching of the remaining seed layer are the same as those for forming the wiring conductor 14 and the like. A suitable plating solution or the like may be selected so that the inside is filled to form a filled via.

Here, formation of wiring conductors including insulating layers 41, 51 and vias 42, 52 is repeated twice in order to form buildup layers 40, 50 (FIG. 7A). Then, solder resists 60 and 70 are formed on the upper surface of the buildup layer 40 and the lower surface of the buildup layer 50, respectively, except for the exposed portions that serve as pads (FIG. 7(b)). Either a dry film type or a liquid type may be used as the solder resists 60 and 70 .

Surface treatment is performed on the exposed pad portion and the like. Here, the pads are coated with plating layers 43 and 53 such as nickel plating and gold plating, and the printed wiring board 100 shown in FIG. 1 is completed. The surface treatment may also include other purposes, such as the formation of a coating for rust prevention (such as an organic coating).

[Modification]
8 and 9 are cross-sectional views of a printed wiring board 100a of a modified example. The same components as those shown in FIG. 1 are denoted by the same reference numerals, and descriptions thereof are omitted as appropriate.
A printed wiring board 100a of Modification 1 shown in FIG. In this printed wiring board 100 a , the upper and lower surfaces of the direct core substrate 10 are covered with solder resists 60 and 70 . The wiring layer partially exposed between the solder resists 60 and 70 is surface-treated and covered with the plating layer 15 .

A printed wiring board 100b of Modification 2 shown in FIG. The inner wall surface of the through hole 20b is covered with an electroless plated layer 211 and an electrolytic plated layer 212 in that order. A resin 22 is filled inside the through hole 20b.

A conductor layer 54 (seed layer) provided on the upper surface of the uppermost insulating layer 51 is thicker than the outside thereof in a predetermined range near the through hole 20b, like the conductor layer 13 described above. As a result, a step occurs at the boundary of the range. A wiring conductor 52 b is positioned in contact with the upper surface of the conductor layer 54 . Furthermore, the plating layer 53 is positioned in contact with the exposed portion of the wiring conductor 52b.

Also, the conductor layer 44 provided on the lower surface of the lowermost insulating layer 41 is thicker than the outer side in a predetermined range near the through hole 20b. As a result, a step occurs at the boundary of the range. A wiring conductor 42 b is positioned in contact with the lower surface of the conductor layer 44 . Furthermore, a plating layer 43 is positioned in contact with the exposed portion of the wiring conductor 42b.

Here, on the boundary between the via 52 provided in the uppermost insulating layer 51 and the upper surface of the insulating layer 51 and the boundary between the via 42 provided in the lowermost insulating layer 41 and the lower surface of the insulating layer 41, Although conductor layers 54 and 44 are shown, respectively, as described above, in order to provide the build-up layers 40 and 50 with insulating layers and wiring conductors, conductor layers (54, 44) may be provided between them whether or not they are shown. seed layer) is formed.

In the modification shown in FIG. 9, the wiring conductor 14 and the conductor layer 13 provided in the wiring layer on the outer surface of the core substrate 10 do not change in thickness around the through hole 20b. Here, a through hole 20b is provided later through the wiring conductor 14 and the conductor layer 13 provided by a conventionally known technique, and the electroless plating layer 211 formed on the inner wall surface is applied to the wiring conductor 14 and the conductor layer 13. are electrically connected to each other. Since no polishing is performed in the vicinity of the contact area between the wiring conductor 14 and the electroless plated layer 211, there is no problem of electrical connectivity at the contact portion inside the printed wiring board 100b.

As described above, the printed wiring boards 100 , 100 a , 100 b of the present embodiment include the laminate 10 a having the conductor layers 13 and the layers of the internal wiring 12 separated by the insulating layers 11 . The laminated plate 10a has a through hole 20 which passes through the laminated plate 10a in the lamination direction of the insulating layer 11, the internal wiring 12 and the conductor layer 13, the inner wall surface of which is covered with the conductor layer 21, and the inside of which is filled with the resin 22. The thickness of the conductor layer 13 positioned on the outer surface of the laminated plate 10a in the stacking direction is thicker than the portion outside the predetermined range within the range (predetermined range) that does not overlap the through hole within the range A that contacts the through hole 20 .
As a result, when the laminated plate 10a is polished, the resin 22 is more easily removed, so that the conductor layer 13 in the area in contact with the resin 22 is scraped more than it should be. prevent bad electrical connections. On the other hand, since a sufficiently thin conductor layer 13 can be obtained as a whole, a circuit can be easily obtained by pattern plating with fine wiring. As described above, in the printed wiring board 100 of the present embodiment, both the thin conductor layer 13 and the reliability of electrical connection can be achieved, and high-density wiring can be obtained more reliably.

Moreover, the thickness of the conductor layer 13 in the area A is larger than the thickness of the conductor layer 13 in the portion other than the area A by 1 μm or more. By locally determining a sufficient thickness within a necessary range in this way, it is possible to achieve both the reliability of electrical connection and the thin conductor layer 13 .

Also, the thickness of the conductor layer 21 covering the inner wall surface of the through hole 20 is thicker than the thickness of the conductor layer 13 in the portion other than the area A. As shown in FIG. Thereby, electrical connection between different wiring layers using the through holes 20 can be obtained more reliably.

Moreover, it has a wiring pattern in which a wiring conductor 14 formed by pattern plating is superimposed on the conductor layer 13 on at least one side of the outer surface of the laminate 10a. That is, by processing the conductor layer 13 in the laminate 10a, it is possible to obtain the printed wiring board 100 stably provided with a fine wiring pattern using pattern plating.

Moreover, the conductor layer 13 is a copper foil. As a result, the dense conductor layer 13 with an appropriate thickness can be used as a seed layer.

Printed wiring boards 100 and 100b also include buildup layers 40 and 50 in contact with at least one side of the outer surface of laminate 10a. By improving the reliability of electrical connection as described above, the yield of printed wiring boards 100 and 100b having such multilayer wiring can be improved.

In addition, the method for manufacturing the printed wiring board 100 of the present embodiment includes a laminated board 10a having a plurality of internal wirings 12 and conductor layers 13 separated by an insulating layer 11, and the laminated board 10a having the insulating layer 11 and the internal wirings 12. and a step of forming a through-hole 20 penetrating the conductor layer 13 in the stacking direction, a step of forming a plating resist 31 in a range A in contact with the through-hole 20 on the outer surface of the laminate 10a in the stacking direction, the outer surface and the through-hole 20 A step of electroplating the inner wall surface to obtain a conductor layer 21, a step of peeling off the plating resist 31, a step of filling the inside of the through hole 20 with a resin 22 so as to protrude into the area A, and polishing the outer surface to make it smooth. A step of thinning the conductor (the conductor layer 13, the electroless plated layer 211 and the electrolytic plated layer 212) of the portion not covered with the resin 22 on the outer surface, and polishing the resin 22 protruding from the thinned conductor. and the step of
In this way, by making it possible to form the conductor layer 13 relatively thick only at the connection portion of the conductor layers 13 and 21, it is possible to avoid loss of electrical connection due to excessive removal of the connection portion during polishing. Also, most of the conductor layers 13 can be kept thin, while the conductor layers 21 within the through-holes 20 can be kept sufficiently thick. Therefore, it is possible to obtain printed wiring board 100 in which stable electrical connection can be maintained and fine wiring patterns can be easily formed by pattern plating.

Further, the method of manufacturing printed wiring board 100 includes a step of forming buildup layers 40 and 50 on the polished outer surface of protruding resin 22 . Printed wiring boards 100 and 100b having multi-layered wiring layers including buildup layers 40 and 50 are produced by manufacturing printed wiring board 100 by the process capable of improving the reliability of electrical connection as described above. yield can be improved.

In addition, the embodiment according to the present disclosure is not limited to the above content, and various modifications are possible.
For example, the range in which the conductor layer 13 is thickened does not have to be defined concentrically around the center of the through hole 20 . For example, an appropriate shape such as a polygon or a polygon with rounded corners may be used depending on the arrangement of the plurality of through holes 20 and the number of wires between them.

Further, in the above embodiment, the thickness of the conductor layer 21 covering the inner wall surfaces of the through holes 20 may be adjusted as appropriate.

Further, in the above-described embodiment, the through holes provided in the core substrate 10 and the through holes penetrating through the core substrate 10 and the buildup layers 40 and 50 as a whole have been described as an example, but the present invention is not limited to this. In through holes similar to the through holes provided in part or all of the buildup layer, the thickness of the conductor layer can be locally increased at the portions in contact with the ends of the through holes based on the above process. . The same applies to the through-holes of any layer substrates that do not have the core substrate 10 .

Further, in the above embodiment, all wirings are formed by MSAP, but some of them may be formed by subtractive method.
In addition, specific details such as the structure, content and procedure of the manufacturing method shown in the above embodiment can be changed as appropriate without departing from the gist of the present disclosure.

10 Core substrate 10a Laminated plate 11 Insulating layer 12 Internal wiring 13 Conductor layer 14 Wiring conductor 15 Plating layers 20, 20b Through hole 21 Conductor layer 22 Resin 31, 32 Plating resist 40, 50 Build-up layers 41, 51 Insulating layers 42, 52 Vias 42b, 52b Wiring conductors 43, 53 Plated layers 44, 54 Conductor layers 60, 70 Solder resists 100, 100a, 100b Printed wiring board 201 Through holes 211 Electroless plated layers 212 Electroplated layers 421, 521 Pilot holes for vias

Claims (2)

A step of forming through-holes penetrating through the laminate having a plurality of conductor layers separated by insulating layers in the laminating direction of the insulating layers and the conductor layers;
forming a plating resist in a predetermined range in contact with the through-hole on the outer surface of the laminate in the lamination direction;
electroplating the outer surface and the inner wall surface of the through-hole;
a step of stripping the plating resist;
filling the interior of the through-hole with a resin so as to protrude into the predetermined range;
polishing and smoothing the outer surface;
thinning a portion of the conductor not covered with the resin on the outer surface;
polishing the resin protruding from the thinned conductor;
A method of manufacturing a printed wiring board comprising: 2. The method of manufacturing a printed wiring board according to claim 1 , further comprising the step of forming a build-up layer on the polished outer surface of the protruding resin.

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