WO2013088520A1 - 半導体装置の製造方法、及び、半導体装置 - Google Patents

半導体装置の製造方法、及び、半導体装置 Download PDF

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WO2013088520A1
WO2013088520A1 PCT/JP2011/078828 JP2011078828W WO2013088520A1 WO 2013088520 A1 WO2013088520 A1 WO 2013088520A1 JP 2011078828 W JP2011078828 W JP 2011078828W WO 2013088520 A1 WO2013088520 A1 WO 2013088520A1
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Prior art keywords
silicon layer
insulating film
type diffusion
sidewall
gate
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PCT/JP2011/078828
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English (en)
French (fr)
Japanese (ja)
Inventor
舛岡　富士雄
広記 中村
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ユニサンティス エレクトロニクス シンガポール プライベート リミテッド
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Priority to KR1020137015260A priority Critical patent/KR20130093149A/ko
Priority to PCT/JP2011/078828 priority patent/WO2013088520A1/ja
Priority to JP2013527212A priority patent/JP5643900B2/ja
Priority to CN2011800599173A priority patent/CN103262234A/zh
Priority to TW101144278A priority patent/TW201324627A/zh
Publication of WO2013088520A1 publication Critical patent/WO2013088520A1/ja

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/823487—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823885—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of vertical transistor structures, i.e. with channel vertical to the substrate surface
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors

Definitions

  • the present invention relates to a semiconductor device manufacturing method and a semiconductor device.
  • SGT Surrounding Gate Transistor
  • depletion can be suppressed and resistance of the gate electrode can be reduced by using metal instead of polysilicon for the gate electrode.
  • the post-process after forming the metal gate must always be a manufacturing process that takes into account metal contamination by the metal gate.
  • a silicon pillar having a nitride hard mask formed in a columnar shape is formed, a diffusion layer under the silicon pillar is formed, a gate material is deposited, and then the gate material is planarized and etched.
  • the insulating film sidewall is formed on the sidewalls of the silicon pillar and the nitride film hard mask.
  • a resist pattern for gate wiring is formed, the gate material is etched, the nitride film hard mask is removed, and a diffusion layer is formed on the silicon pillar (see, for example, Patent Document 4).
  • CMOS Complementary Metal Oxide Semiconductor
  • NMOS Negative Channel Metal Oxide Semiconductor
  • PMOS Platinum Channel Metal Oxide Semiconductor
  • a diffusion layer is formed on the upper and lower parts of the silicon pillar, and a gate material is deposited. Thereafter, the gate material is flattened and etched back to form an insulating film sidewall on the side wall of the silicon pillar, and then the gate material is etched to form a floating gate, and then the insulating film sidewall is removed (for example, see Patent Document 5).
  • JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2009-182317 A JP 2006-310651 A
  • an object of the present invention is to provide a method for manufacturing a semiconductor device (SGT) in which the number of steps is small and the upper part of the silicon pillar is protected during etching of the gate, and a semiconductor device (SGT structure).
  • SGT semiconductor device
  • a method for manufacturing a semiconductor device includes: Forming a planar silicon layer on a silicon substrate, and forming a first columnar silicon layer and a second columnar silicon layer on the planar silicon layer; After the first step, a gate insulating film is formed around the first and second columnar silicon layers, a metal film and polysilicon are deposited around the gate insulating film and planarized, Etching is performed to expose the upper portions of the first and second columnar silicon layers, and a first insulating film sidewall is formed on the upper sidewall of the first columnar silicon layer.
  • a second insulating film side wall on the upper side wall of the silicon layer Forming a first gate electrode and a second gate electrode having a laminated structure of a metal film and polysilicon around the gate insulating film; A second step of forming a gate wiring connected to the first gate electrode and the second gate electrode; After the second step, a first n-type diffusion layer is formed on the first columnar silicon layer, and a second n-type diffusion layer is formed on the lower portion of the first columnar silicon layer and the upper portion of the planar silicon layer.
  • n-type diffusion layer is formed, a first p-type diffusion layer is formed on the second columnar silicon layer, and a second layer is formed on the lower portion of the second columnar silicon layer and the upper portion of the planar silicon layer.
  • a third step of forming a p-type diffusion layer After the third step, a third insulating film sidewall is formed on the first and second insulating film sidewalls, the first and second gate electrodes, and the side walls of the gate wiring. 4 steps, After the fourth step, a fifth step of forming silicide on the first and second n-type diffusion layers, the first and second p-type diffusion layers, and the gate wiring. And having It is characterized by that.
  • a first resist for forming the first and second columnar silicon layers is formed on the silicon substrate, the silicon substrate is etched, and the first and second columnar silicon layers are formed. And removing the first resist, forming a second resist for forming the planar silicon layer, etching the silicon substrate, forming the planar silicon layer, and forming the second resist. Remove, It is preferable.
  • the gate insulating film is formed around the first and second columnar silicon layers, Forming a metal film around the gate insulating film; depositing and planarizing polysilicon; etching the polysilicon; exposing the metal film; etching the polysilicon; and Exposing the top of the columnar silicon layer, Etching the metal film, depositing a second oxide film and a first nitride film, and etching the first nitride film into a sidewall shape to form a nitride film sidewall; The second oxide film and the nitride film sidewall serve as the first and second insulating film sidewalls,
  • a third resist is formed so as to cover upper portions of the first and second columnar
  • a fourth resist for forming the first n-type diffusion layer and the second n-type diffusion layer is formed, arsenic is implanted, and the first and second n-type diffusion layers are formed.
  • a heat treatment is performed, The third oxide film is removed, the second oxide film and the gate insulating film are etched, and the second oxide film is etched to surround the first and second columnar silicon layers.
  • the oxide film sidewall and the nitride film sidewall serve as the first insulating film sidewall, and the oxide film sidewall and the nitride film sidewall serve as the second insulating film sidewall, Forming a fifth resist for forming the first p-type diffusion layer and the second p-type diffusion layer; implanting boron; forming the first and second p-type diffusion layers; Removing the fifth resist, depositing, and performing a heat treatment; It is preferable.
  • a second nitride film is further deposited, and the second nitride film is etched into a sidewall shape to form a nitride film sidewall serving as a third insulating film sidewall. It is preferable.
  • a semiconductor device is A planar silicon layer formed on a silicon substrate; First and second columnar silicon layers formed on the planar silicon layer; A first gate insulating film formed around the first columnar silicon layer; A first gate electrode having a laminated structure of a metal film and polysilicon formed around the first gate insulating film; A second gate insulating film formed around the second columnar silicon layer; A second gate electrode having a laminated structure of a metal film and polysilicon formed around the second gate insulating film; A gate wiring connected to the first and second gate electrodes; A first n-type diffusion layer formed on top of the first columnar silicon layer; A second n-type diffusion layer formed in a lower portion of the first columnar silicon layer and an upper portion of the planar silicon layer; A first p-type diffusion layer formed on top of the second columnar silicon layer; A second p-type diffusion layer formed in a lower portion of the second columnar silicon layer and an upper portion of the planar silicon layer; A first insulating film sidewall formed on
  • a method for manufacturing a semiconductor device (SGT) and a semiconductor device (SGT structure) in which the number of steps is small and the upper part of the silicon pillar is protected during gate etching.
  • the silicon pillar lower diffusion layer and the upper diffusion layer are formed simultaneously, the number of steps can be reduced.
  • a third resist is formed so as to cover the upper part of the first columnar silicon layer and the upper part of the second columnar silicon layer. Since the upper portions of the first and second columnar silicon layers are covered with the third resist, the gate insulating film is etched during the etching and the columnar silicon layer is prevented from being etched.
  • the first gate electrode has an upper portion covered with the first insulating film sidewall and a side wall covered with the third insulating film sidewall.
  • the side wall of the first insulating film side wall is covered with the third insulating film side wall. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is displaced to the first gate electrode side, the first gate electrode and the contact can be prevented from being short-circuited.
  • the second gate electrode is covered with the second insulating film side wall at the top and the side wall is covered with the third insulating film side wall.
  • the side wall of the second insulating film sidewall is covered with the third insulating film sidewall. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is formed in the vicinity of the second gate electrode, when the contact is displaced to the second gate electrode side, The contact is prevented from being short-circuited.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG. FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG. (A) is a top view which shows the manufacturing method of the semiconductor device which concerns on this embodiment.
  • FIG. 4B is a sectional view taken along line X-X ′ in FIG.
  • FIG. 6C is a sectional view taken along line Y-Y ′ in FIG.
  • first resists 102 and 103 for forming a first columnar silicon layer 105 and a second columnar silicon layer 104 are formed on a silicon substrate 101.
  • the silicon substrate 101 is etched to form a first columnar silicon layer 105 and a second columnar silicon layer 104.
  • the first resists 102 and 103 are removed.
  • a second resist 106 for forming the planar silicon layer 107 is formed.
  • the silicon substrate 101 is etched to form a planar silicon layer 107.
  • the second resist 106 is removed.
  • the first oxide film 108 is deposited and the surface thereof is flattened.
  • the first oxide film 108 is etched and left around the planar silicon layer 107.
  • a gate insulating film 109 is formed around the first columnar silicon layer 105 and the second columnar silicon layer 104, and around the gate insulating film 109.
  • the metal film 110 and the polysilicon 111 are deposited and the surface thereof is planarized and etched to expose the first columnar silicon layer 105 and the upper portion of the second columnar silicon layer 104.
  • a first insulating film sidewall 201 is formed on the upper sidewall of the first columnar silicon layer 105
  • a second insulating film sidewall 200 is formed on the upper sidewall of the second columnar silicon layer 104, and gate insulation is performed.
  • a first gate electrode 117b and a second gate electrode 117a having a laminated structure of a metal film 110 and polysilicon 111 are formed around the film. Then, a second step of forming the gate wiring 117c connected to the first gate electrode 117b and the second gate electrode 117a is shown.
  • a gate insulating film 109 is formed around the first columnar silicon layer 105 and the second columnar silicon layer 104.
  • a material of the gate insulating film 109 here, an oxide film, a laminated structure of an oxide film and a nitride film, a nitride film, or a high dielectric film can be used.
  • a metal film 110 is formed around the gate insulating film 109.
  • a metal material that can be used for a gate electrode such as titanium, titanium nitride, tantalum, or tantalum nitride can be used for the metal film 110.
  • polysilicon 111 is deposited and the surface thereof is flattened.
  • the polysilicon 111 is etched.
  • the polysilicon 111 is etched to expose the metal film 110.
  • the polysilicon 111 is etched to expose the upper portions of the first columnar silicon layer 105 and the second columnar silicon layer.
  • the metal film 110 is etched.
  • wet etching it is preferable to use wet etching.
  • a second oxide film 112 and a first nitride film 113 are deposited.
  • the first nitride film 113 is etched to remain on the side walls of the two columnar bodies to form nitride film side walls 114 and 115.
  • the first insulating film sidewall 201 is formed from the first oxide film 112 and the nitride film sidewall 115.
  • a second insulating film sidewall 200 is formed from the first oxide film 112 and the nitride film sidewall 114.
  • the upper part of the first columnar silicon layer 105 and the second gate electrode 117c are formed.
  • a third resist 116 is formed so as to cover the upper part of the columnar silicon layer 104.
  • the second oxide film 112 is etched.
  • the polysilicon 111 is etched, the metal film 110 is etched, and a first gate electrode 117b, a second gate electrode 117a, and a gate wiring 117c are formed.
  • the third resist 116 is removed.
  • wet etching is performed to remove the residue of the metal film 110. This treatment can be omitted when there is no residue of the metal film 110.
  • the gate insulating film 109 is formed around the second step, that is, the first columnar silicon layer 105 and the second columnar silicon layer 104, and the metal film 110 and the polysilicon 111 are formed around the gate insulating film 109. And the surface of the first columnar silicon layer 105 and the second columnar silicon layer 104 are exposed by performing etching. Then, the first insulating film sidewall 201 is formed on the upper sidewall of the first columnar silicon layer 105, and the second insulating film sidewall 200 is formed on the upper sidewall of the second columnar silicon layer 104.
  • a first gate electrode 117 b and a second gate electrode 117 a having a stacked structure of the metal film 110 and the polysilicon 111 are formed around the gate insulating film 109. Thereafter, a second step of forming the gate wiring 117c connected to the first gate electrode 117b and the second gate electrode 117a was shown.
  • a third step that is, a first n-type diffusion layer 119 is formed on the first columnar silicon layer 105, and a lower portion of the first columnar silicon layer 105 and an upper portion of the planar silicon layer 107 are formed. Then, the second n-type diffusion layer 120 is formed. Then, a first p-type diffusion layer 125 is formed on the second columnar silicon layer 104, and a second p-type diffusion layer is formed on the lower portion of the second columnar silicon layer 104 and the upper portion of the planar silicon layer 107. A third step of forming 126 is shown.
  • a fourth resist 118 for forming the first n-type diffusion layer 119 and the second n-type diffusion layer 120 is formed.
  • arsenic is implanted to form a first n-type diffusion layer 119 and a second n-type diffusion layer 120.
  • phosphorus can be implanted instead of arsenic.
  • the fourth resist 118 is removed, and a third oxide film 121 is deposited.
  • heat treatment is performed.
  • the third oxide film 121 is removed, and the second oxide film 112 and the gate insulating film 109 are etched.
  • the second oxide film 112 is etched and remains around the first columnar silicon layer 105 to form the oxide film sidewall 123, and also remains around the second columnar silicon layer 104, and the oxide film sidewall 122. It becomes. Therefore, the oxide film side wall 123 and the nitride film side wall 115 become the first insulating film side wall 201, and the oxide film side wall 122 and the nitride film side wall 114 become the second insulating film side wall 200. .
  • a fifth resist 124 for forming the first p-type diffusion layer 125 and the second p-type diffusion layer 126 is formed.
  • boron is implanted to form the first p-type diffusion layer 125 and the second p-type diffusion layer 126.
  • the fifth resist 124 is removed.
  • a second nitride film 127 is deposited.
  • heat treatment is performed.
  • the first n-type diffusion layer 119 is formed on the upper portion of the first columnar silicon layer 105, and the lower portion of the first columnar silicon layer 105 and the upper portion of the planar silicon layer 107 are formed.
  • a second n-type diffusion layer 120 is formed.
  • a first p-type diffusion layer 125 is formed above the second columnar silicon layer 104, and a second p-type diffusion layer 126 is formed below the second columnar silicon layer 104 and above the planar silicon layer 107.
  • a third step of forming was shown.
  • the present invention is not limited to this.
  • a sidewall is formed on the sidewall of the columnar silicon layer, and then the first n-type diffusion layer and the second n-type diffusion layer are formed.
  • a first p-type diffusion layer and a second p-type diffusion layer may be formed, and then a gate electrode may be formed.
  • a third insulating film sidewall 201, a second insulating film sidewall 202, a first gate electrode 117b, a second gate electrode 117a, and a gate wiring 117c are formed on the sidewalls of the third insulating film sidewall 201, the second insulating film sidewall 202, The 4th process of forming the insulating film side wall 202 is shown.
  • the second nitride film 127 is etched and left in a sidewall shape to form nitride film sidewalls 128, 129, and 130.
  • the nitride film sidewall 128 becomes the third insulating film sidewall 202.
  • the upper part of the first gate electrode 117b is covered with the first insulating film sidewall 201, and the side wall is covered with the third insulating film sidewall 202. Further, the side wall of the first insulating film sidewall 201 is covered with the third insulating film sidewall 202. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is displaced to the first gate electrode side, the first gate electrode and the contact are prevented from being short-circuited.
  • the upper part of the second gate electrode 117 a is covered with the second insulating film sidewall 200 and the side wall is covered with the third insulating film sidewall 202. Further, the side wall of the second insulating film side wall 200 is covered with the third insulating film side wall 202. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is formed in the vicinity of the second gate electrode 117a, when the contact is displaced to the second gate electrode side, the second A short circuit between the gate electrode and the contact is prevented.
  • the third insulating film sidewall 201, the second insulating film sidewall 202, the first gate electrode 117b, the second gate electrode 117a, and the side wall of the gate wiring 117c are third insulating.
  • a fourth step of forming the film sidewall 202 has been shown.
  • a metal such as nickel or cobalt is deposited and heat treatment is performed to remove unreacted metal.
  • a metal such as nickel or cobalt is deposited and heat treatment is performed to remove unreacted metal.
  • silicides 133, 134, 135, 136, 132, 131, and 137 are formed.
  • the second n-type diffusion layer 120 and the second p-type diffusion layer 126 are connected by the silicides 134 and 135.
  • the output terminal of the inverter is not formed under the silicon pillar, it is possible to omit connecting the second n-type diffusion layer 120 and the second p-type diffusion layer 126 with silicide.
  • a fifth step of forming silicide on 117c is shown.
  • a third nitride film 138 is deposited, an interlayer insulating film 139 is further deposited, and the surface thereof is flattened.
  • a sixth resist 140 for forming contacts on the first columnar silicon layer 105 and the second columnar silicon layer 104 is formed.
  • the interlayer insulating film 139 is etched to form contact holes 141 and 142.
  • the sixth resist 140 is removed.
  • a seventh resist 143 for forming a contact is formed on the gate wiring 117c and the planar silicon layer 107.
  • the interlayer insulating film 139 is etched to form contact holes 144 and 145.
  • the seventh resist 143 is removed.
  • the third nitride film 138 is etched.
  • metal is deposited to form contacts 146, 147, 148, and 149.
  • a metal 150 for metal wiring is deposited.
  • eighth resists 151, 152, 153, 154 are formed in order to form metal wiring.
  • the metal 150 is etched to form metal wirings 155, 156, 157, 158.
  • the eighth resists 151, 152, 153, 154 are removed.
  • the manufacturing method of SGT in which the number of steps is small and the upper part of the silicon pillar is protected during the etching of the gate is shown.
  • FIG. A structure of a semiconductor device obtained by the manufacturing method is shown in FIG. As shown in FIG. A planar silicon layer 107 formed on the silicon substrate 101; A first columnar silicon layer 105 formed on the planar silicon layer 107; A second columnar silicon layer 104 formed on the planar silicon layer 107; A gate insulating film 109 formed around the first columnar silicon layer 105; A first gate electrode 117b having a laminated structure of a metal film 110 and polysilicon 111 formed around the gate insulating film 109; A gate insulating film 109 formed around the second columnar silicon layer 104; A second gate electrode 117a having a laminated structure of a metal film 110 and polysilicon 111 formed around the gate insulating film 109; A gate wiring 117c connected to the first gate electrode 117b and the second gate electrode 117a; A first n-type diffusion layer 119 formed on the first columnar silicon layer 105; A second n-type diffusion layer 120 formed below the first columnar silicon layer 105 and above the planar silicon
  • a membrane sidewall 202 Formed on the first n-type diffusion layer 119, the second n-type diffusion layer 120, the first p-type diffusion layer 125, the second p-type diffusion layer 126, and the gate wiring 117c. Silicided 133, 134, 135, 136, 132, 131, 137, Have
  • the upper portion of the first gate electrode 117 b is covered with the first insulating film sidewall 201 and the side wall is covered with the third insulating film sidewall 202. Further, the side wall of the first insulating film sidewall 201 is covered with the third insulating film sidewall 202. Therefore, when the contact 140 formed on the diffusion layer above the planar silicon layer is displaced to the first gate electrode 117b side, the first gate electrode 117b and the contact 140 are prevented from being short-circuited. . Similarly, the second gate electrode 117 a is covered with the second insulating film sidewall 200 at the top and with the third insulating film sidewall 202 at the sidewall.
  • the side wall of the second insulating film side wall 200 is covered with the third insulating film side wall 202. Therefore, when the contact formed on the diffusion layer above the planar silicon layer is formed in the vicinity of the second gate electrode 117a, when the contact is displaced to the second gate electrode 117a side, the second It is possible to prevent a short circuit between the gate electrode 117a and the contact.
  • Second nitride film 128. Nitride film sidewall 129. Nitride film sidewall 130. Nitride film sidewall 131.
  • Silicide 132. Silicide 133.
  • Silicide 134. Silicide 135.
  • Silicide 136. Silicide 137.
  • Silicide 138. Third nitride film 139. Interlayer insulating film 140. Sixth resist 141. Contact hole 142. Contact hole 143. Seventh resist 144. Contact hole 145. Contact hole 146. Contact 147. Contact 148. Contact 149. Contact 150. Metal 151. Eighth resist 152. Eighth resist 153. Eighth resist 154. Eighth resist 155. Metal wiring 156. Metal wiring 157. Metal wiring 158. Metal wiring 200. Second insulating film sidewall 201. First insulating film sidewall 202. Third insulating film sidewall

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PCT/JP2011/078828 2011-12-13 2011-12-13 半導体装置の製造方法、及び、半導体装置 WO2013088520A1 (ja)

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WO2009096468A1 (ja) * 2008-01-29 2009-08-06 Unisantis Electronics (Japan) Ltd. 半導体記憶装置およびメモリ混載半導体装置、並びにそれらの製造方法
JP2010251678A (ja) * 2009-04-20 2010-11-04 Unisantis Electronics Japan Ltd 半導体装置の製造方法

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JP4987926B2 (ja) * 2009-09-16 2012-08-01 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置
JP5031809B2 (ja) * 2009-11-13 2012-09-26 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド 半導体装置
JP2011216657A (ja) * 2010-03-31 2011-10-27 Unisantis Electronics Japan Ltd 半導体装置

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JP2010251678A (ja) * 2009-04-20 2010-11-04 Unisantis Electronics Japan Ltd 半導体装置の製造方法

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JP5639317B1 (ja) * 2013-11-06 2014-12-10 ユニサンティス エレクトロニクス シンガポール プライベート リミテッドＵｎｉｓａｎｔｉｓ Ｅｌｅｃｔｒｏｎｉｃｓ Ｓｉｎｇａｐｏｒｅ Ｐｔｅ Ｌｔｄ． Ｓｇｔを有する半導体装置と、その製造方法
WO2015068226A1 (ja) * 2013-11-06 2015-05-14 ユニサンティス エレクトロニクス シンガポール プライベート リミテッド Ｓｇｔを有する半導体装置と、その製造方法
US9613827B2 (en) 2013-11-06 2017-04-04 Unisantis Electronics Singapore Pte. Ltd. SGT-including semiconductor device and method for manufacturing the same
US10312110B2 (en) 2013-11-06 2019-06-04 Unisantis Electronics Singapore Pte. Ltd. Method for manufacturing an SGT-including semiconductor device

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