WO2013171908A1 - 半導体装置の製造方法及び半導体装置 - Google Patents
半導体装置の製造方法及び半導体装置 Download PDFInfo
- Publication number
- WO2013171908A1 WO2013171908A1 PCT/JP2012/062857 JP2012062857W WO2013171908A1 WO 2013171908 A1 WO2013171908 A1 WO 2013171908A1 JP 2012062857 W JP2012062857 W JP 2012062857W WO 2013171908 A1 WO2013171908 A1 WO 2013171908A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- silicon layer
- fin
- polysilicon gate
- polysilicon
- insulating film
- Prior art date
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 76
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 73
- 239000010410 layer Substances 0.000 claims abstract description 267
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 210
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 210
- 239000010703 silicon Substances 0.000 claims abstract description 210
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims abstract description 175
- 229920005591 polysilicon Polymers 0.000 claims abstract description 175
- 229910052751 metal Inorganic materials 0.000 claims abstract description 100
- 239000002184 metal Substances 0.000 claims abstract description 100
- 239000011229 interlayer Substances 0.000 claims abstract description 14
- 239000012535 impurity Substances 0.000 claims abstract description 9
- 238000009792 diffusion process Methods 0.000 claims description 59
- 150000004767 nitrides Chemical class 0.000 claims description 42
- 238000000034 method Methods 0.000 claims description 31
- 229910021332 silicide Inorganic materials 0.000 claims description 26
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 26
- 239000000758 substrate Substances 0.000 claims description 25
- 238000005530 etching Methods 0.000 claims description 21
- 238000000151 deposition Methods 0.000 claims description 14
- 238000010438 heat treatment Methods 0.000 claims description 3
- 239000006185 dispersion Substances 0.000 abstract 1
- 230000003071 parasitic effect Effects 0.000 description 7
- 238000005498 polishing Methods 0.000 description 3
- 239000000126 substance Substances 0.000 description 3
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 2
- 230000015572 biosynthetic process Effects 0.000 description 2
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 1
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 229910052785 arsenic Inorganic materials 0.000 description 1
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 1
- 238000000231 atomic layer deposition Methods 0.000 description 1
- 229910052796 boron Inorganic materials 0.000 description 1
- 229910017052 cobalt Inorganic materials 0.000 description 1
- 239000010941 cobalt Substances 0.000 description 1
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000004518 low pressure chemical vapour deposition Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66666—Vertical transistors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/7827—Vertical transistors
Definitions
- the present invention relates to a semiconductor device manufacturing method and a semiconductor device.
- SGT Surrounding Gate Transistor
- a metal gate last process for creating a metal gate after a high-temperature process has been put into practical use in order to achieve both a metal gate process and a high-temperature process at the time of manufacture (for example, see Non-Patent Document 1). reference). That is, in a conventional MOS transistor, after forming a gate with polysilicon, an interlayer insulating film is deposited on the polysilicon, and the polysilicon gate is exposed by CMP (Chemical Mechanical Polishing). And after processing the polysilicon gate by etching, it is manufactured by a manufacturing method of depositing metal.
- CMP Chemical Mechanical Polishing
- the conventional MOS transistor uses the first insulating film.
- a first insulating film is formed around one fin-shaped semiconductor layer, and then the first insulating film is etched back to form a fin-shaped semiconductor.
- the parasitic capacitance between the gate wiring and the substrate is reduced.
- the SGT it is necessary to use the first insulating film in order to reduce the parasitic capacitance generated between the gate wiring and the substrate.
- the SGT includes a columnar semiconductor layer in addition to the fin-shaped semiconductor layer, some device is required to form the columnar semiconductor layer.
- contact holes for a columnar silicon layer are formed by etching using a mask, and then a contact hole for a planar silicon layer and a gate wiring is formed by etching using a mask.
- a contact hole for a planar silicon layer and a gate wiring is formed by etching using a mask.
- JP-A-2-71556 Japanese Patent Laid-Open No. 2-188966 Japanese Patent Laid-Open No. 3-145761 JP 2011-258780 A
- the present invention has been made in view of the above-described circumstances, reduces a parasitic capacitance generated between a gate wiring and a substrate, is a gate last process, and uses only one mask for contact.
- An object of the present invention is to provide a manufacturing method of the above and a semiconductor device obtained thereby.
- a method for manufacturing a semiconductor device includes: A fin-like silicon layer is formed on a silicon substrate, a first insulating film is formed around the fin-like silicon layer, a columnar silicon layer is formed on the fin-like silicon layer, and the diameter of the fin-like silicon layer is A first step of forming it to be equal to the width; Subsequent to the first step, a second step of implanting impurities into the upper part of the columnar silicon layer, the upper part of the fin-like silicon layer, and the lower part of the columnar silicon layer to form a diffusion layer, Subsequent to the second step, a gate insulating film, a polysilicon gate electrode, a polysilicon gate wiring, and a polysilicon gate pad are formed, and the gate insulating film covers the periphery and top of the columnar silicon layer.
- a silicon gate electrode covers the gate insulating film, and the polysilicon gate electrode, and the upper surface of the polysilicon after forming the polysilicon gate wiring and the polysilicon gate pad are formed on the diffusion on the columnar silicon layer.
- a third step in which the width of the polysilicon gate electrode and the polysilicon gate pad is wider than the width of the polysilicon gate wiring, the position being higher than the gate insulating film located on the layer;
- an interlayer insulating film is deposited, the polysilicon gate electrode, the polysilicon gate wiring, and the polysilicon gate pad are exposed, and the polysilicon gate electrode and the polysilicon gate are exposed.
- a fifth step of forming so as to extend in a direction orthogonal to the fin-like silicon layer Following the fifth step, a sixth step of forming a contact directly connecting the diffusion layer above the columnar silicon layer, It is characterized by that.
- Forming a first resist for forming a fin-like silicon layer on the silicon substrate etching the silicon substrate with the first resist to form the fin-like silicon layer; Removing the first resist; Depositing a first insulating film around the fin-like silicon layer, etching back the first insulating film, exposing an upper portion of the fin-like silicon layer; A second resist is formed so as to be orthogonal to the fin-like silicon layer, the fin-like silicon layer is etched using the second resist, and the second resist is removed to thereby remove the fin Forming the columnar silicon layer so that a portion where the columnar silicon layer and the second resist are orthogonal to each other is the columnar silicon layer; It is preferable.
- a second oxide film is deposited from above, a first nitride film is formed on the second oxide film, and the first nitride film is etched to remain in a sidewall shape, After that, by implanting impurities, a diffusion layer is formed in the upper part of the columnar silicon layer and the upper part of the fin-like silicon layer, and the first nitride film and the second oxide film are removed, and thereafter Heat treatment, It is preferable.
- a gate insulating film is formed, polysilicon is deposited, and the upper surface of the polysilicon after planarizing the polysilicon is flattened so as to be higher than the gate insulating film on the diffusion layer above the columnar silicon layer.
- a second nitride film is deposited, a third resist for forming a polysilicon gate electrode, a polysilicon gate wiring, and a polysilicon gate pad is formed, the second nitride film is etched, and the polysilicon is etched. Etching, forming the polysilicon gate electrode, the polysilicon gate wiring and the polysilicon gate pad, etching the gate insulating film, and removing the third resist; It is preferable.
- a third nitride film is deposited, and the third nitride film is etched to leave it in a sidewall shape, and then a metal layer is deposited, and silicide is added to the diffusion layer above the fin-like silicon layer. It is preferable to form in the upper part.
- a fourth nitride film is deposited, an interlayer insulating film is deposited and planarized, and the polysilicon gate electrode, the polysilicon gate wiring and the polysilicon gate pad are exposed, and the polysilicon gate electrode and the polysilicon gate are exposed.
- the columnar silicon is removed by removing the wiring and the polysilicon gate pad, embedding a metal in a portion where the polysilicon gate electrode and the polysilicon gate wiring and the polysilicon gate pad existed, and etching the metal. It is preferable that the gate insulating film on the diffusion layer in the upper part of the layer is exposed to form the metal gate electrode, the metal gate wiring, and the metal gate pad.
- the columnar shape is formed.
- contact holes are formed on the silicon layer and the metal gate pad.
- a semiconductor device provides: A fin-like silicon layer formed on a silicon substrate; A first insulating film formed around the fin-like silicon layer; A columnar silicon layer formed on the fin-like silicon layer; The columnar silicon layer has the same diameter as the fin-shaped silicon layer, and a diffusion layer formed on the fin-shaped silicon layer and on the columnar silicon layer; A diffusion layer formed on top of the columnar silicon layer; A silicide formed on top of a diffusion layer on top of the fin-like silicon layer; A gate insulating film formed around the columnar silicon layer; A metal gate electrode formed around the gate insulating film; A metal gate wiring extending in a direction orthogonal to the fin-like silicon layer connected to the metal gate electrode; A metal gate pad connected to the metal gate wiring, The width of the metal gate electrode and the width of the metal gate pad are wider than the width of the metal gate wiring, A contact formed on the diffusion layer formed on the columnar silicon layer; and The diffusion layer formed on the columnar silicon layer and the contact are directly connected. It
- a method for manufacturing a semiconductor device which is a gate last process, which can reduce parasitic capacitance generated between a gate wiring and a substrate, and a semiconductor device obtained thereby.
- FIG. (A) is a plan view of the semiconductor device according to the present invention
- (b) is a cross-sectional view taken along line XX ′ in (a)
- (c) is taken along line YY ′ in (a).
- FIG. (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- (A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A) is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention, (b) is sectional drawing in the XX 'line of (a), (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- A is a top view for demonstrating the manufacturing method of the semiconductor device based on this invention,
- (b) is sectional drawing in the XX 'line of (a),
- (c) is (a).
- FIG. 6 is a sectional view taken along line YY ′.
- a manufacturing method in which a fin-like silicon layer is formed on a silicon substrate, a first insulating film is formed around the fin-like silicon layer, and a columnar silicon layer is formed on the fin-like silicon layer will be described.
- a first resist 102 for forming a fin-like silicon layer is formed on a silicon substrate 101.
- the silicon substrate 101 is etched to form a fin-like silicon layer 103.
- the fin-like silicon layer is formed using a resist as a mask, but a hard mask such as an oxide film or a nitride film may be used instead of the resist.
- the first resist 102 is removed.
- a first insulating film 104 made of an oxide is deposited around the fin-like silicon layer 103.
- an oxide film formed by high-density plasma or an oxide film formed by low-pressure chemical vapor deposition can be used instead of such a deposition method.
- the first insulating film 104 is etched back to expose the upper portion of the fin-like silicon layer 103.
- the process up to here is the same as the manufacturing method of the fin-like silicon layer of Patent Document 2.
- a second resist 105 is formed so as to be orthogonal to the fin-like silicon layer 103.
- a portion where the fin-like silicon layer 103 and the resist 105 are orthogonal to each other becomes a columnar silicon layer. Since a line-shaped resist can be used in this way, there is a low possibility that the resist will collapse after pattern formation, and the process is stable.
- the fin-like silicon layer 103 is formed by etching.
- the diameter of the columnar silicon layer 106 is equal to the width of the fin-like silicon layer 103.
- a columnar silicon layer 106 is formed on the fin-shaped silicon layer 103, and a first insulating film 104 is formed around the fin-shaped silicon layer 103.
- the second resist 105 is removed.
- a second oxide film 107 is deposited to form a first nitride film 108.
- the first nitride film 108 may be formed in a sidewall shape on the sidewall of the columnar silicon layer.
- the first nitride film 108 is etched to remain in a sidewall shape.
- impurities such as arsenic, phosphorus, and boron are implanted to form the diffusion layer 110 on the columnar silicon layer and the diffusion layers 109 and 111 on the fin-like silicon layer 103.
- the first nitride film 108 and the second oxide film 107 are removed.
- a method of manufacturing a polysilicon gate electrode, a polysilicon gate wiring, and a polysilicon gate pad with polysilicon will be described.
- the polysilicon gate electrode, the polysilicon gate wiring, and the polysilicon gate pad are exposed by CMP (Chemical Mechanical Polishing), so that the upper part of the columnar silicon layer is not exposed by CMP. It is necessary to make it.
- a gate insulating film 113 is formed, polysilicon 114 is deposited, and the surface thereof is flattened.
- the upper surface of the polysilicon 114 after planarization is positioned higher than the gate insulating film 113 on the diffusion layer 110 above the columnar silicon layer 106. Accordingly, after depositing the interlayer insulating film, when the polysilicon gate electrode 114a, the polysilicon gate wiring 114b, and the polysilicon gate pad 114c are exposed by CMP, the upper portion of the columnar silicon layer is not exposed by CMP. .
- a second nitride film 115 is deposited.
- the second nitride film 115 indicates that when silicide is formed on the fin-like silicon layer 103, silicide is formed on the polysilicon gate electrode 114a, polysilicon gate wiring 114b, and polysilicon gate pad 114c. It is for preventing.
- a third resist 116 for forming the polysilicon gate electrode 114a, the polysilicon gate wiring 114b, and the polysilicon gate pad 114c is formed.
- the portion serving as the gate wiring is orthogonal to the fin-like silicon layer 103 in order to reduce the parasitic capacitance generated between the gate wiring and the substrate.
- the width of the polysilicon gate electrode 114a and the width of the polysilicon gate pad 114c are preferably wider than the width of the polysilicon gate wiring 114b.
- a second nitride film 115 is formed by etching.
- the polysilicon 114 is etched to form a polysilicon gate electrode 114a, a polysilicon gate wiring 114b, and a polysilicon gate pad 114c.
- the bottom portion of the gate insulating film 113 is removed by etching.
- the polysilicon gate electrode 114a, the polysilicon gate wiring 114b, and the polysilicon gate pad 114c are formed of polysilicon.
- the upper surface of the polysilicon after the polysilicon gate electrode 114a, the polysilicon gate wiring 114b, and the polysilicon gate pad 114c is formed is higher than the gate insulating film 113 on the diffusion layer 110 on the columnar silicon layer 106. It has become.
- silicide on the fin-like silicon layer will be described. This method is characterized in that no silicide is formed in the diffusion layer 110 above the polysilicon gate electrode 114 a, the polysilicon gate wiring 114 b, the polysilicon gate pad 114 c, and the columnar silicon layer 106. Note that formation of silicide in the diffusion layer 110 above the columnar silicon layer 106 is not preferable because the number of manufacturing steps increases.
- a third nitride film 117 is deposited.
- the third nitride film 117 is etched to remain in a sidewall shape.
- a metal such as nickel or cobalt is deposited to form a silicide 118 on the diffusion layer 112 above the fin-like silicon layer 103.
- the polysilicon gate electrode 114a, the polysilicon gate wiring 114b, and the polysilicon gate pad 114c are covered with the third nitride film 117 and the second nitride film 115, and the diffusion layer 110 on the columnar silicon layer 106 is Since it is covered with the gate insulating film 113, the polysilicon gate electrode 114a, and the polysilicon gate wiring 114b, no silicide is formed.
- silicide is formed on the fin-like silicon layer 103.
- the polysilicon gate electrode 114a, the polysilicon gate wiring 114b, and the polysilicon gate pad 114c are exposed by CMP, and the polysilicon gate electrode 114a is exposed.
- a method of manufacturing a gate last in which metal is deposited after removing the polysilicon gate wiring 114b and the polysilicon gate pad 114c by etching will be described.
- a fourth nitride film 119 is deposited to protect the silicide 118.
- an interlayer insulating film 120 is deposited and the surface thereof is planarized by CMP.
- the polysilicon gate electrode 114a, the polysilicon gate wiring 114b, and the polysilicon gate pad 114c are exposed by CMP.
- the polysilicon gate electrode 114a, the polysilicon gate wiring 114b, and the polysilicon gate pad 114c are etched.
- the metal 121 is deposited and the surface thereof is flattened, and the metal 121 is applied to the portion where the polysilicon gate electrode 114a, the polysilicon gate wiring 114b, and the polysilicon gate pad 114c existed. Embed. It is preferable to use atomic layer deposition for the embedding here.
- the metal 121 is etched to expose the gate insulating film 113 on the diffusion layer 110 above the columnar silicon layer 106. Thereby, the metal gate electrode 121a, the metal gate wiring 121b, and the metal gate pad 121c are formed.
- the above process is a method of manufacturing a semiconductor device by gate last in which after depositing an interlayer insulating film, a polysilicon gate is exposed by CMP, the polysilicon gate is etched, and then a metal layer is deposited.
- the fifth nitride film 122 is thicker than half the width of the polysilicon gate wiring 114b, half the width of the polysilicon gate electrode 114a, and the width of the polysilicon gate pad 114c. Deposit so that it is thinner than half.
- contact holes 123 and 124 are formed on the columnar silicon layer 106 and the metal gate pad 121c.
- the fifth nitride film 122 and the gate insulating film 113 at the bottom of the contact holes 123 and 124 are removed. This eliminates the need for a mask for the contact hole 123 above the columnar silicon layer and the contact hole 124 above the metal gate pad 121c.
- a fourth resist 125 for forming the contact hole 126 is formed on the fin-like silicon layer 103.
- a contact hole 126 is formed by etching the fifth nitride film 122 and the interlayer insulating film 120.
- the fourth resist 125 is removed.
- the fifth nitride film 122, the fourth nitride film 119, and the gate insulating film 113 are etched to expose the silicide 118 and the diffusion layer 110.
- the gate insulating film 113 is etched to expose the silicide 118 and the diffusion layer 110.
- metal is deposited to form contacts 127, 128, and 129.
- contacts 127, 128, and 129 can be formed in the semiconductor device. According to this manufacturing method, since no silicide is formed in the diffusion layer 110 above the columnar silicon layer 106, the contact 128 and the diffusion layer 110 above the columnar silicon layer 106 are directly connected.
- a method for forming the metal wiring layer will be described. That is, first, as shown in FIG. 36, a metal 130 is deposited.
- fifth resists 131, 132, 133 for forming metal wiring are formed.
- the metal 130 is etched to form metal wirings 134, 135, and 136.
- the fifth resists 131, 132, and 133 are removed.
- metal wirings 134, 135, and 136 that are metal wiring layers are formed.
- FIG. 1 shows a semiconductor device manufactured by the manufacturing method described above.
- the semiconductor device shown in FIG. 1 is formed on a fin-like silicon layer 103 formed on a substrate 101, a first insulating film 104 formed around the fin-like silicon layer 103, and the fin-like silicon layer 103.
- the columnar silicon layer 106 and the diameter of the columnar silicon layer 106 are equal to the width of the fin-like silicon layer 103, and include a diffusion layer 112 formed at the upper part of the fin-like silicon layer 103 and the lower part of the columnar silicon layer 106.
- the semiconductor device shown in FIG. 1 further includes a diffusion layer 110 formed above the columnar silicon layer 106, a silicide 118 formed above the diffusion layer 112 above the fin-like silicon layer 103, and the columnar silicon layer 106.
- a wiring 121b and a metal gate pad 121c connected to the metal gate wiring 121b are provided.
- the width of the metal gate electrode 121a and the metal gate pad 121c is wider than the width of the metal gate wiring 121b.
- the semiconductor device shown in FIG. 1 includes a contact 128 formed on the diffusion layer 110 and a structure in which the diffusion layer 110 and the contact 128 are directly connected.
- the embodiment of the present invention is a gate last process that can reduce the parasitic capacitance generated between the gate wiring and the substrate, and is an SGT that uses only one mask for contact. A manufacturing method and the structure of SGT obtained thereby are provided.
- the fin-like silicon layer 103, the first insulating film 104, and the columnar silicon layer 106 can be easily formed because the conventional FINFET manufacturing method is used as a base. Can do.
- silicide is formed on the columnar silicon layer.
- the deposition temperature of polysilicon is higher than the temperature for forming silicide, the silicide is formed after forming the polysilicon gate. It will be necessary. For this reason, when silicide is formed on the silicon pillar, after forming the polysilicon gate, a hole is formed in the upper portion of the polysilicon gate electrode, a sidewall of the insulating film is formed on the sidewall of the hole, and further silicide is formed.
- the process of forming and filling an insulating film in the opened hole has a drawback of increasing the number of manufacturing steps.
- the diffusion layer is formed before the polysilicon gate electrode 114a and the polysilicon gate wiring 114b are formed, the columnar silicon layer 106 is covered with the polysilicon gate electrode 114a, and the silicide is finned. It is formed only on the upper portion of the silicon layer 103. Then, after forming a gate with polysilicon and further depositing an interlayer insulating film 120, the polysilicon gate is exposed by CMP (Chemical Mechanical Polishing), and the polysilicon gate is etched. Thereafter, a metal gate last manufacturing method of depositing metal can be used. Therefore, according to this method for manufacturing a semiconductor device, an SGT having a metal gate can be easily manufactured.
- CMP Chemical Mechanical Polishing
- the width of the polysilicon gate electrode 114a and the polysilicon gate pad 114c is wider than the width of the polysilicon gate wiring 114b, and after forming the metal gate, in the hole formed by etching the polysilicon gate, A fifth nitride film 122 that is thicker than half the width of the polysilicon gate wiring 114b, half the width of the polysilicon gate electrode 114a, and thinner than half the width of the polysilicon gate pad 114c is deposited.
- the contact holes 123 and 124 can be formed on the columnar silicon layer 106 and the metal gate pad 121c. Therefore, the contact holes in the columnar silicon layer, which are required in the conventional SGT manufacturing method, are masked. The process of etching using is eliminated. That is, only one mask for contact formation can be provided.
- Metal gate wiring 121c Metal gate pad 122. Fifth nitride film 123. Contact hole 124. Contact hole 125. Fourth resist 126. Contact hole 127. Contact 128. Contact 129. Contact 130. Metal 131. Fifth resist 132. Fifth resist 133. Fifth resist 134. Metal wiring 135. Metal wiring 136. Metal wiring
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Insulated Gate Type Field-Effect Transistor (AREA)
- Thin Film Transistor (AREA)
- Electrodes Of Semiconductors (AREA)
Abstract
Description
即ち、従来、MOSトランジスタは、ポリシリコンでゲートを作成した後、ポリシリコンの上から層間絶縁膜を堆積し、CMP(化学機械研磨)によりポリシリコンゲートを露出する。そして、そのポリシリコンゲートをエッチングで加工した後、メタルを堆積する製造方法によって製造されている。このため、SGTにおいても、メタルゲートプロセスと高温プロセスとを両立させるために、高温プロセス後にメタルゲートを作成するメタルゲートラストプロセスを用いることが必要となる。SGTでは、柱状シリコン層の上部がゲートよりも高い位置にあるため、メタルゲートラストプロセスを用いるにあたって何らかの工夫が必要となる。
シリコン基板上にフィン状シリコン層を形成し、前記フィン状シリコン層の周囲に第一の絶縁膜を形成し、前記フィン状シリコン層の上部に柱状シリコン層をその直径が前記フィン状シリコン層の幅と等しくなるように形成する第1工程と、
前記第1工程に続いて、前記柱状シリコン層上部、前記フィン状シリコン層上部、及び前記柱状シリコン層下部にそれぞれ不純物を注入し拡散層を形成する第2工程と、
前記第2工程に続いて、ゲート絶縁膜、ポリシリコンゲート電極、ポリシリコンゲート配線、及びポリシリコンゲートパッドを作成するとともに、前記ゲート絶縁膜が前記柱状シリコン層の周囲と上部を覆い、前記ポリシリコンゲート電極が前記ゲート絶縁膜を覆い、前記ポリシリコンゲート電極と、前記ポリシリコンゲート配線と前記ポリシリコンゲートパッドとを形成した後のポリシリコンの上面とを、前記柱状シリコン層上部の前記拡散層上に位置する前記ゲート絶縁膜よりも高い位置とし、前記ポリシリコンゲート電極と前記ポリシリコンゲートパッドの幅とは前記ポリシリコンゲート配線の幅よりも広くする第3工程と、
前記第3工程に続いて、前記フィン状シリコン層上部の前記拡散層上部にシリサイドを形成する第4工程と、
前記第4工程に続いて、層間絶縁膜を堆積し、前記ポリシリコンゲート電極と、前記ポリシリコンゲート配線と、前記ポリシリコンゲートパッドとを露出し、前記ポリシリコンゲート電極と、前記ポリシリコンゲート配線と、前記ポリシリコンゲートパッドとをエッチングし、その後、金属層を堆積し、金属ゲート電極、金属ゲート配線及び金属ゲートパッドを形成するとともに、前記金属ゲート配線は、前記金属ゲート電極に接続された前記フィン状シリコン層に直交する方向に延在させるように形成する第5工程と、
前記第5工程に続いて、前記柱状シリコン層上部の前記拡散層を直接接続するコンタクトを形成する第6工程と、を有する、
ことを特徴とする。
前記フィン状シリコン層の周囲に第1の絶縁膜を堆積し、前記第1の絶縁膜をエッチバックし、前記フィン状シリコン層の上部を露出させ、
前記フィン状シリコン層に直交するように第2のレジストを形成し、前記第2のレジストを用いて、前記フィン状シリコン層をエッチングすると共に、前記第2のレジストを除去することにより、前記フィン状シリコン層と前記第2のレジストとが直交する部分が前記柱状シリコン層となるように前記柱状シリコン層を形成する、
ことが好ましい。
その後、不純物を注入することで、前記柱状シリコン層上部と前記フィン状シリコン層上部とに拡散層を形成すると共に、前記第1の窒化膜と前記第2の酸化膜とを除去し、しかる後に熱処理を行う、
ことが好ましい。
ゲート絶縁膜を形成し、ポリシリコンを堆積すると共に、前記ポリシリコンを平坦化後のポリシリコンの上面が前記柱状シリコン層上部の拡散層の上の前記ゲート絶縁膜より高い位置になるように平坦化し、
第2の窒化膜を堆積し、ポリシリコンゲート電極及びポリシリコンゲート配線とポリシリコンゲートパッドを形成するための第3のレジストを形成し、前記第2の窒化膜をエッチングし、前記ポリシリコンをエッチングし、前記ポリシリコンゲート電極及び前記ポリシリコンゲート配線と前記ポリシリコンゲートパッドを形成し、前記ゲート絶縁膜をエッチングし、第3のレジストを除去する、
ことが好ましい。
シリコン基板上に形成されたフィン状シリコン層と、
前記フィン状シリコン層の周囲に形成された第1の絶縁膜と、
前記フィン状シリコン層上に形成された柱状シリコン層と、
前記柱状シリコン層の直径は前記フィン状シリコン層の幅と同じであって、前記フィン状シリコン層の上部と前記柱状シリコン層の下部とに形成された拡散層と、
前記柱状シリコン層の上部に形成された拡散層と、
前記フィン状シリコン層の上部にある拡散層の上部に形成されたシリサイドと、
前記柱状シリコン層の周囲に形成されたゲート絶縁膜と、
前記ゲート絶縁膜の周囲に形成された金属ゲート電極と、
前記金属ゲート電極に接続された前記フィン状シリコン層に直交する方向に延在する金属ゲート配線と、
前記金属ゲート配線に接続された金属ゲートパッドと、を有し、
前記金属ゲート電極の幅と前記金属ゲートパッドの幅とは前記金属ゲート配線の幅よりも広くされており、
前記柱状シリコン層上部に形成された前記拡散層上に形成されたコンタクトと、をさらに有し、
前記柱状シリコン層上部に形成された前記拡散層と前記コンタクトとは直接接続されている、
ことを特徴とする。
まず、図2に示すように、シリコン基板101上にフィン状シリコン層を形成するための第1のレジスト102を形成する。
以上の工程を経ることで、ポリシリコンでポリシリコンゲート電極114a、ポリシリコンゲート配線114b及びポリシリコンゲートパッド114cが形成される。
以上の工程を経ることにより、フィン状シリコン層103の上部にシリサイドが形成される。
即ち、まず、図36に示すように、金属130を堆積する。
以上の工程を経ることにより、金属配線層である金属配線134、135、136が形成される。
図1に示す半導体装置は、基板101上に形成されたフィン状シリコン層103と、フィン状シリコン層103の周囲に形成された第1の絶縁膜104と、フィン状シリコン層103上に形成された柱状シリコン層106と、柱状シリコン層106の直径はフィン状シリコン層103の幅と等しく、フィン状シリコン層103の上部と柱状シリコン層106の下部に形成された拡散層112とを備える。
102.第1のレジスト
103.フィン状シリコン層
104.第1の絶縁膜
105.第2のレジスト
106.柱状シリコン層
107.第2の酸化膜
108.第1の窒化膜
109.拡散層
110.拡散層
111.拡散層
112.拡散層
113.ゲート絶縁膜
114.ポリシリコン
114a.ポリシリコンゲート電極
114b.ポリシリコンゲート配線
114c.ポリシリコンゲートパッド
115.第2の窒化膜
116.第3のレジスト
117.第3の窒化膜
118.シリサイド
119.第4の窒化膜
120.層間絶縁膜
121.金属層(金属)
121a.金属ゲート電極
121b.金属ゲート配線
121c.金属ゲートパッド
122.第5の窒化膜
123.コンタクト孔
124.コンタクト孔
125.第4のレジスト
126.コンタクト孔
127.コンタクト
128.コンタクト
129.コンタクト
130.金属
131.第5のレジスト
132.第5のレジスト
133.第5のレジスト
134.金属配線
135.金属配線
136.金属配線
Claims (8)
- シリコン基板上にフィン状シリコン層を形成し、前記フィン状シリコン層の周囲に第一の絶縁膜を形成し、前記フィン状シリコン層の上部に柱状シリコン層をその直径が前記フィン状シリコン層の幅と等しくなるように形成する第1工程と、
前記第1工程に続いて、前記柱状シリコン層上部、前記フィン状シリコン層上部、及び前記柱状シリコン層下部にそれぞれ不純物を注入し拡散層を形成する第2工程と、
前記第2工程に続いて、ゲート絶縁膜、ポリシリコンゲート電極、ポリシリコンゲート配線、及びポリシリコンゲートパッドを作成するとともに、前記ゲート絶縁膜が前記柱状シリコン層の周囲と上部を覆い、前記ポリシリコンゲート電極が前記ゲート絶縁膜を覆い、前記ポリシリコンゲート電極と、前記ポリシリコンゲート配線と前記ポリシリコンゲートパッドとを形成した後のポリシリコンの上面とを、前記柱状シリコン層上部の前記拡散層上に位置する前記ゲート絶縁膜よりも高い位置とし、前記ポリシリコンゲート電極と前記ポリシリコンゲートパッドの幅とは前記ポリシリコンゲート配線の幅よりも広くする第3工程と、
前記第3工程に続いて、前記フィン状シリコン層上部の前記拡散層上部にシリサイドを形成する第4工程と、
前記第4工程に続いて、層間絶縁膜を堆積し、前記ポリシリコンゲート電極と、前記ポリシリコンゲート配線と、前記ポリシリコンゲートパッドとを露出し、前記ポリシリコンゲート電極と、前記ポリシリコンゲート配線と、前記ポリシリコンゲートパッドとをエッチングし、その後、金属層を堆積し、金属ゲート電極、金属ゲート配線及び金属ゲートパッドを形成するとともに、前記金属ゲート配線は、前記金属ゲート電極に接続された前記フィン状シリコン層に直交する方向に延在させるように形成する第5工程と、
前記第5工程に続いて、前記柱状シリコン層上部の前記拡散層を直接接続するコンタクトを形成する第6工程と、を有する、
ことを特徴とする半導体装置の製造方法。 - 前記シリコン基板上にフィン状シリコン層を形成するための第1のレジストを形成し、前記第1のレジストを用いて、前記シリコン基板をエッチングし、前記フィン状シリコン層を形成し、その後に前記第1のレジストを除去し、
前記フィン状シリコン層の周囲に第1の絶縁膜を堆積し、前記第1の絶縁膜をエッチバックし、前記フィン状シリコン層の上部を露出させ、
前記フィン状シリコン層に直交するように第2のレジストを形成し、前記第2のレジストを用いて、前記フィン状シリコン層をエッチングすると共に、前記第2のレジストを除去することにより、前記フィン状シリコン層と前記第2のレジストとが直交する部分が前記柱状シリコン層となるように前記柱状シリコン層を形成する、
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記シリコン基板上に形成されたフィン状シリコン層と、前記フィン状シリコン層の周囲に形成された第1の絶縁膜と、前記フィン状シリコン層の上部に形成された柱状シリコン層とを有する構造の上から、第2の酸化膜を堆積し、前記第2の酸化膜上に第1の窒化膜を形成し、前記第1の窒化膜をエッチングすることにより、サイドウォール状に残存させ、
その後、不純物を注入することで、前記柱状シリコン層上部と前記フィン状シリコン層上部とに拡散層を形成すると共に、前記第1の窒化膜と前記第2の酸化膜とを除去し、しかる後に熱処理を行う、
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記シリコン基板上に形成されたフィン状シリコン層と、前記フィン状シリコン層の周囲に形成された第1の絶縁膜と、前記フィン状シリコン層の上部に形成された柱状シリコン層と、前記フィン状シリコン層の上部と前記柱状シリコン層の下部とに形成された拡散層と、前記柱状シリコン層の上部に形成された拡散層と、を有する構造において、
ゲート絶縁膜を形成し、ポリシリコンを堆積すると共に、当該ポリシリコンを平坦化した後のポリシリコンの上面が前記柱状シリコン層上部にある拡散層上の前記ゲート絶縁膜よりも高い位置となるように平坦化し、
第2の窒化膜を堆積し、前記ポリシリコンゲート電極、前記ポリシリコンゲート配線及び前記ポリシリコンゲートパッドとを形成するための第3のレジストを形成し、前記第3のレジストを用いて前記第2の窒化膜と前記ポリシリコンとをエッチングし、前記ポリシリコンゲート電極、前記ポリシリコンゲート配線及び前記ポリシリコンゲートパッドを形成するとともに、前記ゲート絶縁膜をエッチングし、しかる後に、第3のレジストを除去する、
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 第3の窒化膜を堆積し、前記第3の窒化膜をエッチングすることで、サイドウォール状に残存させた後、金属層を堆積し、シリサイドを前記フィン状シリコン層の上部にある拡散層の上部に形成する、ことを特徴とする請求項4に記載の半導体装置の製造方法。
- 第4の窒化膜を堆積し、層間絶縁膜を堆積すると共に平坦化し、前記ポリシリコンゲート電極、前記ポリシリコンゲート配線及び前記ポリシリコンゲートパッドを露出させ、前記ポリシリコンゲート電極、前記ポリシリコンゲート配線及び前記ポリシリコンゲートパッドを除去し、前記ポリシリコンゲート電極及び前記ポリシリコンゲート配線と前記ポリシリコンゲートパッドが存在していた部分に金属を埋めこみ、前記金属をエッチングすることにより、前記柱状シリコン層上部における前記拡散層上のゲート絶縁膜を露出させ、前記金属ゲート電極、前記金属ゲート配線及び前記金属ゲートパッドを形成する、
ことを特徴とする請求項5に記載の半導体装置の製造方法。 - 前記ポリシリコンゲート配線の幅の半分よりも厚く、前記ポリシリコンゲート電極の幅の半分、かつ、前記ポリシリコンゲートパッドの幅の半分よりも薄い第5の窒化膜を堆積することにより、前記柱状シリコン層上と前記金属ゲートパッド上とにコンタクト孔を形成する、ことを特徴とする請求項6に記載の半導体装置の製造方法。
- シリコン基板上に形成されたフィン状シリコン層と、
前記フィン状シリコン層の周囲に形成された第1の絶縁膜と、
前記フィン状シリコン層上に形成された柱状シリコン層と、
前記柱状シリコン層の直径は前記フィン状シリコン層の幅と同じであって、前記フィン状シリコン層の上部と前記柱状シリコン層の下部とに形成された拡散層と、
前記柱状シリコン層の上部に形成された拡散層と、
前記フィン状シリコン層の上部にある拡散層の上部に形成されたシリサイドと、
前記柱状シリコン層の周囲に形成されたゲート絶縁膜と、
前記ゲート絶縁膜の周囲に形成された金属ゲート電極と、
前記金属ゲート電極に接続された前記フィン状シリコン層に直交する方向に延在する金属ゲート配線と、
前記金属ゲート配線に接続された金属ゲートパッドと、を有し、
前記金属ゲート電極の幅と前記金属ゲートパッドの幅とは前記金属ゲート配線の幅よりも広くされており、
前記柱状シリコン層上部に形成された前記拡散層上に形成されたコンタクトと、をさらに有し、
前記柱状シリコン層上部に形成された前記拡散層と前記コンタクトとは直接接続されている、
ことを特徴とする半導体装置。
Priority Applications (5)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2012/062857 WO2013171908A1 (ja) | 2012-05-18 | 2012-05-18 | 半導体装置の製造方法及び半導体装置 |
JP2013552773A JP5662590B2 (ja) | 2012-05-18 | 2012-05-18 | 半導体装置の製造方法及び半導体装置 |
KR1020137030545A KR20140009509A (ko) | 2012-05-18 | 2012-05-18 | 반도체 장치의 제조 방법 및 반도체 장치 |
CN201280024037.7A CN103548125A (zh) | 2012-05-18 | 2012-05-18 | 半导体装置的制造方法以及半导体装置 |
TW102116729A TW201349312A (zh) | 2012-05-18 | 2013-05-10 | 半導體裝置的製造方法以及半導體裝置 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
PCT/JP2012/062857 WO2013171908A1 (ja) | 2012-05-18 | 2012-05-18 | 半導体装置の製造方法及び半導体装置 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2013171908A1 true WO2013171908A1 (ja) | 2013-11-21 |
Family
ID=49583348
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2012/062857 WO2013171908A1 (ja) | 2012-05-18 | 2012-05-18 | 半導体装置の製造方法及び半導体装置 |
Country Status (5)
Country | Link |
---|---|
JP (1) | JP5662590B2 (ja) |
KR (1) | KR20140009509A (ja) |
CN (1) | CN103548125A (ja) |
TW (1) | TW201349312A (ja) |
WO (1) | WO2013171908A1 (ja) |
Cited By (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015083287A1 (ja) * | 2013-12-06 | 2015-06-11 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置及び半導体装置の製造方法 |
JP5798276B1 (ja) * | 2014-06-16 | 2015-10-21 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
WO2015193940A1 (ja) * | 2014-06-16 | 2015-12-23 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置の製造方法、及び、半導体装置 |
JP2016005005A (ja) * | 2015-08-20 | 2016-01-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
JP2016105500A (ja) * | 2016-02-01 | 2016-06-09 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR20160023338A (ko) * | 2014-08-22 | 2016-03-03 | 에스케이하이닉스 주식회사 | 전자 장치 |
KR102472673B1 (ko) | 2016-03-21 | 2022-11-30 | 삼성전자주식회사 | 반도체 장치 및 그 제조 방법 |
KR102308779B1 (ko) * | 2017-04-10 | 2021-10-05 | 삼성전자주식회사 | 이종 컨택들을 구비하는 집적 회로 및 이를 포함하는 반도체 장치 |
Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007329480A (ja) * | 2006-06-09 | 2007-12-20 | Samsung Electronics Co Ltd | 埋め込みビットラインの形成方法 |
JP2008177565A (ja) * | 2007-01-18 | 2008-07-31 | Samsung Electronics Co Ltd | 垂直方向のチャンネルを有するアクセス素子、これを含む半導体装置、及びアクセス素子の形成方法 |
JP2010251678A (ja) * | 2009-04-20 | 2010-11-04 | Unisantis Electronics Japan Ltd | 半導体装置の製造方法 |
JP2010251586A (ja) * | 2009-04-17 | 2010-11-04 | Unisantis Electronics Japan Ltd | 半導体装置 |
JP2010258345A (ja) * | 2009-04-28 | 2010-11-11 | Unisantis Electronics Japan Ltd | Mosトランジスタ及びmosトランジスタを備えた半導体装置の製造方法 |
-
2012
- 2012-05-18 WO PCT/JP2012/062857 patent/WO2013171908A1/ja active Application Filing
- 2012-05-18 CN CN201280024037.7A patent/CN103548125A/zh not_active Withdrawn
- 2012-05-18 JP JP2013552773A patent/JP5662590B2/ja active Active
- 2012-05-18 KR KR1020137030545A patent/KR20140009509A/ko not_active Application Discontinuation
-
2013
- 2013-05-10 TW TW102116729A patent/TW201349312A/zh unknown
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2007329480A (ja) * | 2006-06-09 | 2007-12-20 | Samsung Electronics Co Ltd | 埋め込みビットラインの形成方法 |
JP2008177565A (ja) * | 2007-01-18 | 2008-07-31 | Samsung Electronics Co Ltd | 垂直方向のチャンネルを有するアクセス素子、これを含む半導体装置、及びアクセス素子の形成方法 |
JP2010251586A (ja) * | 2009-04-17 | 2010-11-04 | Unisantis Electronics Japan Ltd | 半導体装置 |
JP2010251678A (ja) * | 2009-04-20 | 2010-11-04 | Unisantis Electronics Japan Ltd | 半導体装置の製造方法 |
JP2010258345A (ja) * | 2009-04-28 | 2010-11-11 | Unisantis Electronics Japan Ltd | Mosトランジスタ及びmosトランジスタを備えた半導体装置の製造方法 |
Cited By (10)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2015083287A1 (ja) * | 2013-12-06 | 2015-06-11 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置及び半導体装置の製造方法 |
JP5798276B1 (ja) * | 2014-06-16 | 2015-10-21 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
WO2015193940A1 (ja) * | 2014-06-16 | 2015-12-23 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置の製造方法、及び、半導体装置 |
WO2015193939A1 (ja) * | 2014-06-16 | 2015-12-23 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッド | 半導体装置の製造方法、及び、半導体装置 |
JP5902868B1 (ja) * | 2014-06-16 | 2016-04-13 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
US9647142B2 (en) | 2014-06-16 | 2017-05-09 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing semiconductor device and semiconductor device |
US9780215B2 (en) | 2014-06-16 | 2017-10-03 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing semiconductor device and semiconductor device |
US10026842B2 (en) | 2014-06-16 | 2018-07-17 | Unisantis Electronics Singapore Pte. Ltd. | Method for producing semiconductor device |
JP2016005005A (ja) * | 2015-08-20 | 2016-01-12 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
JP2016105500A (ja) * | 2016-02-01 | 2016-06-09 | ユニサンティス エレクトロニクス シンガポール プライベート リミテッドUnisantis Electronics Singapore Pte Ltd. | 半導体装置の製造方法、及び、半導体装置 |
Also Published As
Publication number | Publication date |
---|---|
KR20140009509A (ko) | 2014-01-22 |
JPWO2013171908A1 (ja) | 2016-01-07 |
CN103548125A (zh) | 2014-01-29 |
TW201349312A (zh) | 2013-12-01 |
JP5662590B2 (ja) | 2015-02-04 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5695745B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
US9246001B2 (en) | Semiconductor device | |
US8697511B2 (en) | Method for producing semiconductor device and semiconductor device | |
JP5596237B2 (ja) | 半導体装置の製造方法と半導体装置 | |
JP5662590B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
JP5667699B2 (ja) | 半導体装置の製造方法と半導体装置 | |
US20130140627A1 (en) | Method for producing semiconductor device and semiconductor device | |
JP6235662B2 (ja) | 半導体装置 | |
JP5974066B2 (ja) | 半導体装置の製造方法と半導体装置 | |
JP5986618B2 (ja) | 半導体装置 | |
JP6329301B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
JP6284585B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
JPWO2014174672A1 (ja) | 半導体装置の製造方法及び半導体装置 | |
JP6156883B2 (ja) | 半導体装置の製造方法及び半導体装置 | |
JP6246276B2 (ja) | 半導体装置の製造方法と半導体装置 | |
JP6026610B2 (ja) | 半導体装置の製造方法と半導体装置 | |
JP5814437B2 (ja) | 半導体装置の製造方法と半導体装置 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
ENP | Entry into the national phase |
Ref document number: 2013552773 Country of ref document: JP Kind code of ref document: A Ref document number: 20137030545 Country of ref document: KR Kind code of ref document: A |
|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 12876893 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 12876893 Country of ref document: EP Kind code of ref document: A1 |