WO2013073417A1 - エッチング方法 - Google Patents
エッチング方法 Download PDFInfo
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- WO2013073417A1 WO2013073417A1 PCT/JP2012/078712 JP2012078712W WO2013073417A1 WO 2013073417 A1 WO2013073417 A1 WO 2013073417A1 JP 2012078712 W JP2012078712 W JP 2012078712W WO 2013073417 A1 WO2013073417 A1 WO 2013073417A1
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- substrate
- etching
- resist film
- mask layer
- plasma
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- 238000005530 etching Methods 0.000 title claims abstract description 137
- 238000000034 method Methods 0.000 title claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 170
- 229910052594 sapphire Inorganic materials 0.000 claims abstract description 48
- 239000010980 sapphire Substances 0.000 claims abstract description 48
- 230000008569 process Effects 0.000 claims abstract description 16
- 230000004075 alteration Effects 0.000 claims description 33
- 229910004298 SiO 2 Inorganic materials 0.000 claims description 13
- 238000004380 ashing Methods 0.000 claims description 8
- 239000000463 material Substances 0.000 abstract description 13
- 238000001020 plasma etching Methods 0.000 abstract description 11
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- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 4
- 238000001816 cooling Methods 0.000 description 4
- 150000004767 nitrides Chemical class 0.000 description 4
- 239000000243 solution Substances 0.000 description 4
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 description 3
- 229910052799 carbon Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 description 2
- GRYLNZFGIOXLOG-UHFFFAOYSA-N Nitric acid Chemical compound O[N+]([O-])=O GRYLNZFGIOXLOG-UHFFFAOYSA-N 0.000 description 2
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- 239000002356 single layer Substances 0.000 description 2
- ZAMOUSCENKQFHK-UHFFFAOYSA-N Chlorine atom Chemical compound [Cl] ZAMOUSCENKQFHK-UHFFFAOYSA-N 0.000 description 1
- 229910001218 Gallium arsenide Inorganic materials 0.000 description 1
- 239000007864 aqueous solution Substances 0.000 description 1
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- 238000005229 chemical vapour deposition Methods 0.000 description 1
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- 238000010894 electron beam technology Methods 0.000 description 1
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- AMGQUBHHOARCQH-UHFFFAOYSA-N indium;oxotin Chemical compound [In].[Sn]=O AMGQUBHHOARCQH-UHFFFAOYSA-N 0.000 description 1
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Images
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/48—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor body packages
- H01L33/58—Optical field-shaping elements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
- H01L33/0062—Processes for devices with an active region comprising only III-V compounds
- H01L33/0066—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound
- H01L33/007—Processes for devices with an active region comprising only III-V compounds with a substrate not being a III-V compound comprising nitride compounds
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3105—After-treatment
- H01L21/311—Etching the insulating layers by chemical or physical means
- H01L21/31105—Etching inorganic layers
- H01L21/31111—Etching inorganic layers by chemical means
- H01L21/31116—Etching inorganic layers by chemical means by dry-etching
- H01L21/31122—Etching inorganic layers by chemical means by dry-etching of layers not containing Si, e.g. PZT, Al2O3
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/005—Processes
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/20—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a particular shape, e.g. curved or truncated substrate
- H01L33/22—Roughened surfaces, e.g. at the interface between epitaxial layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0008—Processes
- H01L2933/0033—Processes relating to semiconductor body packages
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2933/00—Details relating to devices covered by the group H01L33/00 but not provided for in its subgroups
- H01L2933/0083—Periodic patterns for optical field-shaping in or on the semiconductor body or semiconductor body package, e.g. photonic bandgap structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L33/00—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
- H01L33/02—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies
- H01L33/12—Semiconductor devices having potential barriers specially adapted for light emission; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof characterised by the semiconductor bodies with a stress relaxation structure, e.g. buffer layer
Definitions
- the present invention relates to an etching method using plasma, a sapphire substrate processed by this etching method, and a light-emitting element including the sapphire substrate.
- a method for etching a workpiece a method in which a substrate having a resist film formed on the surface is etched using the resist film as a mask (see, for example, Patent Document 1).
- a sapphire substrate is etched by exciting a mixed gas obtained by adding a carbon-based gas to an etching gas into a plasma state, and the flow rate of the carbon-based gas is adjusted by adjusting the flow rate of the carbon-based gas.
- the taper shape is adjusted.
- the etching process is performed in consideration of the selection ratio determined by the material of the workpiece and the resist.
- the etching process is performed in consideration of the selection ratio determined by the material of the workpiece and the resist.
- processing of a desired shape cannot be performed unless a material with an appropriate selection ratio exists.
- the present invention has been made in view of the above circumstances, and an object of the present invention is to provide an etching method capable of increasing the etching selectivity between a workpiece and a resist, and a sapphire substrate processed by this etching method. And it is providing a light emitting element provided with this sapphire substrate.
- a resist film forming step of forming a resist film on a workpiece a pattern forming step of forming a predetermined pattern on the resist film, and the resist on which the pattern is formed Exposing the film to plasma under predetermined alteration conditions, altering the resist film to increase the etching selectivity, and exposing the workpiece to plasma under etching conditions different from the alteration conditions And an etching process for the workpiece, which etches the workpiece using the resist film having a high etching selectivity as a mask.
- condition for alteration may have a lower bias output than the condition for etching.
- the workpiece may be a substrate mask layer formed on a predetermined substrate.
- the etching method may include a substrate etching step of etching the substrate to be processed using the etched substrate mask layer as a mask.
- an uneven shape with a period of 1 ⁇ m or less may be formed on the substrate to be processed in the substrate etching step.
- an uneven shape having a depth of 300 nm or more may be formed on the substrate to be processed.
- the substrate to be processed may be sapphire.
- a sapphire substrate that has been subjected to uneven processing by the etching method is provided.
- a light emitting device having the sapphire substrate and a semiconductor light emitting layer formed on the sapphire substrate.
- a resist film forming step for forming a resist film on a work material, a pattern forming step for forming a predetermined pattern on the resist film, and the resist film on which the pattern is formed are predetermined.
- a resist alteration process in which the resist film is exposed to plasma under alteration conditions and the resist film is altered to increase the etching selectivity, and the workpiece is exposed to plasma under etching conditions different from the alteration conditions, and an etching selectivity ratio is obtained.
- the processed substrate is a sapphire substrate, and the sapphire substrate is etched using the etched substrate mask layer as a mask.
- Ar gas plasma is used as the plasma in the etching step, and a bias output higher than the alteration condition is applied, and the Ar gas plasma is applied to the substrate mask layer.
- An inductive etching method is provided.
- an uneven shape having a depth of 300 nm or more may be formed on the sapphire substrate in the substrate etching step.
- an uneven shape having a depth of 500 nm or more may be formed on the sapphire substrate in the substrate etching step.
- the etching method may include a residual film removing step of removing the residual film of the resist film by plasma ashing after the pattern forming step.
- the resist film may be cured while the pressed state is maintained, and the uneven structure of the mold may be transferred to the resist film.
- the sapphire substrate may be etched in the substrate etching step in a state where the resist film remains on the substrate mask layer.
- the sapphire substrate may be etched in a state where the Ni layer and the resist film are laminated.
- the etching method may include a mask layer removing step of removing the substrate mask layer remaining on the sapphire substrate using a predetermined stripping solution after the substrate etching step.
- the resist film is removed in advance by O 2 ashing, and then the substrate mask layer remaining on the sapphire substrate is removed using a predetermined stripping solution. Also good.
- a resist film forming step for forming a resist film on a work material, a pattern forming step for forming a predetermined pattern on the resist film, and the resist film on which the pattern is formed are predetermined.
- a resist alteration process in which the resist film is exposed to plasma under alteration conditions and the resist film is altered to increase the etching selectivity, and the workpiece is exposed to plasma under etching conditions different from the alteration conditions, and an etching selectivity ratio is obtained.
- the processed substrate is a sapphire substrate, and the sapphire substrate is etched using the etched substrate mask layer as a mask. And etching the substrate to form a concavo-convex shape on the sapphire substrate.
- Ar gas plasma is used as plasma, a predetermined bias output is applied, and the Ar gas plasma is applied to the substrate.
- the etching selectivity between the workpiece and the resist can be increased.
- FIG. 1 is a schematic explanatory view of a plasma etching apparatus showing an embodiment of the present invention.
- FIG. 2 is a flowchart showing an etching method.
- FIG. 3A shows the process of the etching method of the substrate to be processed and the mask layer, (a) shows the substrate to be processed before processing, (b) shows the state in which the mask layer is formed on the substrate to be processed, (c ) Shows a state where a resist film is formed on the mask layer, (d) shows a state where a mold is brought into contact with the resist film, and (e) shows a state where a pattern is formed on the resist film.
- FIG. 3A shows the process of the etching method of the substrate to be processed and the mask layer, (a) shows the substrate to be processed before processing, (b) shows the state in which the mask layer is formed on the substrate to be processed, (c ) Shows a state where a resist film is formed on the mask layer, (d) shows a state where a mold is
- FIG. 3B shows a process of the etching method of the substrate to be processed and the mask layer
- (f) shows a state in which the residual film of the resist film is removed
- (g) shows a state in which the resist film is altered
- (h) Indicates a state in which the mask layer is etched using the resist film as a mask
- (i) indicates a state in which the substrate to be processed is etched using the mask layer as a mask
- FIG. 3C shows the process of the etching method of the substrate to be processed and the mask layer
- (j) shows a state where the substrate to be processed is further etched using the mask layer as a mask
- (k) shows the mask layer remaining from the substrate to be processed.
- FIG. 4A is a schematic perspective view
- FIG. 4B is a schematic cross-sectional view of a light-emitting element provided with a substrate to be processed.
- FIG. 1 is a schematic explanatory view of a plasma etching apparatus showing an embodiment of the present invention.
- the plasma etching apparatus 1 is an inductively coupled (ICP) type, a flat substrate holding table 2 that holds a substrate to be processed 100, a container 3 that houses the substrate holding table 2, and a container 3, a coil 4 provided via a quartz plate 6, and a power source 5 connected to the substrate holder 2.
- the coil 4 is a three-dimensional spiral coil, which supplies high-frequency power from the center of the coil and is grounded at the outer periphery of the coil.
- the substrate 100 to be etched is placed on the substrate holder 2 directly or via a transfer tray.
- the substrate holder 2 has a built-in cooling mechanism for cooling the substrate 100 to be processed, and is controlled by the cooling control unit 7.
- the container 3 has a supply port and can supply various gases such as O 2 gas and Ar gas.
- the substrate 100 to be processed is placed on the substrate holder 2, and then the air in the container 3 is discharged to make the pressure reduced. Then, a predetermined processing gas is supplied into the container 3 to adjust the gas pressure in the container 3. Thereafter, high-frequency high-frequency power is supplied to the coil 4 and the substrate holder 2 for a predetermined time to generate a reactive gas plasma 8.
- the substrate 8 to be processed is etched by the plasma 8.
- FIG. 2 is a flowchart showing an etching method.
- the etching method of this embodiment includes a mask layer forming step S1, a resist film forming step S2, a pattern forming step S3, a residual film removing step S4, a resist alteration step S5, and a mask layer.
- FIG. 3A shows the process of the etching method of the substrate to be processed and the mask layer, (a) shows the substrate to be processed before processing, (b) shows the state in which the mask layer is formed on the substrate to be processed, (c ) Shows a state where a resist film is formed on the mask layer, (d) shows a state where a mold is brought into contact with the resist film, and (e) shows a state where a pattern is formed on the resist film.
- FIG. 3A shows the process of the etching method of the substrate to be processed and the mask layer, (a) shows the substrate to be processed before processing, (b) shows the state in which the mask layer is formed on the substrate to be processed, (c ) Shows a state where a resist film is formed on the mask layer, (d) shows a state where a mold is brought into contact with the resist film, and (e) shows a state where a pattern is formed on the resist film.
- 3B shows a process of the etching method of the substrate to be processed and the mask layer
- (f) shows a state in which the residual film of the resist film is removed
- (g) shows a state in which the resist film is altered
- (h) Indicates a state in which the mask layer is etched using the resist film as a mask
- (i) indicates a state in which the substrate to be processed is etched using the mask layer as a mask.
- the resist film after the alteration is expressed by painting out in the drawing.
- 3C shows the process of the etching method of the substrate to be processed and the mask layer
- (j) shows a state in which the substrate to be processed is further etched using the mask layer as a mask
- (k) shows the mask layer remaining from the substrate to be processed. The removed state is shown
- (l) shows a state in which wet etching is performed on the substrate to be processed.
- a substrate to be processed 100 before processing is prepared. Prior to etching, the substrate to be processed 100 is cleaned with a predetermined cleaning liquid.
- the substrate to be processed 100 is a sapphire substrate.
- a mask layer 110 is formed on the substrate to be processed 100 (mask layer forming step: S1).
- the mask layer 110 has a SiO 2 layer 111 on the substrate to be processed 100 and a Ni layer 112 on the SiO 2 layer 111.
- the thickness of each of the layers 111 and 112 is arbitrary.
- the SiO 2 layer can be 1 nm to 100 nm and the Ni layer 112 can be 1 nm to 100 nm.
- the mask layer 110 may be a single layer.
- the mask layer 110 is formed by a sputtering method, a vacuum evaporation method, a CVD method, or the like.
- a resist film 120 is formed on the mask layer 110 (resist film forming step: S2).
- a thermoplastic resin is used as the resist film 120 and is formed to have a uniform thickness by a spin coating method.
- the resist film 120 is made of, for example, an epoxy resin and has a thickness of, for example, 100 nm or more and 300 nm or less.
- a photo-curable resin that can be cured by ultraviolet rays or the like can be used.
- the resist film 120 is heated and softened together with the substrate to be processed 100, and the resist film 120 is pressed with a mold 130 as shown in FIG. 3A (d).
- An uneven structure 131 is formed on the contact surface of the mold 130, and the resist film 120 is deformed along the uneven structure 131.
- the resist film 120 is cooled and cured together with the substrate to be processed 100 while keeping the pressed state. Then, by separating the mold 200 from the resist film 120, the concavo-convex structure 121 is transferred to the resist film 120 as shown in FIG. 3A (e) (pattern forming step: S3).
- the period of the concavo-convex structure 121 is 1 ⁇ m or less. In the present embodiment, the period of the concavo-convex structure 121 is 500 nm.
- the width of the convex portion 123 of the concavo-convex structure 121 is not less than 100 nm and not more than 300 nm. Moreover, the height of the convex part 123 is 100 nm or more and 300 nm or less. In this state, a residual film 122 is formed in the recess of the resist film 120.
- the substrate to be processed 100 on which the resist film 120 is formed as described above is attached to the substrate holder 2 of the plasma etching apparatus 1. Then, the residual film 122 is removed by, for example, plasma ashing to expose the mask layer 110 that is a workpiece as shown in FIG. 3B (f) (residual film removing step: S4).
- O 2 gas is used as a processing gas for plasma ashing.
- the convex portion 123 of the resist film 120 is also affected by ashing, and the side surface 124 of the convex portion 123 is not perpendicular to the surface of the mask layer 110 but is inclined by a predetermined angle.
- the resist film 120 is exposed to plasma under the condition for alteration, thereby altering the resist film 120 and increasing the etching selectivity (resist alteration step: S5).
- Ar gas is used as a process gas for altering the resist film 120, and Ar gas plasma is induced to the resist film 120 by applying a predetermined bias output.
- the alteration condition is set such that the bias output of the power source 5 is lower than the etching condition described later.
- the mask layer 110 as a workpiece is etched using the resist film 120 that has been exposed to plasma under the etching conditions and has a high etching selectivity as a mask (mask layer etching step: S6).
- Ar gas is used as a processing gas for etching the resist film 120, and a bias output higher than the alteration condition is applied to induce Ar gas plasma to the resist film 120.
- a pattern 113 is formed in the mask layer 110 as shown in FIG.
- the processing gas, the antenna output, the bias output, and the like can be changed as appropriate for the alteration condition and the etching condition, but it is preferable to change the bias output using the same processing gas as in this embodiment.
- the processing gas is Ar gas
- the back pressure is 0.5 Pa
- the Ar gas flow rate is 25 sccm
- the antenna output of the coil 4 is 350 W
- the bias output of the power source 5 is 50 W
- the resist film 120 Curing was observed.
- Etching of the mask layer 110 is performed when the etching gas is Ar gas
- the back pressure is 0.5 Pa
- the Ar gas flow rate is 25 sccm
- the antenna output of the coil 4 is 350 W
- the bias output of the power source 5 is 100 W.
- the resist can be cured even if the antenna output is reduced or the gas flow rate is reduced.
- the substrate to be processed 100 is etched using the mask layer 110 as a mask (etching step of the substrate to be processed: S7).
- etching is performed with the resist film 120 remaining on the mask layer 110.
- plasma etching is performed using a chlorine-based gas such as BCl 3 gas as a processing gas.
- a concavo-convex structure 101 is formed on the substrate 100 to be processed.
- the height of the concavo-convex structure 101 is 500 nm.
- the height of the concavo-convex structure 101 can be larger than 500 nm.
- the etching may be finished with the resist film 120 remaining as shown in FIG. 3B (i). .
- side etching is promoted by the SiO 2 layer 111 of the mask layer 110, and the side surface 103 of the convex portion 102 of the concavo-convex structure 101 is inclined. Further, the state of side etching can also be controlled by the inclination angle of the side surface 123 of the resist film 120. If the mask layer 110 is a single layer of the Ni layer 112, the side surface 103 of the convex portion 102 can be made substantially perpendicular to the main surface.
- the mask layer 110 remaining on the substrate to be processed 100 is removed using a predetermined stripping solution (mask layer removing step: S8).
- the SiO 2 layer 111 is removed by using hydrofluoric acid. Note that even if the resist film 120 remains on the mask layer 110, it can be removed together with the Ni layer 112 with high-temperature nitric acid. However, if the residual amount of the resist film 120 is large, the resist film 120 is previously obtained by O 2 ashing. Is preferably removed.
- the corner of the convex portion 102 is removed by wet etching to form a curved portion (curved portion forming step: S9).
- the etching solution is arbitrary, but for example, a phosphoric acid aqueous solution heated to about 170 ° C., so-called “hot phosphoric acid” can be used.
- this bending part formation process can be abbreviate
- the resist film 120 is exposed to plasma and altered, so that the etching selectivity between the mask layer 110 and the resist film 120 can be increased. Thereby, it becomes easy to process the mask layer 110 with a fine and deep shape, and the mask layer 110 with a fine shape can be formed sufficiently thick.
- the plasma etching apparatus 1 can continuously perform the alteration of the resist film 120 and the etching of the mask layer 110 without significantly increasing the number of steps.
- the resist film 120 is altered and the mask layer 110 is etched by changing the bias output of the power supply 5, and the selectivity of the resist film 120 can be easily increased.
- the substrate to be processed 100 is etched using the sufficiently thick mask layer 110 as a mask, it becomes easy to process the substrate 100 to be processed in a fine and deep shape.
- the formation of the concavo-convex structure 101 having a period of 1 ⁇ m or less and a depth of 300 nm or more forms a resist film on the substrate on which the mask layer is formed, and uses the resist film to form the mask layer
- the etching method that performs etching has been impossible in the past, but is possible with the etching method of the present embodiment.
- the etching method of this embodiment is suitable for forming a concavo-convex structure having a period of 1 ⁇ m or less and a depth of 500 nm or more.
- the nanoscale periodic concavo-convex structure is called moth eye, but when sapphire is processed to sapphire, sapphire is a difficult-to-cut material and can only be processed to a depth of about 200 nm. However, a step of about 200 nm may be insufficient as a moth eye. It can be said that the etching method of this embodiment has solved a novel problem in the case of performing moth-eye processing on a sapphire substrate.
- the mask layer 110 made of SiO 2 / Ni is shown as a workpiece, it goes without saying that the mask layer 110 may be a single Ni layer or other material. In short, the resist may be altered to increase the etching selectivity between the mask layer 110 and the resist film 120.
- the processed substrate 100 may be etched without using the mask layer 110.
- the substrate to be processed 100 becomes a material to be processed, and a resist film 120 is formed on the substrate to be processed 100, and the resist is altered to increase the etching selectivity.
- a sapphire substrate can be etched without using a mask layer by directly forming a resist film on the sapphire substrate.
- the change of the bias output of the plasma etching apparatus 1 is shown as the condition for alteration and the condition for etching.
- the condition for alteration may be a condition in which the resist is altered when the resist is exposed to plasma and the etching selectivity is increased.
- the present invention can be applied to etching of other materials.
- SiC, Si, GaAs, GaN, InP, ZnO or the like can be used as a substrate for etching.
- the mask layer 110 made of SiO 2 / Ni similar to the above embodiment is formed on the SiC substrate, the resist film is cured under the same conditions as the above embodiment, and the SiC substrate can be etched with SF 6 type gas It has been confirmed.
- SF 6 type gas It has been confirmed.
- FIGS. 4A and 4B show a substrate to be processed, where FIG. 4A is a schematic perspective view, and FIG. 4B is a cross-sectional view along AA.
- the processed substrate 100 manufactured through the above-described steps will be described.
- the concavo-convex structure 101 has a plurality of convex portions 102 formed periodically, and a concave portion is formed between the convex portions 102. ing.
- the shape of each convex part 102 is a frustum shape which cut off the upper part of the cone.
- the shape of the convex part 102 can be made into other frustum shapes, such as a polygonal frustum other than a truncated cone shape, and can also be made into weights, such as a cone and a polygonal frustum.
- the concave portion instead of the convex portion 102 may have a shape such as a weight, a frustum, or a frustum.
- the concavo-convex structure 101 is formed in alignment with the intersection of the virtual triangular lattice at a predetermined cycle so that the center of each convex portion 102 is the position of the apex of the regular triangle in plan view.
- each convex portion 102 is 500 nm.
- the period refers to the distance between the height peak positions of adjacent convex portions 102.
- each convex portion 102 has a base end diameter of 200 nm and a height of 600 nm.
- the period, dimension, shape, etc. of each convex part 102 can be changed suitably.
- the light emitting element 200 shown in FIG. 5 can be manufactured by using the substrate 100 to be processed.
- the light emitting element 200 is a face-up type LED, and a group III nitride semiconductor layer is formed on the surface of the substrate 100 to be processed having the concavo-convex structure 101.
- the group III nitride semiconductor layer has a buffer layer 210, an n-type GaN layer 212, a multiple quantum well active layer 214, an electron block layer 216, and a p-type GaN layer 218 in this order from the substrate 100 to be processed.
- a p-side electrode 220 is formed on the p-type GaN layer 218, and an n-side electrode 224 is formed on the n-type GaN layer 212.
- a reflective film 226 is formed on the back surface side of the sapphire substrate 2.
- the reflective film 226 can be composed of, for example, a dielectric multilayer film and an Al layer.
- the buffer layer 210 is made of AlN
- the n-type GaN layer 212 is made of n-GaN
- the multiple quantum well active layer 214 is made of GalnN / GaN.
- the peak wavelength of light emission of the multiple quantum well active layer 214 is 450 nm.
- the electron block layer 216 is composed of p-AIGaN
- the p-type GaN layer 218 is composed of p-GaN.
- the n-type GaN layer 212 to the p-type GaN layer 218 are formed by epitaxial growth of a group III nitride semiconductor, and the concavo-convex structure 101 exists on the substrate 100 to be processed. Is flattened.
- the p-side electrode 220 is made of a transparent material such as ITO (Indium Tin Oxide).
- the n-side electrode 224 is formed on the exposed n-type GaN layer 212 by etching the n-type GaN layer 212 from the p-type GaN layer 218.
- the n-side electrode 224 is made of, for example, Ti / Al / Ti / Au.
- the surface of the reflective film 226 on the substrate 100 side forms the reflective surface 228, and light emitted from the active layer 214 is transmitted through the interface of the concavo-convex structure 101 by diffraction.
- Light is reflected by the reflecting surface 228.
- the light transmitted by the diffractive action is re-incident on the interface, and the light is transmitted again using the diffractive action at the interface, whereby the light can be extracted outside the element in a plurality of modes.
- the period of each convex portion 101 is preferably larger than the optical wavelength of the light emitted from the multiple quantum well active layer 214 and smaller than the coherent length of the light.
- the optical wavelength means a value obtained by dividing the actual wavelength by the refractive index.
- the coherent length corresponds to the distance until the periodic oscillations of the waves cancel each other and the coherence disappears due to differences in individual wavelengths of the photon group having a predetermined spectral width.
- the period of each convex part 102 is preferably larger than twice the optical wavelength of the light emitted from the multiple quantum well active layer 214. Moreover, it is preferable that the period of each convex part 102 is half or less of the coherent length of the light emitted from the multiple quantum well active layer 214.
- the period of each convex portion 102 is 500 nm. Since the wavelength of light emitted from the active layer 214 is 450 nm and the refractive index of the group III nitride semiconductor layer is 2.4, the optical wavelength thereof is 187.5 nm. Further, since the half width of the light emitted from the active layer 214 is 63 nm, the coherent length of the light is 3214 nm. That is, the period of the concavo-convex structure 101 is greater than twice the optical wavelength of the active layer 214 and less than or equal to half the coherent length.
- the to-be-processed substrate 100 which consists of sapphire for the light emitting element 200 was illustrated, the to-be-processed substrate 100 can also be used for another device, and about other specific uses etc. suitably It can be changed.
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Abstract
Description
図1に示すように、プラズマエッチング装置1は、誘導結合型(ICP)であり、被加工基板100を保持する平板状の基板保持台2と、基板保持台2を収容する容器3と、容器3の上方に石英板6を介して設けられたコイル4と、基板保持台2に接続された電源5と、を有している。コイル4は立体渦巻形のコイルであり、コイル中央から高周波電力を供給し、コイル外周の末端が接地されている。エッチング対象の被加工基板100は直接或いは搬送用トレーを介して基板保持台2に載置される。基板保持台2には被加工基板100を冷却するための冷却機構が内蔵されており、冷却制御部7によって制御される。容器3は供給ポートを有し、O2ガス、Arガス等の各種ガスが供給可能となっている。
図2は、エッチング方法を示すフローチャートである。図2に示すように、本実施形態のエッチング方法は、マスク層形成工程S1と、レジスト膜形成工程S2と、パターン形成工程S3と、残膜除去工程S4と、レジスト変質工程S5と、マスク層のエッチング工程S6と、被加工基板のエッチング工程S7と、マスク層除去工程S8と、湾曲部形成工程S9と、を含んでいる。
図3Bは被加工基板及びマスク層のエッチング方法の過程を示し、(f)はレジスト膜の残膜を除去した状態を示し、(g)はレジスト膜を変質させた状態を示し、(h)はレジスト膜をマスクとしてマスク層をエッチングした状態を示し、(i)はマスク層をマスクとして被加工基板をエッチングした状態を示す。尚、変質後のレジスト膜は、図中、塗りつぶすことで表現している。
図3Cは被加工基板及びマスク層のエッチング方法の過程を示し、(j)はマスク層をマスクとして被加工基板をさらにエッチングした状態を示し、(k)は被加工基板から残ったマスク層を除去した状態を示し、(l)は被加工基板にウェットエッチングを施した状態を示す。
前述の工程を経て作製される被加工基板100について説明する。本実施形態においては、図4(a)及び(b)に示すように、凹凸構造101は、周期的に形成された複数の凸部102を有し、各凸部102の間が凹部をなしている。本実施形態においては、各凸部102の形状は、円錘の上部を切り落とした円錘台状である。尚、凸部102の形状は、円錐台状の他、多角錘台等の他の錘台状としたり、円錐、多角錘等の錘状とすることができる。尚、凸部102でなく凹部が、錘状、円錘台、錘台状等の形状をなしていてもよい。本実施形態においては、凹凸構造101は、平面視にて、各凸部102の中心が正三角形の頂点の位置となるように、所定の周期で仮想の三角格子の交点に整列して形成される。
2 基板保持台
3 容器
4 コイル
5 電源
6 石英板
7 冷却制御部
8 プラズマ
100 被加工基板
101 凹凸構造
102 凸部
103 側面
200 発光素子
210 バッファ層
212 n型GaN層
214 多重量子井戸活性層
216 電子ブロック層
218 p型GaN層
220 p側電極
224 n側電極
226 反射膜
228 反射面
Claims (10)
- 被加工材上にレジスト膜を形成するレジスト膜形成工程と、
前記レジスト膜に所定のパターンを形成するパターン形成工程と、
前記パターンが形成された前記レジスト膜を所定の変質用条件にてプラズマに曝し、前記レジスト膜を変質させてエッチング選択比を高くするレジスト変質工程と、
前記被加工材を前記変質用条件と異なるエッチング用条件にてプラズマに曝し、エッチング選択比が高くなった前記レジスト膜をマスクとして前記被加工材のエッチングを行う被加工材のエッチング工程と、
前記被加工材は所定の被加工基板上に形成された基板用マスク層であるとともに前記被加工基板はサファイア基板であり、エッチングされた基板用マスク層をマスクとして、前記サファイア基板のエッチングを行って、前記サファイア基板に1μm以下の周期の凹凸形状を形成する基板のエッチング工程と、を含み、
前記レジスト変質工程にて、プラズマとしてArガスのプラズマを用い、所定のバイアス出力を加えて、Arガスのプラズマを前記基板用マスク層へ誘導し、
前記エッチング工程にて、プラズマとしてArガスのプラズマを用い、前記変質用条件より高いバイアス出力を加えて、Arガスのプラズマを前記基板用マスク層へ誘導するエッチング方法。 - 前記基板のエッチング工程にて、前記サファイア基板に深さ300nm以上の凹凸形状を形成する請求項1に記載のエッチング方法。
- 前記基板のエッチング工程にて、前記サファイア基板に深さ500nm以上の凹凸形状を形成する請求項1に記載のエッチング方法。
- 前記パターン形成工程の後、プラズマアッシングにより前記レジスト膜の残膜を取り除く残膜除去工程を含む請求項1から3のいずれか1項に記載のエッチング方法。
- 前記パターン形成工程にて、モールドで前記レジスト膜をプレスした後、プレス状態を保ったまま前記レジスト膜を硬化させ、前記レジスト膜に前記モールドの凹凸構造を転写する請求項1から4のいずれか1項に記載のエッチング方法。
- 前記基板のエッチング工程にて、前記基板用マスク層上に前記レジスト膜が残った状態で、前記サファイア基板のエッチングを行う請求項1から5のいずれか1項に記載のエッチング方法。
- 前記基板用マスク層は、前記サファイア基板上のSiO2層と、前記SiO2層上のNi層と、を有し、
前記基板のエッチング工程にて、前記SiO2層と、前記Ni層と、前記レジスト膜と、が積層した状態で、前記サファイア基板のエッチングを行う請求項6に記載のエッチング方法。 - 前記基板のエッチング工程の後、所定の剥離液を用いて前記サファイア基板上に残った前記基板用マスク層を除去するマスク層除去工程を含む請求項6または7に記載のエッチング方法。
- 前記マスク層除去工程にて、O2アッシングにより予め前記レジスト膜を除去してから、所定の剥離液を用いて前記サファイア基板上に残った前記基板用マスク層を除去する請求項8に記載のエッチング方法。
- 被加工材上にレジスト膜を形成するレジスト膜形成工程と、
前記レジスト膜に所定のパターンを形成するパターン形成工程と、
前記パターンが形成された前記レジスト膜を所定の変質用条件にてプラズマに曝し、前記レジスト膜を変質させてエッチング選択比を高くするレジスト変質工程と、
前記被加工材を前記変質用条件と異なるエッチング用条件にてプラズマに曝し、エッチング選択比が高くなった前記レジスト膜をマスクとして前記被加工材のエッチングを行う被加工材のエッチング工程と、
前記被加工材は所定の被加工基板上に形成された基板用マスク層であるとともに前記被加工基板はサファイア基板であり、エッチングされた基板用マスク層をマスクとして、前記サファイア基板のエッチングを行って、前記サファイア基板に凹凸形状を形成する基板のエッチング工程と、を含み、
前記レジスト変質工程にて、プラズマとしてArガスのプラズマを用い、所定のバイアス出力を加えて、Arガスのプラズマを前記基板用マスク層へ誘導し、
前記エッチング工程にて、プラズマとしてArガスのプラズマを用い、前記変質用条件より高いバイアス出力を加えて、Arガスのプラズマを前記基板用マスク層へ誘導するエッチング方法。
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014058069A1 (ja) * | 2012-10-12 | 2014-04-17 | エルシード株式会社 | 半導体発光素子及びその製造方法 |
CN105355538A (zh) * | 2014-08-21 | 2016-02-24 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 一种刻蚀方法 |
Families Citing this family (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101447083B1 (ko) | 2013-01-03 | 2014-10-06 | 주식회사 에이앤디코퍼레이션 | 사파이어 기판의 표면 패턴 형성 방법 |
CN104969366A (zh) * | 2013-02-12 | 2015-10-07 | 崇高种子公司 | Led元件及其制造方法 |
WO2014171467A1 (ja) * | 2013-04-16 | 2014-10-23 | エルシード株式会社 | Led素子及びその製造方法 |
JP6177168B2 (ja) * | 2013-05-08 | 2017-08-09 | 旭化成株式会社 | エッチング被加工材及びそれを用いたエッチング方法 |
JP6194515B2 (ja) * | 2014-06-30 | 2017-09-13 | 豊田合成株式会社 | サファイア基板の製造方法およびiii族窒化物半導体発光素子の製造方法 |
US20160013363A1 (en) | 2014-07-08 | 2016-01-14 | Epistar Corporation | Light-emitting element and the manufacturing method thereof |
JP6436694B2 (ja) * | 2014-09-17 | 2018-12-12 | 住友化学株式会社 | 窒化物半導体テンプレートの製造方法 |
US20180011564A1 (en) * | 2016-07-11 | 2018-01-11 | Dell Products, Lp | Display Surface Structure for Enhanced Optical, Thermal, and Touch Performance |
US10304993B1 (en) * | 2018-01-05 | 2019-05-28 | Epistar Corporation | Light-emitting device and method of manufacturing the same |
CN109037029B (zh) * | 2018-06-29 | 2020-09-01 | 山东元旭光电股份有限公司 | 一种蓝宝石等离子刻蚀负载效应的图形修饰方法及系统 |
CN114220893B (zh) * | 2021-12-17 | 2024-04-16 | 北京北方华创微电子装备有限公司 | 蓝宝石衬底的刻蚀方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000221698A (ja) * | 1999-01-29 | 2000-08-11 | Sony Corp | 電子装置の製造方法 |
JP2010074090A (ja) * | 2008-09-22 | 2010-04-02 | Meijo Univ | 発光素子、発光素子用サファイア基板及び発光素子用サファイア基板の製造方法 |
JP2011060916A (ja) * | 2009-09-08 | 2011-03-24 | Tokyo Electron Ltd | 被処理体の処理方法およびコンピュータ読み取り可能な記憶媒体 |
JP2011134800A (ja) | 2009-12-22 | 2011-07-07 | Samco Inc | エッチング方法及びプラズマ処理装置 |
Family Cites Families (21)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4472237A (en) * | 1981-05-22 | 1984-09-18 | At&T Bell Laboratories | Reactive ion etching of tantalum and silicon |
US4554048A (en) * | 1984-10-17 | 1985-11-19 | At&T Bell Laboratories | Anistropic etching |
US4729815A (en) * | 1986-07-21 | 1988-03-08 | Motorola, Inc. | Multiple step trench etching process |
JPH08153714A (ja) * | 1994-09-30 | 1996-06-11 | Sanyo Electric Co Ltd | エッチング方法及び半導体装置の製造方法 |
JPH09213687A (ja) | 1995-11-30 | 1997-08-15 | Fujitsu Ltd | 半導体装置の製造方法 |
JP4055503B2 (ja) * | 2001-07-24 | 2008-03-05 | 日亜化学工業株式会社 | 半導体発光素子 |
JP2003069158A (ja) | 2001-08-29 | 2003-03-07 | Sanyo Electric Co Ltd | 窒化物系半導体レーザ素子の形成方法 |
US6716570B2 (en) * | 2002-05-23 | 2004-04-06 | Institute Of Microelectronics | Low temperature resist trimming process |
AU2003244166A1 (en) | 2002-06-27 | 2004-01-19 | Tokyo Electron Limited | Plasma processing method |
US6923920B2 (en) * | 2002-08-14 | 2005-08-02 | Lam Research Corporation | Method and compositions for hardening photoresist in etching processes |
JP4538209B2 (ja) * | 2003-08-28 | 2010-09-08 | 株式会社日立ハイテクノロジーズ | 半導体装置の製造方法 |
JP2005136106A (ja) | 2003-10-29 | 2005-05-26 | Kyocera Corp | 単結晶サファイア基板とその製造方法及び半導体発光素子 |
JP2005203672A (ja) * | 2004-01-19 | 2005-07-28 | Sony Corp | 半導体装置の製造方法 |
JP2007184390A (ja) | 2006-01-06 | 2007-07-19 | Nippon Telegr & Teleph Corp <Ntt> | 半導体基板のエッチング方法 |
JP2008110895A (ja) | 2006-10-31 | 2008-05-15 | Mitsubishi Cable Ind Ltd | 窒化物半導体結晶の製造方法 |
JP5094535B2 (ja) | 2008-05-07 | 2012-12-12 | 富士フイルム株式会社 | 凹部形成方法、凹凸製品の製造方法、発光素子の製造方法および光学素子の製造方法 |
JP2010062212A (ja) * | 2008-09-01 | 2010-03-18 | Oki Semiconductor Co Ltd | 半導体装置の製造方法 |
US7968401B2 (en) * | 2009-01-26 | 2011-06-28 | Applied Materials, Inc. | Reducing photoresist layer degradation in plasma immersion ion implantation |
US8941136B2 (en) * | 2009-09-07 | 2015-01-27 | El-Seed Corporation | Semiconductor light emitting element |
TWI414647B (zh) * | 2010-09-27 | 2013-11-11 | 私立中原大學 | 製作次微米圖樣化藍寶石基板之方法 |
JP2012169366A (ja) * | 2011-02-10 | 2012-09-06 | Toshiba Corp | 半導体発光装置の製造方法 |
-
2011
- 2011-11-15 JP JP2011249370A patent/JP5142236B1/ja not_active Expired - Fee Related
-
2012
- 2012-11-06 WO PCT/JP2012/078712 patent/WO2013073417A1/ja active Application Filing
- 2012-11-06 CN CN201280055844.5A patent/CN103946960B/zh not_active Expired - Fee Related
- 2012-11-06 US US14/357,185 patent/US9472736B2/en not_active Expired - Fee Related
- 2012-11-06 KR KR1020147013080A patent/KR20140090209A/ko not_active Application Discontinuation
- 2012-11-06 EP EP12850278.8A patent/EP2782120A4/en not_active Withdrawn
- 2012-11-08 TW TW101141478A patent/TWI518776B/zh not_active IP Right Cessation
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2000221698A (ja) * | 1999-01-29 | 2000-08-11 | Sony Corp | 電子装置の製造方法 |
JP2010074090A (ja) * | 2008-09-22 | 2010-04-02 | Meijo Univ | 発光素子、発光素子用サファイア基板及び発光素子用サファイア基板の製造方法 |
JP2011060916A (ja) * | 2009-09-08 | 2011-03-24 | Tokyo Electron Ltd | 被処理体の処理方法およびコンピュータ読み取り可能な記憶媒体 |
JP2011134800A (ja) | 2009-12-22 | 2011-07-07 | Samco Inc | エッチング方法及びプラズマ処理装置 |
Non-Patent Citations (1)
Title |
---|
See also references of EP2782120A4 |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
WO2014058069A1 (ja) * | 2012-10-12 | 2014-04-17 | エルシード株式会社 | 半導体発光素子及びその製造方法 |
CN105355538A (zh) * | 2014-08-21 | 2016-02-24 | 北京北方微电子基地设备工艺研究中心有限责任公司 | 一种刻蚀方法 |
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