WO2013048155A3 - 유도된 자가정렬 공정을 이용한 반도체 소자의 미세패턴 형성 방법 - Google Patents

유도된 자가정렬 공정을 이용한 반도체 소자의 미세패턴 형성 방법 Download PDF

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Publication number
WO2013048155A3
WO2013048155A3 PCT/KR2012/007837 KR2012007837W WO2013048155A3 WO 2013048155 A3 WO2013048155 A3 WO 2013048155A3 KR 2012007837 W KR2012007837 W KR 2012007837W WO 2013048155 A3 WO2013048155 A3 WO 2013048155A3
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WO
WIPO (PCT)
Prior art keywords
forming
self assembly
guide pattern
patterns
fine patterns
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PCT/KR2012/007837
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English (en)
French (fr)
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WO2013048155A2 (ko
Inventor
이정열
장유진
이재우
김재현
Original Assignee
주식회사 동진쎄미켐
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Application filed by 주식회사 동진쎄미켐 filed Critical 주식회사 동진쎄미켐
Priority to US14/346,080 priority Critical patent/US20140287587A1/en
Priority to CN201280047901.5A priority patent/CN103843112A/zh
Publication of WO2013048155A2 publication Critical patent/WO2013048155A2/ko
Publication of WO2013048155A3 publication Critical patent/WO2013048155A3/ko

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00031—Regular or irregular arrays of nanoscale structures, e.g. etch mask layer
    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/0002—Lithographic processes using patterning methods other than those involving the exposure to radiation, e.g. by stamping
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B81—MICROSTRUCTURAL TECHNOLOGY
    • B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00—Manufacture or treatment of microstructural devices or systems
    • B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0147—Film patterning
    • B81C2201/0149—Forming nanoscale microstructures using auto-arranging or self-assembling material

Abstract

가이드 패턴의 벌크 노광 및 경화 과정 없이, 패턴 선폭의 사이즈가 20nm 이하인 패턴을 형성할 수 있는, 반도체 소자의 미세패턴 형성 방법은 (a) 유기반사방지막이 형성된 기판 위에 포토레지스트막을 형성하는 단계; (b) 상기 포토레지스트막을 노광하고, 네가티브 톤 현상액으로 현상하여 가이드 패턴을 형성하는 단계; (c) 상기 가이드 패턴이 형성된 기판 위에 자가정렬 유도층을 형성하는 단계; (d) 현상액을 이용하여 상기 가이드 패턴을 제거하여, 자가정렬 유도층을 형성하는 단계; (e) 상기 가이드 패턴이 제거된 자가정렬 유도층이 코팅된 기판 위에 DSA(directed self assembly) 물질인 블록 공중합체를 코팅하고, 상기 블록 공중합체의 유리전이온도 이상의 온도로 가열하여 자가정렬된 패턴을 형성하는 단계; 및 (f) 자가정렬된 패턴 중, 식각에 대한 저항성이 작은(또는 식각속도가 빠른) 부분을 산소(O2) 플라즈마를 이용하여 선택적으로 식각하여 미세패턴을 형성하는 단계를 포함한다.
PCT/KR2012/007837 2011-09-29 2012-09-27 유도된 자가정렬 공정을 이용한 반도체 소자의 미세패턴 형성 방법 WO2013048155A2 (ko)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US14/346,080 US20140287587A1 (en) 2011-09-29 2012-09-27 Method for Forming Fine Patterns of Semiconductor Device Using Directed Self-Assembly Process
CN201280047901.5A CN103843112A (zh) 2011-09-29 2012-09-27 使用定向自组装技术形成半导体器件精细图案的方法

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
KR10-2011-0098838 2011-09-29
KR1020110098838A KR20130034778A (ko) 2011-09-29 2011-09-29 유도된 자가정렬 공정을 이용한 반도체 소자의 미세패턴 형성 방법

Publications (2)

Publication Number Publication Date
WO2013048155A2 WO2013048155A2 (ko) 2013-04-04
WO2013048155A3 true WO2013048155A3 (ko) 2013-07-04

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Country Status (5)

Country Link
US (1) US20140287587A1 (ko)
KR (1) KR20130034778A (ko)
CN (1) CN103843112A (ko)
TW (1) TW201324615A (ko)
WO (1) WO2013048155A2 (ko)

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Also Published As

Publication number Publication date
CN103843112A (zh) 2014-06-04
KR20130034778A (ko) 2013-04-08
TW201324615A (zh) 2013-06-16
WO2013048155A2 (ko) 2013-04-04
US20140287587A1 (en) 2014-09-25

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