WO2009041306A1 - 半導体装置の製造方法および装置ならびにレジスト材料 - Google Patents

半導体装置の製造方法および装置ならびにレジスト材料 Download PDF

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Publication number
WO2009041306A1
WO2009041306A1 PCT/JP2008/066646 JP2008066646W WO2009041306A1 WO 2009041306 A1 WO2009041306 A1 WO 2009041306A1 JP 2008066646 W JP2008066646 W JP 2008066646W WO 2009041306 A1 WO2009041306 A1 WO 2009041306A1
Authority
WO
WIPO (PCT)
Prior art keywords
resist film
semiconductor device
developer
pattern
resist material
Prior art date
Application number
PCT/JP2008/066646
Other languages
English (en)
French (fr)
Inventor
Toshihiko Tanaka
Original Assignee
Renesas Technology Corp.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Renesas Technology Corp. filed Critical Renesas Technology Corp.
Priority to US12/678,977 priority Critical patent/US20100209855A1/en
Priority to JP2009534285A priority patent/JP5295968B2/ja
Publication of WO2009041306A1 publication Critical patent/WO2009041306A1/ja

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
    • G03F7/26—Processing photosensitive materials; Apparatus therefor
    • G03F7/38—Treatment before imagewise removal, e.g. prebaking
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H01L21/0273—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers characterised by the treatment of photoresist layers
    • H01L21/0274—Photolithographic processes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28123—Lithography-related aspects, e.g. sub-lithography lengths; Isolation-related aspects, e.g. to solve problems arising at the crossing with the side of the device isolation; Planarisation aspects

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)

Abstract

　半導体装置の製造方法は、ウエハＷの上に、現像液撥水性、例えば、現像液との接触角が６５度以上、の材料からなるレジスト膜１０２を形成する工程と、レジスト膜１０２に対して所望のパターンの露光を行う工程と、レジスト膜１０２の表層を酸化処理して表層１０４を親水性化する工程と、レジスト膜１０２に対して現像液を用いて現像処理を行い、レジストパターン１０５を形成する工程とを含む。 　こうした方法によって、マイクロ膨潤によるパターン倒れと、現像不均一性によるパターン寸法のばらつきの両方を解決して、製品の歩留まりを改善することができる。
PCT/JP2008/066646 2007-09-25 2008-09-16 半導体装置の製造方法および装置ならびにレジスト材料 WO2009041306A1 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
US12/678,977 US20100209855A1 (en) 2007-09-25 2008-09-16 Method and apparatus for manufacturing semiconductor device and resist material
JP2009534285A JP5295968B2 (ja) 2007-09-25 2008-09-16 半導体装置の製造方法および装置

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-247125 2007-09-25
JP2007247125 2007-09-25

Publications (1)

Publication Number Publication Date
WO2009041306A1 true WO2009041306A1 (ja) 2009-04-02

Family

ID=40511193

Family Applications (1)

Application Number Title Priority Date Filing Date
PCT/JP2008/066646 WO2009041306A1 (ja) 2007-09-25 2008-09-16 半導体装置の製造方法および装置ならびにレジスト材料

Country Status (4)

Country Link
US (1) US20100209855A1 (ja)
JP (1) JP5295968B2 (ja)
TW (1) TW200921297A (ja)
WO (1) WO2009041306A1 (ja)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011176218A (ja) * 2010-02-25 2011-09-08 Toshiba Corp 基板処理方法、ｅｕｖマスクの製造方法、ｅｕｖマスクおよび半導体装置の製造方法
JP2013046005A (ja) * 2011-08-26 2013-03-04 Renesas Electronics Corp 半導体装置の製造方法
JP2014119496A (ja) * 2012-12-13 2014-06-30 Dainippon Printing Co Ltd レジスト付きフォトマスクブランクス、その製造方法、および、フォトマスクの製造方法

Families Citing this family (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4967004B2 (ja) * 2009-09-14 2012-07-04 東京エレクトロン株式会社 レジスト塗布現像装置およびレジスト塗布現像方法
JP6881120B2 (ja) * 2017-07-19 2021-06-02 東京エレクトロン株式会社 基板処理装置、基板処理方法及び記憶媒体
JP7360053B2 (ja) * 2018-05-23 2023-10-12 セントラル硝子株式会社 パターン膜付き基板の製造方法および含フッ素共重合体
US10615037B2 (en) * 2018-08-17 2020-04-07 International Business Machines Corporation Tone reversal during EUV pattern transfer using surface active layer assisted selective deposition

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04217258A (ja) * 1990-12-18 1992-08-07 Sharp Corp レジストパターンの作製方法及びその装置
JPH09312257A (ja) * 1996-03-18 1997-12-02 Fujitsu Ltd 微細加工方法及び装置
JPH09319097A (ja) * 1996-01-16 1997-12-12 Sumitomo Chem Co Ltd レジストパターンの形成方法
JPH11295903A (ja) * 1998-04-09 1999-10-29 Tokyo Electron Ltd レジストマスクの形成方法
JP2002015971A (ja) * 2000-06-27 2002-01-18 Matsushita Electric Ind Co Ltd パターン形成方法及び半導体装置の製造装置

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2705023B2 (ja) * 1993-11-26 1998-01-26 ウシオ電機株式会社 被処理物の酸化方法
TW260806B (ja) * 1993-11-26 1995-10-21 Ushio Electric Inc
JP2948110B2 (ja) * 1994-09-19 1999-09-13 ウシオ電機株式会社 被処理物体表面または当該表面上の物質を減圧下で酸化する方法
JP3727044B2 (ja) * 1998-11-10 2005-12-14 東京応化工業株式会社 ネガ型レジスト組成物
JP2001015472A (ja) * 1999-06-28 2001-01-19 Hoya Schott Kk 紫外光照射方法及び装置
US6730256B1 (en) * 2000-08-04 2004-05-04 Massachusetts Institute Of Technology Stereolithographic patterning with interlayer surface modifications
US6900001B2 (en) * 2003-01-31 2005-05-31 Applied Materials, Inc. Method for modifying resist images by electron beam exposure
JP3993549B2 (ja) * 2003-09-30 2007-10-17 株式会社東芝 レジストパターン形成方法
US20060008746A1 (en) * 2004-07-07 2006-01-12 Yasunobu Onishi Method for manufacturing semiconductor device
JP4687878B2 (ja) * 2005-05-27 2011-05-25 信越化学工業株式会社 高分子化合物、レジスト材料及びパターン形成方法
US7473749B2 (en) * 2005-06-23 2009-01-06 International Business Machines Corporation Preparation of topcoat compositions and methods of use thereof

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04217258A (ja) * 1990-12-18 1992-08-07 Sharp Corp レジストパターンの作製方法及びその装置
JPH09319097A (ja) * 1996-01-16 1997-12-12 Sumitomo Chem Co Ltd レジストパターンの形成方法
JPH09312257A (ja) * 1996-03-18 1997-12-02 Fujitsu Ltd 微細加工方法及び装置
JPH11295903A (ja) * 1998-04-09 1999-10-29 Tokyo Electron Ltd レジストマスクの形成方法
JP2002015971A (ja) * 2000-06-27 2002-01-18 Matsushita Electric Ind Co Ltd パターン形成方法及び半導体装置の製造装置

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011176218A (ja) * 2010-02-25 2011-09-08 Toshiba Corp 基板処理方法、ｅｕｖマスクの製造方法、ｅｕｖマスクおよび半導体装置の製造方法
JP2013046005A (ja) * 2011-08-26 2013-03-04 Renesas Electronics Corp 半導体装置の製造方法
JP2014119496A (ja) * 2012-12-13 2014-06-30 Dainippon Printing Co Ltd レジスト付きフォトマスクブランクス、その製造方法、および、フォトマスクの製造方法

Also Published As

Publication number Publication date
US20100209855A1 (en) 2010-08-19
JPWO2009041306A1 (ja) 2011-01-27
JP5295968B2 (ja) 2013-09-18
TW200921297A (en) 2009-05-16

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