WO2013023385A1 - 用于锁相环的高速占空比调节和双端转单端电路 - Google Patents

用于锁相环的高速占空比调节和双端转单端电路 Download PDF

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WO2013023385A1
WO2013023385A1 PCT/CN2011/078759 CN2011078759W WO2013023385A1 WO 2013023385 A1 WO2013023385 A1 WO 2013023385A1 CN 2011078759 W CN2011078759 W CN 2011078759W WO 2013023385 A1 WO2013023385 A1 WO 2013023385A1
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circuit
inverter
edge detection
signal
ended
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PCT/CN2011/078759
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English (en)
French (fr)
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王友华
张俊安
付东兵
胡刚毅
刘军
李儒章
陈光炳
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中国电子科技集团公司第二十四研究所
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Priority to US13/522,745 priority Critical patent/US9054681B2/en
Publication of WO2013023385A1 publication Critical patent/WO2013023385A1/zh

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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/01—Shaping pulses
    • H03K5/04—Shaping pulses by increasing duration; by decreasing duration
    • H03K5/06—Shaping pulses by increasing duration; by decreasing duration by the use of delay lines or other analogue delay elements
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/156—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern
    • H03K5/1565—Arrangements in which a continuous pulse train is transformed into a train having a desired pattern the output pulses having a constant duty cycle

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  • the invention relates to a semiconductor device and a phase-locked loop circuit, and more particularly to a duty cycle adjustment and a double-ended to single-ended circuit.
  • the direct application of the circuit is to adjust the voltage-controlled oscillator output waveform duty cycle of the phase-locked loop. And convert the output waveform of the vacuum oscillator from double-ended to single-ended.
  • the duty cycle of the output clock signal of the phase-locked loop voltage controlled oscillator typically deviates by 50%.
  • the output of the phase-locked loop voltage-controlled oscillator is usually a double-ended signal.
  • the double-ended signal is usually converted into a single-ended signal, and the conversion is required by a double-ended to single-ended circuit.
  • the present invention provides a high-speed duty cycle adjustment and a double-ended to single-ended circuit for a phase-locked loop, which has a compact design and a reasonable scheme, and can deviate far from the duty ratio of the input clock signal by 50.
  • the clock signal with a duty ratio of 50% is output; at the same time, the input double-ended signal is converted into a single-ended signal while adjusting the duty ratio of the input signal.
  • two functions of duty cycle adjustment and double-end to differential are completed.
  • the first stage clock input shaping stage includes an input clock shaping circuit I and an input clock shaping circuit II.
  • the input clock shaping circuit I and the input clock shaping circuit II respectively receive clock signals with a phase difference of 180o, and the output has a strong driving capability.
  • the second-stage single-edge detection circuit stage includes a single-edge detection circuit I and a single-edge detection circuit II, and the single-edge detection circuit I and the single-edge detection circuit II respectively receive the input clock shaping circuit I and the input clock shaping circuit II outputs a clock signal and detects a rising or falling edge of the clock signal, and outputs a pulse signal when a rising edge or a falling edge is detected;
  • the third-stage duty-recovery circuit receives the pulse signal with a phase difference of 180o outputted by the single-edge detection circuit I and the single-edge detection circuit II, and outputs a clock signal having the same frequency as the pulse signal and having a duty ratio of 50%.
  • the single edge detecting circuit I and the single edge detecting circuit II adopt a structure of a rising edge detecting circuit, and when detecting a rising edge of the input clock signal, output a low pulse signal;
  • the structure of the rising edge detecting circuit used by the single edge detecting circuit I and/or the single edge detecting circuit II includes
  • a delay unit that receives the clock signal and generates a delayed signal of the clock signal
  • An inverter that receives the delayed clock signal and generates an inverted signal of the delayed signal
  • a NAND gate receives the clock signal and the delayed reverse clock signal and generates a pulse signal.
  • the single edge detection circuit I or / and the single edge detection circuit II can also adopt another rising edge detection circuit structure, including
  • the rising edge triggered D flip-flop receives the clock signal, and the data input terminal is connected to the logic high level VDD;
  • the inverter I is connected to the positive phase output terminal of the D flip-flop, and the output terminal is connected to the asynchronous reset terminal of the D flip-flop;
  • the inverter II is connected with the positive phase output end of the D flip-flop, and the output end is a pulse signal;
  • the single edge detecting circuit I or / and the single edge detecting circuit II may also adopt a structure of a falling edge detecting circuit, and when detecting a falling edge of the input clock signal, output a low pulse signal;
  • the structure of the falling edge detecting circuit used by the single edge detecting circuit I and/or the single edge detecting circuit II includes:
  • a delay unit that receives the clock signal and generates a delayed signal of the clock signal
  • An inverter that receives the delayed clock signal and generates an inverted signal of the delayed signal
  • An OR gate receiving a clock signal and a delayed reverse clock signal and generating a pulse signal
  • the single edge detection circuit I or / and the single edge detection circuit II can also adopt another falling edge detection circuit structure, including
  • the falling edge triggered D flip-flop receives the clock signal, and the data input terminal is connected to the logic high level VDD;
  • the inverter I is connected to the positive phase output terminal of the D flip-flop, and the output terminal is connected to the asynchronous reset terminal of the D flip-flop;
  • the inverter II is connected with the positive phase output end of the D flip-flop, and the output end is a pulse signal;
  • the duty cycle recovery circuit includes
  • the inverter I and the inverter II respectively receive the pulse signals having the large duty ratio output by the single edge detecting circuit I and the single edge detecting circuit II;
  • the inverter III and the inverter IV respectively receive the inverted pulse signals having a large duty ratio output by the inverter 1 and the inverter II;
  • the transmission gate I and the transmission gate II respectively receive the reverse pulse signals output by the inverter I and the inverter II, and generate delayed pulse signals;
  • Transmission gate III and transmission gate IV one of which is controlled by the pulse signal output from the transmission gate I and the reverse pulse signal output from the inverter III, and the other is the pulse signal output from the transmission gate II and the inverse of the inverter IV output. Under the control of the pulse signal, a high level is generated;
  • the inverter V and the inverter VI are connected in series, and the input of the inverter V is coupled to the output of the transmission gate III and the transmission gate IV, and the clock signal is output through the inverter VI.
  • the circuit includes
  • An OR gate that receives an output signal of the inverter
  • An edge trigger that receives the output signal of the OR gate and generates a high and low level.
  • the "pulse signal having a large duty ratio" as described above means that the duty ratio of the pulse signal is greater than 50%.
  • the duty cycle adjustment and double-ended to single-ended circuit of the present invention comprises a first-stage input clock signal shaping stage, a single edge detection stage and a duty cycle recovery circuit, compared with a conventional duty cycle adjustment circuit and a double-ended to differential circuit, It has the following advantages:
  • the clock signal with a duty ratio of 50% can be output when the duty ratio of the input clock signal is far from 50%;
  • the input double-ended signal is converted into a single-ended signal, which reduces the conversion link and the implementation cost compared with the prior art solution;
  • the circuit is simple to implement. Compared with the traditional structure, the standard digital cell library is used to reduce the cost and realize the complexity.
  • the circuit structure is simple, compared with the traditional structure, at the same output frequency, the operating frequency of the voltage controlled oscillator is reduced, and the design difficulty of the voltage controlled oscillator is reduced.
  • Figure 1 is a schematic block diagram of the present invention
  • 10, 11 two single edge detection circuits 20, 21 and a duty cycle recovery circuit 30;
  • FIG. 2(a) is a circuit connection diagram of the first embodiment of the single edge detecting circuit of FIG. 1;
  • Figure 2 (b) is a timing chart of Figure 2 (a);
  • Figure 3 (a) is a circuit connection diagram of the second embodiment of the single edge detecting circuit of Figure 1;
  • Figure 3 (b) is a timing diagram of Figure 3 (a);
  • FIG. 4(a) is a circuit connection diagram of Embodiment 3 of the single edge detecting circuit of FIG. 1;
  • Figure 4 (b) is a timing chart of Figure 4 (a);
  • Figure 5 (a) is a circuit connection diagram of the fourth embodiment of the single edge detecting circuit of Figure 1;
  • Figure 5 (b) is a timing chart of Figure 5 (a);
  • Embodiment 1 is a circuit connection diagram of Embodiment 1 of the duty ratio recovery circuit of FIG. 1;
  • Figure 7 is a timing chart of Figure 6;
  • Embodiment 8 is a circuit connection diagram of Embodiment 2 of the duty cycle recovery circuit of FIG. 1;
  • Figure 9 is a timing chart of Figure 8.
  • Figure 10 is a circuit simulation timing diagram of the present invention.
  • the input to the circuit is a multiphase clock signal CLK 101 and bCLK with phase differences of 180o. 102.
  • the output is a single-ended clock signal CLKOUT 107 with a duty ratio of 50%.
  • the circuit is composed of three parts, the first part is composed of an input clock shaping stage, and the stage includes an input clock shaping circuit I 10 and input clock shaping circuit II 11, the input clock shaping circuit receives the multiphase clocks CLK 101 and bCLK output from the voltage controlled oscillator of the phase locked loop 102 and shape the input multi-phase clock signal to increase its driving capability.
  • the second part consists of single edge detection circuits I 20 and II 21 .
  • Single edge detection circuit I 20 when detecting clock signal SCLK When one edge of 103 (rising or falling), a pulse signal PULSE 105 is output.
  • Single edge detection circuit II 21 when detecting the clock signal bSCLK When one edge of 104 (rising or falling), a pulse signal bPULSE 106 is output. It should be noted that the single edge detection circuit I 20 and the single edge detection circuit II The detection edge of 21 must be uniform, that is, both the rising edge detection and the falling edge detection. Of course, the detection circuit structure used can be different.
  • the third part is the duty cycle recovery circuit 30, which produces a single-ended clock signal CLKOUT 107 with a 50% duty cycle.
  • Multiphase clock signals CLK 101 and bCLK output from a phase-locked loop voltage controlled oscillator 102 has a large rise and fall time.
  • the input clock shaping stages 10, 11 are formed by one or more buffers to increase the drive capability of the input multi-phase clocks CLK 101 and bCLK 102.
  • Single edge detection circuit I 20 and II 21 are connected after the input clock shaping circuits I10 and II11, respectively.
  • the present invention provides four embodiments for the circuit design of the single edge detection circuit. It should be understood that the embodiments are only used to explain the technical solutions of the present invention, and are not intended to be limiting, and The spirit and scope of the technical solutions are intended to be included within the scope of the appended claims.
  • Fig. 2(a) shows a rising edge detecting circuit structure composed of a NAND gate 24, a delay unit 22 and an inverter 23.
  • the delay unit 22 is composed of a buffer chain or an even number of inverters.
  • the input clock signal SCLK103 passes through the delay unit 22 and the inverter 23 to obtain a delayed reverse clock signal D25.
  • the other clock signal SCLK and the delayed reverse clock signal D25 are input to the NAND gate 24 to generate the pulse signal PULSE105.
  • Fig. 2(b) is a timing chart of the rising edge detecting circuit shown in Fig. 2(a).
  • the rising edge detection circuit outputs a low pulse signal PULSE28 when the rising edge of the input clock signal SCLK26 is detected. Since the delay amount ⁇ t of the signal D27 with respect to the input clock SCLK26 is equal to the sum of the delay time of the delay unit 22 and the delay time of the inverter 24. Therefore, the low level time of the pulse PULSE 28 is proportional to the delay time of the delay unit 22 and the inverter 24. Since the delay time of the delay unit and the inverter is small, the rising edge detection circuit outputs a low pulse PULSE 28 having a small width, and its duty ratio is much larger than 50%. The pulse PULSE 28 is supplied to the duty ratio recovery circuit 30.
  • Fig. 3(a) shows a rising edge detection circuit structure, triggered by a rising edge, and a rising edge triggered D flip-flop with asynchronous reset function.
  • 1001 and inverters 1002, 1004 are constructed.
  • Input clock signal SCLK 1003 is coupled to the clock input of D flip-flop 1001.
  • the data input terminal of the D flip-flop 1001 is connected to a logic high level VDD.
  • the positive phase output of the D flip-flop 1001 is output to the inputs of the inverters 1002 and 1004.
  • the output of inverter 1002 is coupled to the asynchronous reset terminal of flip flop 1001.
  • the output of the inverter 1004 is the pulse signal PULSE.
  • Fig. 3(b) is a timing chart of the rising edge detecting circuit shown in Fig. 3(a).
  • the rising edge detection circuit outputs a low pulse signal PULSE when detecting the rising edge of the input clock signal SCLK.
  • the pulse width ⁇ t is equal to the sum of the time delay of the D flip-flop 1001 from the asynchronous reset terminal to the forward output terminal and the time delay of the inverter 1002. Therefore, the pulse PULSE The low time is proportional to the asynchronous reset of the D flip-flop 1001 to the forward output time delay and the delay time of the inverter 1002.
  • the rising edge detection circuit outputs a low pulse PULSE having a small width, and its duty ratio is much larger than 50%.
  • the pulse PULSE is supplied to the duty ratio recovery circuit 30.
  • this implementation is a falling edge detection circuit structure.
  • the falling edge detection circuit is composed of an OR gate 704, a delay unit 702 and an inverter 703.
  • Delay unit 702 can be comprised of a buffer or an even number of inverters.
  • the input clock signal SCLK701 passes through the delay unit 702 and the inverter 703 to obtain a delayed reverse clock signal D705.
  • the other clock signal SCLK and the delayed reverse clock signal D705 are input to the NAND gate 704 to generate a pulse signal PULSE 706.
  • Fig. 4 (b) is a timing chart of the falling edge detecting circuit shown in Fig. 3 (a).
  • the falling edge detection circuit outputs a low pulse signal PULSE when detecting the falling edge of the input clock signal SCLK801. 803. Due to signal D
  • the delay amount ⁇ t of 802 with respect to the input clock SCLK 801 is equal to the sum of the delay time of the delay unit 702 and the delay time of the inverter 703. Therefore, the low level time of the pulse PULSE 803 is proportional to the delay time of the delay unit 702 and the inverter 703. Since the delay time of the delay unit and the inverter is small, the rising edge detection circuit outputs a low pulse PULSE The width of 803 is small and its duty cycle is much greater than 50%.
  • the pulse PULSE 803 is supplied to the duty ratio recovery circuit 30.
  • Fig. 5(a) shows a falling edge detection circuit structure, which is triggered by a falling edge and has a falling edge triggered D flip-flop with asynchronous reset function.
  • 2001 and the reverser 2002, 2004 constitute.
  • Input clock signal SCLK 2003 receives the clock input of the D flip-flop 2001.
  • the data input terminal of the D flip-flop 2001 is connected to a logic high level VDD.
  • the positive phase output of the D flip-flop 2001 is output to the inputs of the inverters 2002 and 2004.
  • the output of the inverter 2002 is connected to the asynchronous reset terminal of the flip-flop 2001.
  • the output of the inverter 2004 is the pulse signal PULSE.
  • Fig. 5(b) is a timing chart of the falling edge detecting circuit shown in Fig. 5(a).
  • the rising edge detecting circuit outputs a low pulse signal PULSE when the rising edge of the input clock signal SCLK is detected.
  • the pulse width ⁇ t is equal to the sum of the time delay of the D flip-flop 2001 from the asynchronous reset terminal to the forward output terminal and the time delay of the inverter 2002. Therefore, the pulse PULSE The low level time is proportional to the asynchronous reset of the D flip-flop 2001 to the forward output time delay and the delay time of the inverter 2002.
  • the rising edge detection circuit outputs a low pulse PULSE having a small width, and its duty ratio is much larger than 50%.
  • the pulse PULSE is supplied to the duty ratio recovery circuit 30.
  • the present invention provides two embodiments for the circuit design of the duty cycle recovery circuit. It should be understood that the embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to be limiting, and the technical solutions of the present invention are modified or equivalently replaced without departing from the embodiments. The spirit and scope of the present invention are intended to be included within the scope of the appended claims.
  • FIG. 6 is a specific embodiment of the duty cycle recovery circuit 30 of FIG.
  • the duty cycle recovery circuit is composed of an inverter I 305 and an inverter II 307, inverter III 306, inverter IV 308, inverter V 309a, inverter VI 309b, transmission gate I 301, transmission gate II 302, transmission gate III 303 and transmission gate IV 304 are formed.
  • the input signal PULSE 311 passes through the inverter I 305 to generate a corresponding complementary control signal PULSE_N 314, and at the same time, the input signal bPULSE 312 passes through inverter II 307 to generate a corresponding complementary control signal bPULSE_N 315.
  • Complementary control signal PULSE_N 314 generates control signal A via inverter III 306 316
  • the complementary control signal bPULSE_N 315 generates a control signal B 317 via the inverter IV 308.
  • Simultaneous transmission of gates III 303 and IV 304 will signal PULSE_N 314 and bPULSE_N 315 are delayed to obtain the control signal, and signal A 316, B 317 collectively controls transmission gates 301 and 302.
  • the inverter V and the inverter VI are connected in series, and the input of the inverter V is coupled to the output of the transmission gate III and the transmission gate IV, and the clock signal is output through the inverter VI.
  • Figure 7 is a timing diagram of the duty cycle recovery circuit of Figure 6.
  • the pulse signal PULSE 311 when the pulse signal PULSE 311 is low, When the pulse signal bPULSE 312 is high, the transmission gate III 301 is turned on. At this time, the voltage value at the X point is equal to the power supply voltage VDD.
  • the parasitic capacitance at the X point can temporarily store the charge. Therefore, the value of the voltage at the X point remains unchanged from the previous state.
  • the pulse signal PULSE 311 is high, the pulse signal bPULSE When 312 is low, the transmission gate IV 302 is turned on, and the voltage value of the X point is low.
  • the phase of the pulse signal bPULSE 314 is behind the pulse signal PULSE
  • the phase of 313 is 180o. Therefore, the duty ratio of the X point voltage is 50%.
  • the inverter V 309a is connected after the X point, and the input of the inverter VI 309b is connected to the output of the inverter V 309a. Inverter V The 309a and VI 309b increase the drive capability of the X-point output signal while shielding the external load.
  • FIG. 8 shows another embodiment of the duty cycle recovery circuit 30 of FIG.
  • the implementation input is a pulse signal PULSE901 and a pulse signal bPULSE902, and the output has a clock signal CLKOUT with a duty ratio of 50%. 908.
  • the duty cycle recovery circuit is comprised of two inverters 903, 904, an OR gate 905 and an edge flip-flop 907 that is triggered by a rising edge of the clock.
  • Input pulse signal PULSE 901 is connected to the input of the inverter 903, and inputs a pulse signal bPULSE 902 is coupled to the input of inverter 904.
  • the outputs of the inverters 903, 904 are connected to the two inputs of the OR gate 905.
  • Output signal CLK_R of OR gate 905 906 is coupled to the clock input of the edge trigger 907 of the rising edge trigger.
  • the data input of the edge trigger 907 triggered by the rising edge is connected to the inverted output of the edge trigger 907.
  • the input pulse signals PULSE and bPULSE pass through the inverter and OR gate to obtain a set of pulse sequences CLK_R.
  • the period of the pulse sequence CLK_R is half of the period of the input clock signal. Therefore, the rising edge triggered edge flip-flop 907 transitions once every half of the input clock cycle state, and the low level time and the high level time of the output clock signal CLKOUT are both half cycles of the input signal. Therefore, the duty ratio of the output clock signal CLKOUT is 50%.
  • Figure 10 is a general timing diagram of the present invention.
  • Fig. 10(a) shows the case where the input duty ratio is 20%.
  • Fig. 10(b) shows the case where the input duty ratio is 50%.
  • Fig. 10(c) shows the case where the input duty ratio is 80%.
  • Input signal SCLK in Figure 10(a) 401 denotes a clock signal output from the voltage controlled oscillator of the phase locked loop, which has a duty ratio of 20%.
  • Output signal CLKOUT 402 represents the output clock waveform after processing by the present invention.
  • Input signal SCLK in Figure 8(b) 403 denotes a clock signal output from the voltage controlled oscillator of the phase locked loop, which has a duty ratio of 50%.
  • Output signal CLKOUT 404 represents the output clock waveform processed by the present invention.
  • Input signal SCLK in Figure 8(c) 405 denotes a clock signal output from the voltage controlled oscillator of the phase locked loop, which has a duty ratio of 80%.
  • Output signal CLKOUT 406 represents the output clock waveform after processing by the present invention.
  • the duty ratio of the input waveform is much larger than 50%, the duty ratio of the output waveform is still 50%.

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Abstract

公开了一种用于锁相环的高速占空比调节和双端转单端电路，包括三个部分：第一级输入波形整形级，第二级单边沿检测电路和第三级占空比恢复电路，该技术方案能够将锁相环压控振荡器的输出双端信号转换成单端信号，同时，该技术方案可以将锁相环压控振荡器输出波形的占空比调节到百分之五十，从而输出单端的，具有占空比为百分之五十的时钟信号。

Description

用于锁相环的高速占空比调节和双端转单端电路 技术领域
本发明涉及半导体器件及锁相环电路，更确切的说是一种占空比调节及双端转单端电路，该电路的直接应用为调节锁相环的压控振荡器输出波形占空比，及将压空振荡器的输出波形由双端转成单端信号。
 背景技术
现代高速大规模集成电路设计对时钟信号的质量越来越敏感。时钟信号质量除了传统的时钟抖动外，时钟占空比越来越成为影响高速集成电路性能的关键因素。而占空比为50％的时钟信号在高速大规模集成电路设计中尤为重要。如高速的模数转换器及双数据率的SDRAM，由于系统利用时钟的上升沿和下降沿，因此占空比为50％的时钟信号对这类系统非常重要。高速动态电路，占空比决定了预充电及评估阶段的时间。占空比对高速动态电路的性能影响非常大。但是，由于器件失配等因素，锁相环压控振荡器输出时钟信号的占空比通常会偏离50％。为了将占空比不为50%的时钟信号校正为占空比为50％的时钟信号，传统的做法通常是将锁相环压控振荡器的输出信号通过分频电路进行二分频。但是这样会使压控振荡器的振荡频率为所需时钟频率的两倍，提高了锁相环的设计难度。
当前，常采用占空比调节电路完成该功能。同时，锁相环压控振荡器的输出通常为双端信号，为了适应单端时钟应用需求，通常将双端信号转换为单端信号，需要采用双端转单端电路实现该转换。
 发明内容
有鉴于此，本发明提供了一种用于锁相环的高速占空比调节和双端转单端电路，其结构设计紧凑，方案合理，能够在输入时钟信号的占空比远远偏离50％的情况下，输出占空比为50％的时钟信号；同时在调节输入信号的占空比同时，将输入的双端信号转换成单端信号。同时完成占空比调节和双端转差分的两个功能。
本发明的目的是通过以下技术方案实现的：
用于锁相环的高速占空比调节和双端转单端电路，包括
第一级时钟输入整形级，该级包括输入时钟整形电路I和输入时钟整形电路II，输入时钟整形电路I和输入时钟整形电路II分别接收相位相差180º的时钟信号，输出具有较强驱动能力的时钟信号；
第二级单边沿检测电路级，该级包括单边沿检测电路I和单边沿检测电路II，所述单边沿检测电路I和单边沿检测电路II分别对应接收输入时钟整形电路I和输入时钟整形电路II输出的时钟信号，并检测时钟信号的上升沿或下降沿，当检测到上升沿或下降沿时，输出脉冲信号；
第三级占空比恢复电路，该电路接收由单边沿检测电路I和单边沿检测电路II输出的相位相差180º的脉冲信号，输出与脉冲信号同频率，占空比为50％的时钟信号。
进一步，所述单边沿检测电路I和单边沿检测电路II采用上升沿检测电路的结构，当检测到输入时钟信号的上升沿时，输出一低脉冲信号；
进一步，所述单边沿检测电路I和/或单边沿检测电路II采用的上升沿检测电路的结构包括
一延迟单元，接收时钟信号，并产生时钟信号的延迟信号；
一反向器，接收延迟的时钟信号，并产生延迟信号的反相信号；
一与非门，接收时钟信号和延迟的反向时钟信号，并产生脉冲信号。
当然，采用上升沿检测电路结构时，单边沿检测电路I或/和单边沿检测电路II还可以采用另一种上升沿检测电路结构，包括
上升沿触发的D触发器，其时钟输入端接收时钟信号，数据输入端接逻辑高电平VDD；
反向器I，与D触发器的正相输出端相联接，输出端连接到D触发器的异步复位端；
反向器II，与D触发器的正相输出端相联接，输出端为脉冲信号；
进一步，所述单边沿检测电路I或/和单边沿检测电路II还可以采用下降沿检测电路的结构，当检测到输入时钟信号的下降沿时，输出一低脉冲信号；
进一步，所述单边沿检测电路I和/或单边沿检测电路II采用的下降沿检测电路的结构包括：
一延迟单元，接收时钟信号，并产生时钟信号的延迟信号；
一反向器，接收延迟的时钟信号，并产生延迟信号的反相信号；
一或门，接收时钟信号和延迟的反向时钟信号，并产生脉冲信号；
当然，采用下降沿检测电路结构时，单边沿检测电路I或/和单边沿检测电路II还可以采用另一种下降沿检测电路结构，包括
下降沿触发的D触发器，其时钟输入端接收时钟信号，数据输入端接逻辑高电平VDD；
反向器I，与D触发器的正相输出端相联接，输出端连接到D触发器的异步复位端；
反向器II，与D触发器的正相输出端相联接，输出端为脉冲信号；
进一步，所述占空比恢复电路包括
反向器I和反向器II，分别接收由单边沿检测电路I和单边沿检测电路II输出的具有大的占空比的脉冲信号；
反向器III和反向器IV，分别接收由反向器I和反向器II输出的反向的具有大的占空比的脉冲信号；
传输门I和传输门II，分别接收由反向器I和反向器II输出的反向脉冲信号，并产生延迟的脉冲信号；
传输门III和传输门IV，其中一个在传输门I输出的脉冲信号和反向器III输出的反向脉冲信号控制下，另外一个在传输门II输出的脉冲信号和反向器IV输出的反向脉冲信号控制下，产生高低电平；
依次串联的反向器V和反向器VI，所述反向器V的输入端联接至传输门III和传输门IV的输出端，通过反向器VI输出时钟信号。
作为占空比恢复电路的另一种构成方式，所述电路包括
两个反向器，接收具有大的占空比的脉冲信号；
一个或门，接收反向器的输出信号；
一个边沿触发器，接收或门的输出信号，产生高低电平。
上述所述的“具有大的占空比的脉冲信号”是指脉冲信号的占空比大于50%。
 有益效果
本发明的占空比调节和双端转单端电路包括一级输入时钟信号整形级，单边沿检测级和占空比恢复电路，与传统占空比调节电路和双端转差分电路相比，它具有以下优点：
1.能够在输入时钟信号的占空比远远偏离50％的情况下，输出占空比为50％的时钟信号；
2.在调节输入信号的占空比同时，将输入的双端信号转换成单端信号，与现有技术方案相比，减少了转换环节和实施成本；
3.电路实现简单，与传统结构相比，采用标准数字单元库，降低了成本及实现复杂度；
4.电路结构简单，与传统结构相比，在相同的输出频率下，降低了压控振荡器的工作频率，降低了压控振荡器的设计难度。
本发明的其他优点、目标和特征在某种程度上将在随后的说明书中进行阐述，并且在某种程度上，基于对下文的考察研究对本领域技术人员而言将是显而易见的，或者可以从本发明的实践中得到教导。本发明的目标和其他优点可以通过下面的说明书和权利要求书来实现和获得。
 附图说明
为了使本发明的目的、技术方案和优点更加清楚，下面将结合附图对本发明作进一步的详细描述，其中：
图1是本发明的原理框图；由两个输入整形级 10，11，两个单边沿检测电路20，21和一占空比恢复电路30构成；
图2(a)是图1中的单边沿检测电路实施例一的电路连接图；
图2(b)是图2(a)的时序图；
图3(a)是图1中的单边沿检测电路实施例二的电路连接图；
图3(b)是图3(a)的时序图；
图4(a)是图1中的单边沿检测电路实施例三的电路连接图；
图4(b)是图4(a)的时序图；
图5(a)是图1中的单边沿检测电路实施例四的电路连接图；
图5(b)是图5(a)的时序图；
图6是本图1中的占空比恢复电路实施例一的电路连接图；
图7是图6的时序图；
图8是图1中的占空比恢复电路实施例二的电路连接图；
图9是图8的时序图；
图10为本发明的电路仿真时序图。
 本发明的实施方式
以下将参照附图，对本发明的优选实施例进行详细的描述。应当理解，优选实施例仅为了说明本发明，而不是为了限制本发明的保护范围。
如图1所示，电路的输入为相位相差180º的多相时钟信号CLK 101和bCLK 102,输出为占空比为50％的单端时钟信号CLKOUT 107。该电路由三部分构成，第一部分由输入时钟整形级构成，该级包括输入时钟整形电路I 10和输入时钟整形电路II 11，输入时钟整形电路接收从锁相环的压控振荡器输出的多相时钟CLK 101和bCLK 102并将输入的多相时钟信号整形，增加其驱动能力。第二部分由单边沿检测电路I 20和II 21组成。单边沿检测电路I 20当检测时钟信号SCLK 103的一个边沿（上升或者下降）时，输出一个脉冲信号PULSE 105。单边沿检测电路II 21当检测时钟信号bSCLK 104的一个边沿（上升或者下降）时，输出一个脉冲信号bPULSE 106。应当指出的是，单边沿检测电路I 20和单边沿检测电路II 21的检测边沿必须是统一的，即同时为上升沿检测或同时为下降沿检测，当然，其采用的检测电路结构可以有差别。
第三部分为占空比恢复电路30，该电路产生占空比为50％的单端时钟信号CLKOUT 107。
从锁相环压控振荡器输出的多相时钟信号CLK 101和bCLK 102具有较大的上升下降时间。通过一个或者多个缓冲器构成输入时钟整形级 10，11增加输入多相时钟CLK 101和bCLK 102的驱动能力。单边沿检测电路I 20和II 21分别接在输入时钟整形电路I10和II11之后。
关于单边沿检测电路的电路设计，本发明提供了四个实施例，应当理解实施例仅用以说明本发明的技术方案而非限制，对本发明的技术方案进行修改或者等同替换，而不脱离本技术方案的宗旨和范围，其均应涵盖在本发明的权利要求范围当中。
单边沿检测电路的实施例一
图2(a)所示，图2(a)为一上升沿检测电路结构，由一个与非门24，一个延迟单元22和一个反向器23构成。延迟单元22由缓冲器链或偶数个反向器构成。输入时钟信号SCLK103一路经过延迟单元22和反向器23得到延迟反向的时钟信号D25。另外一路时钟信号SCLK和延迟反向的时钟信号D25输入到与非门24,产生脉冲信号PULSE105。图2(b)为图2(a)所示的上升沿检测电路的时序图。如时序图2(a)所示，上升沿检测电路当检测到输入时钟信号SCLK26的上升沿时，输出一低脉冲信号PULSE28。由于信号D27相对与输入时钟SCLK26的延迟量∆t等于延迟单元22的延迟时间与反向器24的延迟时间之和。因此，脉冲PULSE28的低电平时间与延迟单元22和反向器24的延迟时间成正比。由于延迟单元和反向器的延迟时间较小，因此，该上升沿检测电路输出低脉冲PULSE28的宽度较小，其占空比远远大于50％。脉冲PULSE28送入占空比恢复电路30。
单边沿检测电路的实施例二
如图3(a)所示，图3(a)为一上升沿检测电路结构，由一个上升沿触发，并且具有异步复位功能的上升沿触发的D触发器 1001和反向器1002，1004构成。输入时钟信号SCLK 1003接到D触发器1001的时钟输入端。D触发器1001的数据输入端接逻辑高电平VDD。D触发器1001的正相输出端输出接到反向器1002和1004的输入端。反向器1002的输出端连接到触发器1001的异步复位端。反向器1004的输出端为脉冲信号PULSE。
图3(b)为图3(a)所示的上升沿检测电路的时序图。如时序图3(b)所示，上升沿检测电路当检测到输入时钟信号SCLK的上升沿时，输出一低脉冲信号PULSE。 由图3(b)知，脉冲宽度∆t等于D触发器1001从异步复位端到正向输出端时间延迟和反相器1002的时间延迟之和。因此，脉冲PULSE 的低电平时间与D触发器1001异步复位到正向输出端时间延迟和反向器1002的延迟时间成正比。由于D触发器1001延迟时间和反向器的延迟时间较小，因此，该上升沿检测电路输出低脉冲PULSE的宽度较小，其占空比远远大于50％。脉冲PULSE送入占空比恢复电路30。
单边沿检测电路的实施例三
如图4(a)所示，该实现方式为下降沿检测电路结构。下降沿检测电路由一个或门704,一个延迟单元702和一个反向器703构成。延迟单元702可以由缓冲器或偶数个反向器构成。输入时钟信号SCLK701一路经过延迟单元702和反向器703得到延迟反向的时钟信号D705。另外一路时钟信号SCLK和延迟反向的时钟信号D705输入到与非门704,产生脉冲信号PULSE706。图4(b)为图3(a)所示的下降沿检测电路的时序图。如时序图4(b)所示，下降沿检测电路当检测到输入时钟信号SCLK801的下降沿时，输出一低脉冲信号PULSE 803。由于信号D 802相对与输入时钟SCLK801的延迟量∆t等于延迟单元702的延迟时间与反向器703的延迟时间之和。因此，脉冲PULSE803的低电平时间与延迟单元702和反向器703的延迟时间成正比。由于延迟单元和反向器的延迟时间较小，因此，该上升沿检测电路输出低脉冲PULSE 803的宽度较小，其占空比远远大于50％。脉冲PULSE 803送入占空比恢复电路30。
单边沿检测电路的实施例四
图5(a)所示，图5(a)为一下降沿检测电路结构，由一个下降沿触发，并且具有异步复位功能的下降沿触发的D触发器 2001和反向器2002，2004构成。输入时钟信号SCLK 2003接到D触发器2001的时钟输入端。D触发器2001的数据输入端接逻辑高电平VDD。D触发器2001的正相输出端输出接到反向器2002和2004的输入端。反向器2002的输出端连接到触发器2001的异步复位端。反向器2004的输出端为脉冲信号PULSE。
图5(b)为图5(a)所示的下降沿检测电路的时序图。如时序图5(b)所示，上升沿检测电路当检测到输入时钟信号SCLK的上升沿时，输出一低脉冲信号PULSE。由图5(b)知，脉冲宽度∆t等于D触发器2001从异步复位端到正向输出端时间延迟和反相器2002的时间延迟之和。因此，脉冲PULSE 的低电平时间与D触发器2001异步复位到正向输出端时间延迟和反向器2002的延迟时间成正比。由于D触发器2001延迟时间和反向器的延迟时间较小，因此，该上升沿检测电路输出低脉冲PULSE的宽度较小，其占空比远远大于50％。脉冲PULSE送入占空比恢复电路30。
关于占空比恢复电路的电路设计，本发明提供了两个实施例，应当理解实施例仅用以说明本发明的技术方案而非限制，对本发明的技术方案进行修改或者等同替换，而不脱离本技术方案的宗旨和范围，其均应涵盖在本发明的权利要求范围当中。
占空比恢复电路实施例一
图6为图1中占空比恢复电路30的一种具体实施例。该占空比恢复电路由反向器I 305、反向器II 307、反向器III 306、反向器IV 308、反向器V 309a、反向器VI 309b、传输门I 301、传输门II 302、传输门III 303和传输门IV 304组成。输入信号PULSE 311经过反向器I 305后生成对应的互补控制信号PULSE_N 314，同时，输入信号bPULSE 312经过反向器II 307后生成对应的互补控制信号bPULSE_N 315。互补控制信号PULSE_N 314经过反向器III 306生成控制信号 A 316，互补控制信号bPULSE_N 315经过反向器IV 308生成控制信号 B 317。同时传输门III 303和IV 304将信号PULSE_N 314及bPULSE_N 315经过延迟得到控制信号，与信号A 316, B 317共同控制传输门301和302。依次串联的反向器V和反向器VI，所述反向器V的输入端联接至传输门III和传输门IV的输出端，通过反向器VI输出时钟信号。
图7所示为图6中占空比恢复电路的时序图。如图所示，当脉冲信号PULSE 311为低, 脉冲信号bPULSE 312为高时，传输门III 301开启。此时，X点的电压值等于电源电压VDD。当脉冲信号PULSE 311和脉冲信号bPULSE 312同时为高电平时，由于X点的寄生电容能够暂时存储电荷。因此，X点的电压保持上一状态的值不发生变化。当脉冲信号PULSE 311为高, 脉冲信号bPULSE 312为低时，传输门IV 302开启，此时X点的电压值为低电平。由于脉冲信号bPULSE 314的相位落后脉冲信号PULSE 313的相位180º。因此，X点电压的占空比为50％。反向器V 309a 接在X点之后，反向器VI 309b的输入端接在反向器V 309a的输出端。反向器V 309a和VI 309b增加了X点出信号的驱动能力，同时，屏蔽了外部负载。
占空比恢复电路实施例二
图8所示为图1中占空比恢复电路30的另外一种实施方式。该实施输入为脉冲信号PULSE901和脉冲信号bPULSE902，输出具有占空比为50％的时钟信号CLKOUT 908。该占空比恢复电路由两个反向器903，904，一个或门905和一个时钟上升沿触发的边沿触发器907构成。输入脉冲信号PULSE 901连接到反向器903的输入端，输入脉冲信号bPULSE 902连接到反向器904的输入端。反向器903，904的输出端连接到或门905的两个输入端。或门905的输出端信号CLK_R 906连接到上升沿触发的边沿触发器907的时钟输入端。上升沿触发的边沿触发器907的数据输入端接在边沿触发907的反向输出端。
图9为图6中占空比恢复电路的时序图。输入脉冲信号PULSE和bPULSE经过反向器和或门，得到一组脉冲序列CLK_R。脉冲序列CLK_R的周期为输入时钟信号周期的一半。因此，上升沿触发的边沿触发器907每半个输入时钟周期状态转换一次，输出时钟信号CLKOUT的低电平时间和高电平时间均为输入信号的半个周期。因此，输出时钟信号CLKOUT的占空比为50％。
图10所示为本发明的总时序图。图10(a)所示为输入占空比为20％的情况。图10(b)所示为输入占空比为50％的情况。图10(c)为输入占空比为80％的情况。图10(a)中输入信号SCLK 401表示从锁相环的压控振荡器输出的时钟信号，该信号占空比为20％。输出信号CLKOUT 402表示经过本发明处理后的输出时钟波形。
从图10(a)中可知，尽管输入波形的占空比远远小于50％，输出波形的占空比仍然为50％。图8(b)中输入信号SCLK 403表示从锁相环的压控振荡器输出的时钟信号，该信号占空比为50％。输出信号CLKOUT 404表示经过本发明处理后的输出时钟波形。图8(c)中输入信号SCLK 405表示从锁相环的压控振荡器输出的时钟信号，该信号占空比为80％。输出信号CLKOUT 406表示经过本发明处理后的输出时钟波形。从图10(c)中可知，尽管输入波形的占空比远远大于50％，输出波形的占空比仍然为50％。
最后说明的是，以上实施例仅用以说明本发明的技术方案而非限制，尽管参照较佳实施例对本发明进行了详细说明，本领域的普通技术人员应当理解，可以对本发明的技术方案进行修改或者等同替换，而不脱离本技术方案的宗旨和范围，其均应涵盖在本发明的权利要求范围当中。

Claims (9)

  1. 用于锁相环的高速占空比调节和双端转单端电路，其特征在于：所述电路包括
    第一级时钟输入整形级，该级包括输入时钟整形电路I和输入时钟整形电路II，输入时钟整形电路I和输入时钟整形电路II分别接收相位相差180º的时钟信号，输出具有较强驱动能力的时钟信号；
    第二级单边沿检测电路级，该级包括单边沿检测电路I和单边沿检测电路II，所述单边沿检测电路I和单边沿检测电路II分别对应接收输入时钟整形电路I和输入时钟整形电路II输出的时钟信号，并检测时钟信号的上升沿或下降沿，当检测到上升沿或下降沿时，输出脉冲信号；
    第三级占空比恢复电路，该电路接收由单边沿检测电路I和单边沿检测电路II输出的相位相差180º的脉冲信号，输出与脉冲信号同频率，占空比为50％的时钟信号。
  2. 根据权利要求1所述的用于锁相环的高速占空比调节和双端转单端电路，其特征在于：所述单边沿检测电路I和单边沿检测电路II均采用上升沿检测电路的结构，当检测到输入时钟信号的上升沿时，输出一低脉冲信号。
  3. 根据权利要求2所述的用于锁相环的高速占空比调节和双端转单端电路，其特征在于：所述单边沿检测电路I和/或单边沿检测电路II采用的上升沿检测电路的结构包括
    一延迟单元，接收时钟信号，并产生时钟信号的延迟信号；
    一反向器，接收延迟的时钟信号，并产生延迟信号的反相信号；
    一与非门，接收时钟信号和延迟的反向时钟信号，并产生脉冲信号。
  4. 根据权利要求2所述的用于锁相环的高速占空比调节和双端转单端电路，其特征在于：所述单边沿检测电路I和/或单边沿检测电路II采用的上升沿检测电路的结构包括
    上升沿触发的D触发器，其时钟输入端接收时钟信号，数据输入端接逻辑高电平VDD；
    反向器I，与D触发器的正相输出端相联接，输出端连接到D触发器的异步复位端；
    反向器II，与D触发器的正相输出端相联接，输出端为脉冲信号。
  5. 根据权利要求1所述的用于锁相环的高速占空比调节和双端转单端电路，其特征在于：所述单边沿检测电路I和单边沿检测电路II采用下降沿检测电路的结构，当检测到输入时钟信号的下降沿时，输出一低脉冲信号。
  6. 根据权利要求5所述的用于锁相环的高速占空比调节和双端转单端电路，其特征在于：所述单边沿检测电路I和/或单边沿检测电路II采用的下降沿检测电路的结构包括
    一延迟单元，接收时钟信号，并产生时钟信号的延迟信号；
    一反向器，接收延迟的时钟信号，并产生延迟信号的反相信号；
    一或门，接收时钟信号和延迟的反向时钟信号，并产生脉冲信号。
  7. 根据权利要求5所述的用于锁相环的高速占空比调节和双端转单端电路，其特征在于：所述单边沿检测电路I和/或单边沿检测电路II采用的下降沿检测电路的结构包括
    下降沿触发的D触发器，其时钟输入端接收时钟信号，数据输入端接逻辑高电平VDD；
    反向器I，与D触发器的正相输出端相联接，输出端连接到D触发器的异步复位端；
    反向器II，与D触发器的正相输出端相联接，输出端为脉冲信号。
  8. 根据权利要求1所述的用于锁相环的高速占空比调节和双端转单端电路，其特征在于：所述占空比恢复电路包括
    反向器I和反向器II，分别接收由单边沿检测电路I和单边沿检测电路II输出的具有大的占空比的脉冲信号；
    反向器III和反向器IV，分别接收由反向器I和反向器II输出的反向的具有大的占空比的脉冲信号；
    传输门I和传输门II，分别接收由反向器I和反向器II输出的反向脉冲信号，并产生延迟的脉冲信号；
    传输门III和传输门IV，其中一个在传输门I输出的脉冲信号和反向器III输出的反向脉冲信号控制下，另外一个在传输门II输出的脉冲信号和反向器IV输出的反向脉冲信号控制下，产生高低电平；
    依次串联的反向器V和反向器VI，所述反向器V的输入端联接至传输门III和传输门IV的输出端，通过反向器VI输出时钟信号。
  9. 根据权利要求1所述的用于锁相环的高速占空比调节和双端转单端电路，其特征在于：所述占空比恢复电路包括
    两个反向器，接收具有大的占空比的脉冲信号；
    一个或门，接收反向器的输出信号；
    一个边沿触发器，接收或门的输出信号，产生占空比为50％的时钟信号。
PCT/CN2011/078759 2011-08-15 2011-08-23 用于锁相环的高速占空比调节和双端转单端电路 WO2013023385A1 (zh)

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