WO2012094784A1 - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
WO2012094784A1
WO2012094784A1 PCT/CN2011/000712 CN2011000712W WO2012094784A1 WO 2012094784 A1 WO2012094784 A1 WO 2012094784A1 CN 2011000712 W CN2011000712 W CN 2011000712W WO 2012094784 A1 WO2012094784 A1 WO 2012094784A1
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semiconductor device
gate
metal silicide
source
metal
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PCT/CN2011/000712
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English (en)
French (fr)
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罗军
赵超
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中国科学院微电子研究所
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Priority to US13/379,120 priority Critical patent/US9012965B2/en
Publication of WO2012094784A1 publication Critical patent/WO2012094784A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/47—Schottky barrier electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66545—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using a dummy, i.e. replacement gate in a process wherein at least a part of the final gate is self aligned to the dummy gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66643—Lateral single gate silicon transistors with source or drain regions formed by a Schottky barrier or a conductor-insulator-semiconductor structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7839—Field effect transistors with field effect produced by an insulated gate with Schottky drain or source contact
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors

Definitions

  • the present invention relates to a semiconductor device and a method of fabricating the same, and, in particular, to a novel semiconductor device structure having an ultra-thin metal silicide source and drain suitable for a back gate process and a method of fabricating the same. Background technique
  • the parasitic series resistance between the source and drain regions of the MOSFET causes the equivalent operating voltage to drop.
  • MOSFETs doped source technology
  • SADS doped source technology
  • Source and drain this metal silicide source-drain MOSFET is also known as a Schottky barrier source-drain MOSFET.
  • the substrate 10 is divided by a shallow trench isolation (STI) 20 into a plurality of active regions including a channel region 14, and a gate structure 40 and a cap layer 50 at the top thereof are formed on the substrate 10.
  • STI shallow trench isolation
  • the substrate 10 on both sides of the sidewall spacers 60 is formed with a metal silicide source/drain region 30, and the source and drain regions 30 directly contact the channel region 14.
  • the substrate 10 may be bulk silicon or silicon-on-insulator (SOI) including the silicon substrate 1 1 , the buried oxide layer 12 and the thin silicon layer 13 , and may be a compound semiconductor material such as SiGe.
  • SOI silicon-on-insulator
  • this Schottky barrier source-drain MOSFET eliminates the need for ion implantation and activation. The process is simple, the contact resistance is small, and the electrical performance is better.
  • the STI 20 between the body silicon substrate 10 and the SOI village bottom (1, 12, and 13) is only an exemplary isolation, not both. Actually adjacent or in contact.
  • the driving ability of a metal silicide source-drain MOSFET is controlled by the Schottky barrier height (SBH) between its source and channel. As the SBH decreases, the drive current increases.
  • SBH Schottky barrier height
  • the results of the device simulation show that the metal silicide source/drain MOSFET can achieve the same driving capability as a conventional MOSFET when the SBH is reduced to approximately O.leV.
  • FIG. 2A a schematic diagram of a method for reducing SBH using silicide as a doping source technique (SADS).
  • SADS silicide as a doping source technique
  • the separation of the condensed dopant ions 70 reduces the SBH between the source and the channel, thereby improving the driving ability of the device; at the same time, the damage of the silicide film caused by ion implantation is also repaired by annealing.
  • This SADS technique requires a silicide film (metal silicide source drain 30) to withstand high temperature annealing without degradation (condensation) due to the need to anneal at high temperatures to separate the doped ions. That is, the silicide film needs to have sufficient heat. stability.
  • the thermal stability of the originally thick metal silicide source/drain film 30 is also deteriorated.
  • the channel 14 becomes shorter, and the metal silicide source/drain film 30 must be correspondingly thinned to better control the short channel effect, but the thinned silicide film 30 is less thermally stable during annealing, and is easy. Aggregation causes a sharp increase in resistivity. Since in the aforementioned SADS method for reducing SBH, the silicide film cannot withstand the high temperature annealing required for the separation of the doping ions at the silicide/silicon interface, so for the current metal silicide source and drain MOSFET, Unable to effectively reduce SBH.
  • the electric field strength excessively causes the oxide layer to break down, and the gate oxide layer is leaked to break the insulation of the gate dielectric layer.
  • a high-k gate dielectric material is used in place of SiO 2 as the gate dielectric layer.
  • high-k gate dielectric materials are not compatible with polysilicon gate processes, so gates are often made of metal-materials.
  • Figure 3 is a schematic diagram of the "back gate” process currently employed to form such high-k gate dielectric materials and metal gate structures.
  • a dummy gate structure (not shown) is formed over the channel region of the substrate 10 having shallow trench isolation (STI) 20, and an isolation spacer 60 is formed around the dummy gate structure, and two spacer spacers 60 are formed.
  • the source and drain regions 30 of the metal silicide are formed on the side, and the structure is covered with the interlayer dielectric layer .80, and the dummy gate structure is removed.
  • the openings left in the layer 80 are sequentially filled with a high-k gate dielectric material 41 and a metal gate 40 to form a final gate structure (a dummy gate is first deposited, and then a metal gate is formed, so this process is called
  • the back gate process typically performing a high temperature anneal after deposition of the high-k gate dielectric material to eliminate defects in the high-k gate dielectric material, is formed in the interlayer dielectric layer 80 corresponding to the source and drain regions 30.
  • the contact hole and the isolation sidewall there is a certain distance between the contact hole and the isolation sidewall, and there is a certain distance between the metal silicide source drain 30 and the gate structure, that is, there is no metal silicide or doping source under the isolation sidewall 60.
  • the drain extension which causes parasitic resistance to increase, these parasitic resistors and capacitors in the MOSFET structure will increase the RC delay time of the device, reducing the switching speed of the device and greatly affecting the performance of this metal silicide source drain MOSFET. Therefore, reducing the parasitic resistance and the parasitic capacitance between the gate and source and drain is the key to reducing the RC delay.
  • the formation of the metal silicide source drain region 30 in the SADS technique is preceded by high temperature annealing (not only high temperature annealing for doping ion separation and condensation, but also annealing for eliminating high-k gate dielectric material defects),
  • high temperature annealing not only high temperature annealing for doping ion separation and condensation, but also annealing for eliminating high-k gate dielectric material defects
  • the integrity of the metal silicide source drain 30 deteriorates during annealing, that is, the metal silicide film may condense, and poor thermal stability makes it impossible to use SADS technology to reduce SBH.
  • the metal silicide source-drain MOSFET fabricated using the back gate process is considered to be a sub--20 nm next-generation CMOS structure, and the existing SADS method for reducing the SBH between the source and channel regions to improve the drive capability is in the trench.
  • the film is shortened and the metal silicide film is thinned, it cannot be performed because it cannot withstand high temperature annealing.
  • the parasitic resistance capacitor increases the RC delay time of the device and reduces the switching speed of the device. Summary of the invention
  • the present invention provides a semiconductor device including a substrate, a channel region in the substrate, source and drain regions on both sides of the channel region, and a gate structure on the channel region.
  • the feature is that the source and drain regions are formed by epitaxially grown metal silicide.
  • a separation condensation region of doped ions is formed between the metal silicide source drain region and the channel region, and an interface between the separated condensation region of the dopant ions and the channel region and the gate
  • the sides of the structure are parallel, for a p-type metal silicide source-drain MOSFET,
  • the impurity ions are any one of boron, aluminum, gallium, and indium, and combinations thereof; for the n-type metal silicide source-drain MOSFET, the dopant ions are nitrogen, phosphorus, arsenic, oxygen, sulfur, selenium, tellurium, fluorine, Any of chlorine and combinations thereof.
  • the thickness of the epitaxially grown metal silicide is less than or equal to 15 nm
  • the material of the epitaxially grown metal silicide is NiSi 2 . y , Ni 1-x Pt x Si 2-y CoSi 2 . y or Ni 1-x Co x Si 2-y , wherein x is greater than 0 and less than 1, and y is greater than or equal to 0 and less than 1.
  • the device further includes an interlayer dielectric layer and a metal contact structure, the interlayer dielectric layer being on the epitaxially grown metal silicide and surrounding the gate structure and directly contacting the gate structure, the metal contact A structure is located in the interlayer dielectric layer and is electrically connected to the epitaxially grown metal silicide, the metal contact structure including a contact hole buried layer and a fill metal layer.
  • the present invention also provides a method of fabricating a semiconductor device, comprising: forming a dummy gate structure on a substrate; depositing a metal layer covering the substrate and the dummy gate structure; performing a first annealing to make a metal layer on both sides of the dummy gate structure reacts with the substrate to form an epitaxially grown metal silicide; and if the unreacted metal layer is stripped, the epitaxially grown metal silicide forms a source and drain of the device a region, the substrate under the dummy gate structure forms a channel region, the metal silicide source and drain regions are in direct contact with the channel region; and the epitaxially grown metal silicide source drain region Injecting dopant ions; and performing a second annealing to form a separation condensation region of dopant ions at an interface of the epitaxially grown metal silicide source drain region and the channel region.
  • the epitaxially grown metal silicide material is NiSi 2-y , Ni 1-x Pt x Si 2-y , Where x is greater than 0 and less than 1, and y is greater than or equal to 0 and less than 1.
  • the dose of the implanted dopant ions is 1 ⁇ 10 14 cm- 2 to 1 ⁇ 10 16 cm- 2
  • the dopant ions are boron, aluminum, gallium, and indium. Any one or a combination thereof; for an n-type metal silicide source-drain MOSFET, the dopant ion is any one of nitrogen, j ⁇ , arsenic-, -oxygen, sulfur, selenium, monosulfide, fluorine, chlorine - and its combination
  • the temperature of the first annealing and/or the second annealing is 500 to 850 °C.
  • the thickness of the metal layer is less than or equal to 5 nm, and the material of the metal layer comprises cobalt, nickel, nickel platinum alloy, nickel cobalt alloy or nickel platinum cobalt ternary alloy.
  • the dummy gate structure is composed of silicon dioxide.
  • the method of fabricating the semiconductor device further includes forming an interlayer dielectric on the epitaxially grown metal silicide and around the dummy gate structure before performing the second annealing a layer, removing the dummy gate structure, depositing a high-k gate dielectric material.
  • a metal gate material is deposited, which together with the high-k gate dielectric material constitutes a gate stack structure.
  • a metal contact structure is formed in the interlayer dielectric layer, and the metal contact structure is electrically connected to the epitaxially grown metal silicide.
  • the metal contact structure comprises a contact hole buried layer and a filling metal layer.
  • the dummy gate structure is removed by wet etching using hydrofluoric acid.
  • the novel MOSFET fabricated according to the present invention there is no need to isolate the sidewall spacer around the gate stack structure, thereby greatly reducing the parasitic capacitance between the gate and the source and drain, and the MOSFET eliminates the high resistance region under the conventional isolation sidewall.
  • the parasitic resistance is reduced, and the reduced parasitic resistance capacitance greatly reduces the RC delay, which greatly improves the switching performance of the MOSFET device.
  • the epitaxially grown ultra-thin metal silicide has good thermal stability and can withstand the high temperature for improving the performance of the high-k gate dielectric material. Annealing further enhances device performance.
  • Figure 1 shows a schematic cross-sectional view of a metal silicide source-drain MOSFET fabricated using prior art
  • Figure 2 shows a schematic cross-sectional view of a doped ion region that is separated by condensation using SADS techniques
  • Figure 3 shows a cross-sectional view of a metal silicide source drain MOSFET fabricated using existing back gate process technology
  • FIGS. 4 through 12 are cross-sectional views showing the steps of fabricating a metal silicide source and drain MOSFET in accordance with the present invention. Having a body - a real one -
  • FIG. 4 is a schematic cross-sectional view of the basic structure.
  • a pad oxide layer (not shown) is deposited on the substrate 100 having a shallow trench isolation (STI) 200, wherein the substrate 100 may be bulk silicon, silicon-on-insulator (SOI), or other compound semiconductor substrate containing silicon.
  • STI shallow trench isolation
  • the pad oxide layer is, for example, silicon oxide, especially silicon dioxide (Si0 2 ).
  • a dummy gate layer 300 is deposited on the pad oxide layer, and the material of the dummy gate layer 300 is an oxide such as silicon dioxide.
  • a cap layer (not shown) is deposited over the dummy gate layer 300, typically of a nitride such as silicon nitride (SiN), a mask layer for later etching.
  • a dummy gate stack structure composed of a pad oxide layer, a dummy gate layer 300, and a cap layer overlap is formed by a conventional photolithography mask etching process. At this time, the doping ions are activated without ion implantation or annealing.
  • a thin layer of metal is deposited.
  • a thin metal layer 400 for forming an epitaxially grown ultra-thin metal silicide is deposited over the entire structure, i.e., the substrate 100, the STI 200, and the dummy gate stack structure.
  • the material of the metal thin layer 400 may be cobalt (Co), nickel (Ni), nickel-platinum alloy (Ni-Pt, wherein the Pt content is 8% or less), and nickel-cobalt alloy (Ni-Co, wherein the Co content is less than or equal to 10%).
  • a nickel-platinum-cobalt ternary alloy having a thickness of less than 5 nm and preferably less than or equal to 4 nm.
  • the metal thin layer 400 may be Co having a thickness of less than 5 nm, Ni having a thickness of less than 4 nm, Ni-Pt having a thickness of 4 nm or less, or Ni-Co having a thickness of 4 nm or less.
  • an epitaxially grown ultra-thin metal silicide is formed by annealing and a thin layer of unreacted metal is stripped. As shown in FIG. 6, the first annealing is performed at 500 to 85 CTC, and the deposited thin metal layer 400 except for the portion of the unreacted metal thin layer 400 leaves ultrathin on both sides of the dummy gate stack structure on the substrate 100.
  • the epitaxially grown ultra-thin metal silicide 500 constitutes a metal silicide source and drain region.
  • the ultra-thin metal silicide 500 is in contact with the channel region under the dummy gate stack structure, specifically, the interface between the metal silicide 500 and the channel region is parallel to the side of the dummy gate stack structure, preferably To be coplanar.
  • the epitaxially formed ultrathin metal silicide 500 may be NiSi 2-y , Ni 1-x Pt x Si 2-y . CoSi 2-y or Ni 1 -x Co x Si 2 depending on the material of the thin metal layer 400. -y , where x is greater than 0 and less than 1, and y is greater than or equal to 0 and less than 1.
  • the epitaxially grown ultra-thin metal silicide 500 has a thickness of 1 to 15 nm.
  • the higher temperature of the second epitaxial process during the epitaxial growth of the ultra-thin metal silicide 500, and the reaction between the thin layer 400 of the thin-film and the substrate 100 In addition to the extrinsic surface states caused by defects in the surface layer of the substrate 100, the pinning effect normally possessed by the self-aligned nickel-based silicide process is suppressed.
  • the material shield and thickness of the metal thin layer 400 are reasonably controlled, and the first annealing at a relatively high temperature is employed, the epitaxially grown ultra-thin metal silicide 500 formed can be subjected to subsequent processes in order to improve the high-k gate dielectric. High temperature second annealing performed for performance.
  • doping ions are implanted into the epitaxially grown ultrathin silicide source and drain regions formed as shown in FIG.
  • Doping ions are implanted into the epitaxially grown ultrathin metal silicide source drain 500 at a dose of 1 X 10 14 cm - 2 to 1 X 10 16 cm" 2 for a p-type epitaxially grown ultrathin metal silicide source-drain MOSFET
  • the doping ions may be boron aluminum Al, gallium Ga, indium In, etc., and combinations thereof.
  • the doping ions may be nitrogen, phosphorus, arsenic, As, oxygen.
  • the interlayer shield layer is deposited and planarized.
  • a thick dielectric material layer is deposited by a conventional process, and the material is preferably a nitride such as silicon nitride.
  • the dielectric material layer is planarized by chemical mechanical polishing (CMP) until the dummy gate layer 300 is exposed, and finally the interlayer dielectric layer 600 is formed.
  • CMP chemical mechanical polishing
  • the dummy gate layer 300 and the pad oxide layer are removed. As shown in FIG. 9, the dummy gate layer 300 and the pad oxide layer are removed by a conventional wet etching process, leaving a gate hole 310 in the interlayer dielectric layer 600.
  • a 5% etching solution of HF may be used.
  • a gate stack structure and a separation condensation region of doped ions are formed.
  • a high-k gate dielectric material layer 700 is deposited in the gate hole 310 and on the interlayer dielectric 600, and a second annealing is performed at a temperature of 500 to 850 ° C to repair the high-k gate dielectric material. Defects in the area to improve reliability.
  • the second annealing not only repairs the high-k gate dielectric material bovine-defect, but also drives the doped ions in the epitaxially grown ultra-thin metal silicide source drain 500 to the silicide/silicon interface Thereby, a separation condensation zone 510 of doped ions is formed, the interface of the separation condensation zone 510 and the channel zone being parallel to the side of the gate stack structure.
  • the interface of the doped ion separation condensation region 510 and the channel region in the substrate 100 is parallel to the interface of the high-k gate dielectric material layer 700 and the interlayer dielectric layer 600, preferably coplanar; or, the doping
  • the separation of the hetero-ions and the interface between the E 510 and the channel region in the substrate 100 can also be parallel to the high-k gate dielectric material layer 700 ⁇
  • the interface of the gate metal layer 800 to be formed is preferably coplanar.
  • a gate metal layer 800 is deposited over the high k gate dielectric material layer 700.
  • the high-k gate dielectric material layer 700 and the gate metal layer 800 form a gate stack structure in which the high-k gate dielectric material layer 700 is located not only under the gate metal layer 800 but also around its sides.
  • the gate stack structure is planarized. As shown in FIG. 11, the gate stack structure is planarized by CMP until the interlayer dielectric layer 600 is exposed.
  • an ultra-thin metal silicide 500 is formed in the interlayer dielectric layer 600 by photolithography and etching to form epitaxial growth, and a thin contact hole is sequentially filled in the contact hole and the interlayer dielectric layer 600.
  • the contact hole buried layer may be made of TiN, Ti, TaN or Ta and a combination thereof to enhance the adhesion between the filled metal layer 900 and the epitaxially grown ultra-thin metal silicide 500 and to block the diffusion of the shield.
  • the material of the filling metal layer 900 can be W, Cu, TiAl or A1 and the combination thereof. The material selection is in accordance with the layout of the overall circuit wiring, and the material with good conductivity is preferred.
  • a novel metal silicide source-drain MOSFET device structure formed in accordance with the above-described fabrication method of the present invention is shown in FIG. a shallow trench isolation (STI) 200 is formed in the substrate 100; a source/drain region 500 of epitaxially grown ultra-thin metal silicide is formed in an active region between the STIs 200 in the substrate 100; a gate formed on the substrate 100 The pole stack structure is located between the source and drain regions 500.
  • STI shallow trench isolation
  • the gate stack structure includes a high-k gate dielectric material layer 700 and a gate metal layer 800, wherein the high-k gate dielectric material layer 700 is not only located under the gate metal layer 800, but also Between the source and drain regions 500 of the epitaxially grown ultra-thin metal silicide and the channel region in the substrate 100, a separation and condensation region 510 of doped ions is formed, and the separation condensation region 510 is parallel to the interface of the channel region.
  • the interface of the doped ion separation condensation region 510 and the channel region in the substrate 100 is parallel to the interface between the high-k gate dielectric material layer 700 and the interlayer dielectric layer 600, preferably Alternatively, the interface between the doped ion separation condensed region 510 and the channel region in the substrate 100 may be parallel to the interface of the high-k gate dielectric material layer 700 and the gate metal layer 800, preferably coplanar ; ultrathin epitaxially grown metal silicide material 500 may be NiSi 2-y ..
  • An interlayer dielectric layer 600 is disposed around the gate stack structure, and the interlayer dielectric layer 600 directly contacts the high-k gate dielectric material layer 700.
  • the metal contact structure penetrates the interlayer dielectric layer 600 and is electrically connected to the epitaxially grown ultra-thin metal silicide 500.
  • the material of the contact hole buried layer may be TiN, Ti, TaN or Ta and a combination thereof, and the material of the filling metal layer 900 may be W, Cu, TiAl or A1 and a combination thereof.
  • a separation condensation region of doped ions is formed between the source and drain regions and the channel region, which can reduce the Schottky barrier height of the ultra-thin metal silicide source-drain MOSFET for short-channel epitaxial growth. .
  • the parasitic resistance capacitance greatly reduces the RC delay, which greatly improves the switching performance of the MOSFET device.
  • the epitaxially grown ultra-thin metal silicide has good thermal stability and can be subjected to high-k gate dielectric material properties and SBH reduction.
  • the high temperature second annealing further enhances the performance of the device.

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Description

半导体器件及其制造方法 本申请要求了 201 1年 1月 13日提交的、申请号为 201 110006429.8、 发明名称为 "半导体器件及其制造方法" 的中国专利申请的优先权， 其全部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件及其制造方法， 特别是涉及一种适用 于后栅工艺的具有超薄金属硅化物源漏的新型半导体器件结构及其制 造方法。 背景技术
IC集成度不断增大需要器件尺寸持续按比例缩小， 然而电器工作 电压有时维持不变， 使得实际 MOS器件内电场强度不断增大。 高电场 带来一系列可靠性问题， 使得器件性能退化。
MOSFET源漏区之间的寄生串联电阻会使得等效工作电压下降。为 了减小接触电阻率以及源漏串联电阻，深亚微米小尺寸 MOSFET常釆用 硅化物作掺杂源极技术（ SADS ) ， 也即通常采用直接与沟道接触的金 属硅化物来作为 MOSFET的源漏，这种金属硅化物源漏 MOSFET也被称 为肖特基势垒源漏 MOSFET。如附图 1所示，衬底 10被浅沟槽隔离（ STI ) 20划分出其中包含有沟道区 14的多个有源区， 栅结构 40及其顶部的盖 层 50形成在衬底 10上， 栅结构 40两侧形成有隔离侧墙 60， 侧墙 60两侧 的衬底 10中形成有金属硅化物的源漏区 30 , 源漏区 30直接接触沟道区 14。 其中， 衬底 10可为体硅， 也可是包含硅衬底 1 1、 埋氧层 12和薄硅 层 13的绝缘体上硅 （ SOI ) , 还可以是例如 SiGe等化合物半导体材料。 与传统的高掺杂源漏的 MOSFET相比， 这种肖特基势垒源漏 MOSFET 无需进行离子注入和激活， 工艺较简单， 接触电阻小， 电学性能更优 越。
值得注意的是， 图 1以及后续附图中， 为了方便示意起见， 体硅村 底 10与 SOI村底 （ 1 1、 12以及 13 ) 之间的 STI 20仅为示意性的隔离， 并 非两者实际相邻或接触。 金属硅化物源漏 MOSFET的驱动能力是由其源极和沟道之间的肖 特基势垒高度（SBH )来控制的。 随着 SBH降低， 驱动电流增大。 器件 模拟的结果显示， 当 SBH降低至约 O.leV时， 金属硅化物源 /漏 MOSFET 可达到与传统 MOSFET相同的驱动能力。
如附图 2所示， 为使用硅化物作掺杂源极技术（ SADS )以降低 SBH 的方法示意图。 首先， 如图 2A所示， 将硼 B、 砷 As等离子注入硅化物 薄膜 30中； 接着， 如图 2B所示， 在 500至 85CTC温度下执行退火以使得 掺杂离子分离凝结在硅化物 /硅界面（也即源漏区 30与薄硅层 13/沟道区 14的界面） 处， 形成激活的分离凝结的掺杂离子区 70， 如图 2B中阴影 部分代表的掺杂离子区 70所示。 该分离凝结的掺杂离子 70降低了源极 和沟道之间的 SBH , 因此而改进了器件的驱动能力； 同时， 离子注入 带来的硅化物薄膜受损也由于退火而得到修复。 由于需要在高温下退 火使得掺杂离子分离凝结， 这种 SADS技术需要硅化物薄膜（金属硅化 物源漏 30 ) 能承受高温退火而不退化 （凝结） ， 也即硅化物薄膜需要 有足够的热稳定性。
但是， 当 MOSFET尺寸不断减小之后，原本较厚的金属硅化物源漏 薄膜 30的热稳定性也会变差。 尺寸缩减后， 沟道 14变短， 金属硅化物 源漏薄膜 30必须也相应变薄以便较好地控制短沟道效应， 但是变薄的 硅化物薄膜 30在退火时热稳定性较差， 容易聚团， 导致电阻率急剧增 大。 由于在前述降低 SBH的 SADS方法中， 硅化物薄膜无法承受为了将 摻杂离子分离凝结在硅化物 /硅界面处而所需的高温退火， 因此， 对于 目前的金属硅化物源漏 MOSFET而言， 无法有效降低 SBH。
此外， 随着 MOSFET尺寸减小， 栅氧化层不断减薄时， 电场强度过 大会引起氧化层击穿， 形成栅极氧化层漏电， 破坏栅介电层的绝缘性。 为了减小栅极泄漏， 采用高 k栅介电材料来替代 Si02作为栅极介电层。 但是， 高 k栅介电材料与多晶硅栅极工艺不兼容， 因此栅极常采用金属- 材料制成。
图 3所示的为目前形成这种高 k栅介电材料与金属栅极结构所采用 的 "后栅" 工艺的示意图。 具有浅沟槽隔离 （ STI ) 20的衬底 10的沟道 区上方形成有虛拟栅极结构 （dummy gate, 未示出） ， 虚拟栅极结构 周围形成有隔离侧墙 60, 隔离侧墙 60两侧形成有金属硅化物的源漏区 30, ^ 结构上覆盖有层间介质层 .80， 去除虚拟栅极结构 , ϋ 间 ^ 质层 80留下的开孔中依次填充高 k栅介电材料 41和金属栅极 40以构成 最终的栅极结构 （先沉积虛拟栅极， 再形成金属栅极， 因此这种工艺 被称为后栅工艺， 通常在沉积高 k栅介电材料之后还要进行一次高温退 火以消除高 k栅介电材料中的缺陷） , 在层间介质层 80中对应于源漏区 30位置刻蚀形成接触孔， 在接触孔中沉积金属的接触部 90。 这种器件 结构中， 接触孔和隔离侧墙之间有一定间距， 金属硅化物源漏 30和栅 极结构之间有一定距离， 也即隔离侧墙 60下方没有金属硅化物也没有 掺杂源漏的延伸区， 这将导致寄生电阻增大， MOSFET结构中这些寄生 的电阻电容会使得器件的 RC延迟时间增大， 降低器件开关速度， 大大 影响这种金属硅化物源漏 MOSFET的性能。 因此， 降低寄生电阻和栅极 与源漏之间的寄生电容是减小 RC延迟的关键。
此外， 由于 SADS技术中金属硅化物源漏区 30的形成是在高温退火 (不仅是使掺杂离子分离凝结的高温退火， 还包括消除高 k栅介电材料 缺陷的退火） 之前， 因此在高温退火时金属硅化物源漏 30的完整性会 恶化， 也即金属硅化物薄膜可能出现凝结， 较差的热稳定性使得无法 使用 SADS技术来降低 SBH。
总而言之，采用后栅工艺制作的金属硅化物源漏 MOSFET被视为亚 20nm下一代 CMOS的结构， 而现有的为了降低源极和沟道区之间 SBH 以提高驱动能力的 SADS方法， 在沟道缩短、 金属硅化物薄膜减薄时因 为无法承受高温退火而不能实施。 此外很重要的一点是， 在传统器件 中， 隔离侧墙下方没有金属硅化物也没有掺杂源漏区的延伸， 因此寄 生电阻电容使得器件的 RC延迟时间增大， 降低器件开关速度。 发明内容
因此， 本发明的其中一个目的是克服以上缺点中的至少一个， 并 提供一种改进的半导体器件及其制造方法。
本发明提供了一种半导体器件， 包括村底、 位于所述衬底中的沟 道区、 位于所述沟道区两侧的源漏区、 位于所述沟道区上的栅极结构， 其特征在于： 由外延生长的金属硅化物构成所述源漏区。
其中， 所述金属硅化物源漏区与所述沟道区之间形成有掺杂离子 的分离凝结区，所述掺杂离子的分离凝结区和所述沟道区的界面与所述 栅极结构的侧面平行, 对于 p型金属硅化物源漏 MOSFET而言， 杂离子为硼、 铝、 镓、 铟的任一种及其组合； 对于 n型金属硅化物源漏 MOSFET, 所述掺杂离子为氮、 磷、 砷、 氧、 硫、 硒、 碲、 氟、 氯的任 一种及其组合。
其中， 所述外延生长的金属硅化物厚度小于等于 15nm， 所述外延 生长的金属硅化物的材质是 NiSi2.y、 Ni1-xPtxSi2-y CoSi2.y或 Ni1-xCoxSi2-y, 其中 x均大于 0小于 1， y均大于等于 0小于 1。
所述器件还包括层间介质层与金属接触结构， 所述层间介质层位 于所述外延生长的金属硅化物上以及所述栅极结构周围且直接接触所 述栅极结构， 所述金属接触结构位于所述层间介质层中且与所述外延 生长的金属硅化物电连接， 所述金属接触结构包括接触孔埋层以及填 充金属层。
本发明还提供了一种半导体器件的制造方法， 包括： 在衬底上形 成虚拟栅极结构； 沉积覆盖所述衬底、 所述虚拟栅极结构的金属层； 执行第一退火， 以使所述虚拟栅极结构两侧的金属层与所述衬底反应 形成外延生长的金属硅化物； 剥除未反应的所述金属层， 则所述外延 生长的金属硅化物形成所述器件的源漏区， 位于所述虚拟栅极结构下 方的所述衬底形成沟道区， 所述金属硅化物源漏区与所述沟道区直接 接触； 向所述外延生长的金属硅化物源漏区内注入掺杂离子； 以及执 行第二退火， 在所述外延生长的金属硅化物源漏区与所述沟道区的界 面处形成掺杂离子的分离凝结区。
其中， 所述外延生长的金属硅化物材质为 NiSi2-y、 Ni1-xPtxSi2-y,
Figure imgf000006_0001
其中 x大于 0小于 1， y大于等于 0小于 1。
其中， 注入掺杂离子的剂量为 1 X 1014cm-2至 1 X 1016cm-2， 对于 p型 金属硅化物源漏 MOSFET而言， 所述掺杂离子为硼、 铝、 镓、 铟的任一 种及其组合； 对于 n型金属硅化物源漏 MOSFET, 所述掺杂离子为氮、 j粦、 砷-、 - 氧、—硫、 硒、一碲、 氟、 氯的任一种 -及其组合
其中， 所述第一退火和 /或所述第二退火的温度为 500至 850°C。 其中，所述金属层的厚度小于等于 5nm,所述金属层的材质包括钴、 镍、 镍铂合金、 镍钴合金或者镍铂钴三元合金。
其中， 所述虚拟栅极结构由二氧化硅构成。
该半导体器件的制造方法还包括， 执行所述第二退火之前， 在所 述外延生长的金属硅化物上以及所述虛拟栅极结构周围形成层间介质 层， 去除所述虚拟栅极结构， 沉积高 k栅介电材料。 执行第二退火之后， 沉积金属栅极材料， 与高 k栅介电材料共同构成栅极堆叠结构。 沉积金 属栅极材料之后， 在所述层间介质层中形成金属接触结构， 金属接触 结构与所述外延生长的金属硅化物电连接。 其中， 所述金属接触结构 包括接触孔埋层以及填充金属层。 其中， 使用氢氟酸湿法刻蚀去除所 述虛拟栅极结构。
依照本发明制造的新型 M O S F E T , 栅极堆叠结构周围无需隔离侧 墙， 因而大大减小了栅极与源漏之间的寄生电容， 并且该 MOSFET消除 了传统隔离侧墙下面的高阻区， 因此减小了寄生电阻， 减小的寄生电 阻电容大大降低了 RC延迟，使得 MOSFET器件开关性能得到大幅提升。 此外， 由于合理选择金属薄层的材质厚度以及第一退火温度，'使得外 延生长的超薄金属硅化物具有良好的热稳定性， 能够经受为了提高高 k 栅介电材料性能进行的高温第二退火， 进一步提升了器件的性能。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1 显示了采用现有技术制作的金属硅化物源漏 MOSFET的剖面 示意图；
图 2 显示了采用 SADS技术形成分离凝结的掺杂离子区的剖面示 意图；
图 3 显示了采用现有后栅工艺技术制作的金属硅化物源漏 MOSFET的剖面示意图； 以及
图 4至 12 显示了依照本发明制作金属硅化物源漏 MOSFET各步骤 的剖面示意图。 具―体 -实一施方一式—
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果， 公开了可有效减小采用后栅工艺制造的金属硅 化物源漏 MOSFET的源漏串联电阻以及栅极和源漏之间的寄生电容的 新型半导体器件结构及其制造方法。 需要指出的是， 类似的附图标记 表示类似的结构， 本申请中所用的术语 "第一" 、 "第二" 、 "上" 、 "下" 等等可用于修饰各种器件结构。 这些修饰除非特别说明并非暗 示所修饰器件结构的空间、 次序或层级关系。
首先， 形成带有虚拟栅极的基础结构。 如图 4所示为基础结构的剖 面示意图。在具有浅沟槽隔离（ STI ) 200的村底 100上沉积垫氧化层（未 示出） ， 其中衬底 100可以是体硅、 绝缘体上硅 （SOI )或者是含硅的 其他化合物半导体村底， 例如 SiGe、 SiC等等， 以及这些物质的组合； 垫氧化层例如是氧化硅， 特别是二氧化硅（Si02 )。 在垫氧化层上沉积 虚拟栅极层 300， 虚拟栅极层 300的材质是氧化物， 例如二氧化硅。 在 虚拟栅极层 300上沉积盖层（未示出） ， 其材质通常是氮化物， 例如氮 化硅（SiN ) ， 用于稍后刻蚀的掩模层。 采用常用的光刻掩模刻蚀工艺 形成由垫氧化层、 虚拟栅极层 300以及盖层重叠构成的虚拟栅极堆叠结 构。 此时， 不进行离子注入也不退火激活掺杂离子。
其次， 沉积金属薄层。 如图 5所示， 在整个结构也即村底 100、 STI 200、 虚拟栅极堆叠结构上沉积用于形成外延生长的超薄金属硅化物的 金属薄层 400。 金属薄层 400的材质可以是钴 （Co ) 、 镍（Ni ) 、 镍铂 合金 （Ni-Pt, 其中 Pt含量小于等于 8 % ) 、 镍钴合金（Ni-Co， 其中 Co 含量小于等于 10 % )或镍铂钴三元合金， 厚度可以小于 5nm并优选地小 于等于 4nm。 具体地， 金属薄层 400可以是厚度小于 5nm的 Co、 厚度小 于等于 4nm的 Ni、 厚度小于等于 4nm的 Ni-Pt或厚度小于等于 4nm的 Ni-Co。
接着， 退火形成外延生长的超薄金属硅化物并剥除未反应的金属 薄层。 如图 6所示，在 500至 85CTC下进行第一退火， 沉积的金属薄层 400 除未反应的金属薄层 400的那部分， 在衬底 100上虚拟栅极堆叠结构两 侧留下超薄的外延生长的超薄金属硅化物 500， 构成金属硅化物源漏 区。 由图中可知， 超薄金属硅化物 500与虚拟栅极堆叠结构下的沟道区 接触， 具体地也即金属硅化物 500与沟道区的界面与虚拟栅极堆叠结构 的侧面平行， 优选地为共面。 外延生成的超薄金属硅化物 500依照金属 薄层 400材质不同而相应的可以是 NiSi2-y、 Ni1-xPtxSi2-y . CoSi2-y或 Ni1 -xCoxSi2-y, 其中 x均大于 0小于 1， y均大于等于 0小于 1。 外延生长的 超薄金属硅化物 500厚度为 1至 15nm。
值得注意的是， 外延生长超薄金属硅化物 500的过程中进行的较高' 温的第 2^火， ^了促 盒属薄层 400与衬底 100中的 Si反应之外，还消_ 除了衬底 100表面层中缺陷导致的非本征表面态， 因此抑制了自对准镍 基硅化物工艺通常具有的钉扎效应 （piping effect ) 。 此外， 由于合理 控制了金属薄层 400的材盾以及厚度， 并采用了较高温的第一退火， 因 此形成的外延生长的超薄金属硅化物 500可以经受后续工艺中为了提 高高 k栅介电性能而进行的高温第二退火。
然后， 向形成的外延生长的超薄硅化物源漏区内注入掺杂离子， 如图 7所示。 向外延生长的超薄金属硅化物源漏 500注入掺杂离子， 剂 量为 1 X 1014cm—2至 1 X 1016cm"2, 对于 p型外延生长的超薄金属硅化物源 漏 MOSFET, 掺杂离子可为硼 铝 Al、 镓 Ga、 铟 In等等及其组合， 对 于 n型外延生长的超薄金属硅化物源漏 MOSFET, 掺杂离子可为氮 ^、 磷？、 砷 As、 氧 0、 硫8、 硒 Se、 碲 Te、 氟？、 氯 C1等等及其组合。 注入 过程会损伤外延生长的超薄金属硅化物源漏， 因此注入能量不宜过大。 注入能量最好是足够低， 以确保大部分注入的掺杂离子被限定在外延 生长的超薄硅化物源漏内。
接着， 沉积并平坦化层间介盾层。 如图 8所示， 采用常用工艺沉积 厚的介质材料层， 材料优选为氮化物， 例如氮化硅。 采用化学机械抛 光（CMP )对介质材料层进行平坦化， 直至露出虛拟栅极层 300, 最终 形成层间介质层 600。
随后， 去除虚拟栅极层 300以及垫氧化层。 如图 9所示， 采用常用 的湿法刻蚀工艺，去除虚拟栅极层 300以及垫氧化层，在层间介质层 600 中留下栅极孔 310。 当垫氧化层和虛拟栅极层 300的材质为二氧化硅时， 可采用浓度为 5 %的 HF刻蚀液。
然后， 形成栅极堆叠结构和掺杂离子的分离凝结区。 如图 10所示， 在栅极孔 310中以及层间介质^ 600上沉积高 k栅介电材料层 700并在 500至 850°C温度下进行第二退火， 以修复高 k栅介电材料中的缺陷从而 改善可靠性。 -值得注意的是, -第二退火不仅修复了高 k栅介电材料牛的- 缺陷， 还将外延生长的超薄金属硅化物源漏 500中的掺杂离子驱赶至硅 化物 /硅界面处， 从而形成掺杂离子的分离凝结区 510, 分离凝结区 510 与沟道区的界面平行于栅极堆叠结构的侧面。 具体地， 该掺杂离子的 分离凝结区 510与衬底 100中沟道区的界面平行于高 k栅介电材料层 700 与层间介质层 600的界面， 优选为共面； 或者， 该摻杂离子的分离凝结 E 510与衬底 100中沟道区的界面也可平行于高 k栅介电材料层 700^ ― 要形成的栅极金属层 800的界面， 优选为共面。 第二高温退火之后， 在 高 k栅介电材料层 700上沉积栅极金属层 800。 高 k栅介电材料层 700和栅 极金属层 800构成栅极堆叠结构， 其中高 k栅介电材料层 700不仅位于栅 极金属层 800下方， 还位于其侧面周围。
接着， 平坦化栅极堆叠结构。 如图 11所示， 采用 CMP平坦化栅极 堆叠结构， 直至露出层间介质层 600。
最后， 形成源漏接触孔。 如图 12所示， 在层间介质层 600中光刻并 刻蚀后形成接触孔直达外延生长的超薄金属硅化物 500, 在接触孔中以 及层间介质层 600上依次填充薄的接触孔埋层 （未示出） 以及厚的填充 金属层 900， CMP平坦化填充金属层 900直至露出层间介质层 600和栅极 金属层 800。 接触孔埋层的材质可为 TiN、 Ti、 TaN或 Ta及其组合， 其作 用是增强填充金属层 900与外延生长的超薄金属硅化物 500之间的粘合 力并阻挡杂盾扩散。 填充金属层 900的材质可为 W、 Cu、 TiAl或 A1及其 组合， 材质选择依照整体电路连线布局的需要， 优先选用导电性能良 好的材料。
依照本发明的如上所述的制造方法形成的新型金属硅化物源漏 MOSFET器件结构如图 12所示。 衬底 100中具有浅沟槽隔离 （ STI ) 200; 衬底 100中 STI 200之间的有源区内形成有外延生长的超薄金属硅化物 的源漏区 500; 衬底 100上形成的栅极堆叠结构位于源漏区 500之间， 栅 极堆叠结构包括高 k栅介电材料层 700和栅极金属层 800, 其中高 k栅介 电材料层 700不仅位于栅极金属层 800下方， 还位于其侧面周围； 外延 生长的超薄金属硅化物的源漏区 500与衬底 100中沟道区之间形成有掺 杂离子的分离凝结区 510， 分离凝结区 510与沟道区的界面平行于栅极 堆叠结构的侧面， 具体地， 该掺杂离子的分离凝结区 510与衬底 100中 沟道区的界面平行于高 k栅介电材料层 700与层间介质层 600的界面， 优 选为共面； 或者， 该掺杂离子的分离凝结区 510与衬底 100中沟道区的 界面也可平行于高 k栅介电材料层 700与栅极金属层 800的界面， 优选为 共面； 外延生长的超薄金属硅化物 500材质可以是 NiSi2-y、 Ni1-xPtxSi2. CoSi2.y或 Ni XCoxSi2-y， 其中 x均大于 0小于 1， y均大于等于 0小于 1 ; 外 延生长的超薄金属硅化物 500上以及栅极堆叠结构周围具有层间介质 层 600， 层间介质层 600直接接触高 k栅介电材料层 700; 金属接触结构 贯穿层间介质层 600 , 与外延生长的超薄金属硅化物 500电连接， 包括 接触孔埋层以及填充金属层 900, 接触孔埋层的材质可为 TiN、 Ti、 TaN 或 Ta及其组合， 填充金属层 900的材质可为 W、 Cu、 TiAl或 A1及其组合。
依照本发明制造的新型 MOSFET，源漏区与沟道区之间形成有掺杂 离子的分离凝结区， 可降低短沟道外延生长的超薄金属硅化物源漏 MOSFET的肖特基势垒高度。栅极堆叠结构周围无需隔离侧墙， 因而大 大减小了栅极与源漏之间的寄生电容， 并且， 由于消除了传统隔离侧 墙下面的高阻区， 因此减小了寄生电阻， 减小的寄生电阻电容大大降 低了 RC延迟， 使得 MOSFET器件开关性能得到大幅提升。 此外， 由于 合理选择金属薄层的材质厚度以及第一退火温度， 使得生成的外延生 长的超薄金属硅化物具有良好的热稳定性， 能够经受为了提高高 k栅介 电材料性能以及降低 SBH进行的高温第二退火， 进一步提升了器件的 性能。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和 等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的 器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种采用后栅工艺制作半导体器件的制造方法， 包括： 在衬底上形成虚拟栅极结构；
沉积覆盖所述衬底、 所述虚拟栅极结构的金属层；
执行第一退火， 以使所述虚拟栅极结构两侧的金属层与所述衬底 反应形成外延生长的金属硅化物；
剥除未反应的所述金属层， 则所述外延生长的金属硅化物形成所 述器件的源漏区， 位于所述虚拟栅极结构下方的所述衬底形成沟道区， 所述源漏区与所述沟道区直接接触；
向所述外延生长的金属硅化物源漏区内注入掺杂离子；
去除所述虚拟栅极结构；
沉积高 k栅介电材料；
, 执行第二退火， 在所述外延生长的金属硅化物源漏区与所述沟道 区的界面处形成掺杂离子的分离凝结区； 以及
沉积金属栅极材料， 所述金属栅极材料和所述高 k栅介电材料构成 栅极堆叠结构。
2. 如权利要求 1所述的半导体器件的制造方法，其中在沉积金属层 之前， 避免了在虚拟栅极两侧形成隔离侧墙。
3. 如权利要求 1所述的半导体器件的制造方法， 其中， 所述外延生 长的金属硅化物材质为 NiSi2.y、 Nii-xPtxSi2.y
Figure imgf000012_0001
其 中 x大于 0小于 1， y大于等于 0小于 1。
4. 如权利要求 1所述的半导体器件的制造方法， 其中， 对于 p型金 属硅化物源漏 MOSFET而言， 所述掺杂离子为硼、 铝、 镓、 铟的任一种 及其组合； 对于 n型金属硅化物源漏 MOSFET, 所述掺杂离子为氮、 磷、 砷、 氧、 硫、 硒、 碲、 -氟、 氯的 -任一种及其组合。
5. 如权利要求 1所述的半导体器件的制造方法， 其中， 所述第一退 火和 /或所述第二退火的温度为 500至 850°C。
6. 如权利要求 1所述的半导体器件的制造方法， 其中， 注入掺杂离 子的注入剂量为 1 X 1014cm-2至 1 X 1016cm"2 。
7. 如权利要求 1所述的半导体器件的制造方法， 其中， 所述沉积的 金属层厚度小于等于 5nm
8. 如权利要求 1所述的半导体器件的制造方法， 其中， 所述沉积的 金属层材盾包括钴、 镍、 镍铂合金、 镍钴合金或者镍铂钴三元合金。
9. 如权利要求 1所述的半导体器件的制造方法， 其中， 所述虚拟栅 - 极结构由氧化物构成。
10. 如权利要求 9所述的半导体器件的制造方法， 其中， 所述氧化 物为二氧化硅。
1 1. 如权利要求 1所述的半导体器件的制造方法， 还包括， 在去除 所述虚拟栅极结构之前， 在所述外延生长的金属硅化物上以及所述虚 拟栅极结构周围形成层间介质层； 沉积所述金属栅极材料之后， 在所 述层间介盾层中形成金属接触结构， 所述金属接触结构与所述外延生 长的金属硅化物电连接。
12. 如权利要求 1 1所述的半导体器件的制造方法， 其中， 所述金属 接触结构包括接触孔埋层以及填充金属层。
13. 如权利要求 1所述的半导体器件的制造方法， 其中， 使用氢氟 酸湿法刻蚀去除所述虚拟栅极结构。
14. 如权利要求 1所述的半导体器件的制造方法， 其中， 所述村底 为体硅衬底或 SOI村底。
15. 一种采用后栅工艺制作的半导体器件， 包括衬底、 位于所述村 底中的沟道区、 位于所述沟道区两侧的源漏区、 位于所述沟道区上的 栅极结构， 其特征在于：
由外延生长的金属硅化物构成所述源漏区， 所述源漏区与所述沟 道区之间形成有掺杂离子的分离凝结区；
所述半导体器件结构消除了隔离侧墙。
16. 如权利要求 15所述的半导体器件， 其中， 所述掺杂离子的分离 凝结区和所述沟道区的界面与所述栅极结构的侧面平行。
17. 如权利要求 15所述的半导体器件， 其中， 所述外延生长的金属- 硅化物厚度小于等于 15nm。
18. 如权利要求 15所述的半导体器件， 其中， 所述外延生长的金属 硅化物的材质是 NiSi2-y、 Ni1-xPtxSi2-y、 （^(^^^或^^。。^^^, 其中 x均 大于 0小于 1 , y均大于等于 0小于 1。
19. 如权利要求 15所述的半导体器件， 其中， 还包括层间介质层与 金属接触结构， 所述层间介质层位于所述外延生长的金属硅化物上以 及所述栅极结构周围且直接接触所述栅极结构， 所述金属接触结构位 于所述层间介质层中且与所述外延生长的金属硅化物电连接， 所述金 属接触结构包括接触孔埋层以及填充金属层。
20. 如权利要求 15所述的半导体器件， 其特征在于， 对于 p型金属 硅化物源漏 MOSFET而言， 所述掺杂离子为硼、 铝、 镓、 铟的任一种及 其组合； 对于 n型金属硅化物源漏 MOSFET, 所述掺杂离子为氮、 磷、 砷、 氧、 硫、 硒、 碲、 氟、 氯的任一种及其组合。
21. 如权利要求 15所述的半导体器件， 其特征在于， 所述村底为 体硅衬底或 SOI衬底。
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Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102593000B (zh) * 2011-01-13 2015-01-14 中国科学院微电子研究所 半导体器件及其制造方法
US8872230B2 (en) * 2011-12-21 2014-10-28 Imec Tunnel field-effect transistor and methods for manufacturing thereof
US9117667B2 (en) * 2012-07-11 2015-08-25 Taiwan Semiconductor Manufacturing Company, Ltd. Carbon layer and method of manufacture
KR101923946B1 (ko) * 2012-08-31 2018-11-30 삼성전자 주식회사 반도체 장치 및 그 제조 방법
US9461143B2 (en) * 2012-09-19 2016-10-04 Intel Corporation Gate contact structure over active gate and method to fabricate same
US9536876B2 (en) * 2013-08-01 2017-01-03 Taiwan Semiconductor Manufacturing Company Ltd. Temperature detector and controlling heat
US20150118833A1 (en) * 2013-10-24 2015-04-30 Applied Materials, Inc. Method of making source/drain contacts by sputtering a doped target
US10593592B2 (en) 2015-01-09 2020-03-17 Applied Materials, Inc. Laminate and core shell formation of silicide nanowire
CN109216192B (zh) * 2017-07-03 2021-10-15 中芯国际集成电路制造(上海)有限公司 半导体器件及其形成方法
CN110571188B (zh) * 2018-06-05 2021-10-01 中芯国际集成电路制造(上海)有限公司 接触插塞、半导体器件及其制造方法
US11228174B1 (en) 2019-05-30 2022-01-18 Silicet, LLC Source and drain enabled conduction triggers and immunity tolerance for integrated circuits
US10892362B1 (en) 2019-11-06 2021-01-12 Silicet, LLC Devices for LDMOS and other MOS transistors with hybrid contact
CN111129126B (zh) * 2019-12-17 2022-09-16 中国科学院微电子研究所 一种肖特基势垒晶体管及其制备方法
US11522053B2 (en) 2020-12-04 2022-12-06 Amplexia, Llc LDMOS with self-aligned body and hybrid source
CN115863396B (zh) * 2023-01-29 2023-05-12 合肥晶合集成电路股份有限公司 一种半导体器件及其制作方法

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6365450B1 (en) * 2001-03-15 2002-04-02 Advanced Micro Devices, Inc. Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate
US7098120B2 (en) * 2003-10-30 2006-08-29 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
CN101207158A (zh) * 2006-12-18 2008-06-25 株式会社东芝 非易失性半导体存储装置及其制造方法
CN101685800A (zh) * 2008-09-26 2010-03-31 台湾积体电路制造股份有限公司 半导体装置的制造方法
CN101847582A (zh) * 2010-04-16 2010-09-29 清华大学 半导体结构的形成方法

Family Cites Families (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5719081A (en) * 1995-11-03 1998-02-17 Motorola, Inc. Fabrication method for a semiconductor device on a semiconductor on insulator substrate using a two stage threshold adjust implant
US7091093B1 (en) * 1999-09-17 2006-08-15 Matsushita Electric Industrial Co., Ltd. Method for fabricating a semiconductor device having a pocket dopant diffused layer
US6657244B1 (en) * 2002-06-28 2003-12-02 International Business Machines Corporation Structure and method to reduce silicon substrate consumption and improve gate sheet resistance during silicide formation
US6645818B1 (en) * 2002-11-13 2003-11-11 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dual-metal gate for N- and P-FETs
WO2005038901A1 (en) * 2003-10-22 2005-04-28 Spinnaker Semiconductor, Inc. Dynamic schottky barrier mosfet device and method of manufacture
US20050272191A1 (en) * 2004-06-03 2005-12-08 Uday Shah Replacement gate process for making a semiconductor device that includes a metal gate electrode
US20060046523A1 (en) * 2004-08-25 2006-03-02 Jack Kavalieros Facilitating removal of sacrificial layers to form replacement metal gates
US7126199B2 (en) * 2004-09-27 2006-10-24 Intel Corporation Multilayer metal gate electrode
US20060091490A1 (en) * 2004-11-03 2006-05-04 Hung-Wei Chen Self-aligned gated p-i-n diode for ultra-fast switching
US7253049B2 (en) * 2004-12-20 2007-08-07 Texas Instruments Incorporated Method for fabricating dual work function metal gates
KR100653711B1 (ko) * 2005-11-14 2006-12-05 삼성전자주식회사 쇼트키 배리어 핀 펫 소자 및 그 제조방법
JP2007165543A (ja) * 2005-12-13 2007-06-28 Toshiba Corp 半導体記憶装置の製造方法
US7812370B2 (en) * 2007-07-25 2010-10-12 Taiwan Semiconductor Manufacturing Company, Ltd. Tunnel field-effect transistor with narrow band-gap channel and strong gate coupling
DE102007046849B4 (de) * 2007-09-29 2014-11-06 Advanced Micro Devices, Inc. Verfahren zur Herstellung von Gateelektrodenstrukturen mit großem ε nach der Transistorherstellung
JP5221112B2 (ja) * 2007-11-29 2013-06-26 株式会社東芝 半導体装置の製造方法および半導体装置
US7893492B2 (en) * 2009-02-17 2011-02-22 International Business Machines Corporation Nanowire mesh device and method of fabricating same
JP2011146465A (ja) * 2010-01-13 2011-07-28 Fujitsu Semiconductor Ltd 半導体装置およびその製造方法
US20110241115A1 (en) * 2010-04-05 2011-10-06 International Business Machines Corporation Schottky Junction Source/Drain FET Fabrication Using Sulfur or Flourine Co-Implantation
US20110248343A1 (en) * 2010-04-07 2011-10-13 International Business Machines Corporation Schottky FET With All Metal Gate
US8415748B2 (en) * 2010-04-23 2013-04-09 International Business Machines Corporation Use of epitaxial Ni silicide
US9029834B2 (en) * 2010-07-06 2015-05-12 International Business Machines Corporation Process for forming a surrounding gate for a nanowire using a sacrificial patternable dielectric
US8420469B2 (en) * 2010-07-12 2013-04-16 International Business Machines Corporation Schottky FET fabricated with gate last process
US20120037991A1 (en) * 2010-08-16 2012-02-16 International Business Machines Corporation Silicon on Insulator Field Effect Device
KR101811316B1 (ko) * 2010-08-20 2017-12-27 삼성전자주식회사 반도체 소자 및 그 제조 방법
US20120088345A1 (en) * 2010-10-12 2012-04-12 Yi-Wei Chen Method of forming silicide for contact plugs
US20120139047A1 (en) * 2010-11-29 2012-06-07 Jun Luo Semiconductor device and method of manufacturing the same
CN102487085B (zh) * 2010-12-01 2014-04-23 中国科学院微电子研究所 半导体器件及其制造方法
CN102593000B (zh) * 2011-01-13 2015-01-14 中国科学院微电子研究所 半导体器件及其制造方法
US8900935B2 (en) * 2011-01-25 2014-12-02 International Business Machines Corporation Deposition on a nanowire using atomic layer deposition

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6365450B1 (en) * 2001-03-15 2002-04-02 Advanced Micro Devices, Inc. Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate
US7098120B2 (en) * 2003-10-30 2006-08-29 Kabushiki Kaisha Toshiba Method of manufacturing semiconductor devices
CN101207158A (zh) * 2006-12-18 2008-06-25 株式会社东芝 非易失性半导体存储装置及其制造方法
CN101685800A (zh) * 2008-09-26 2010-03-31 台湾积体电路制造股份有限公司 半导体装置的制造方法
CN101847582A (zh) * 2010-04-16 2010-09-29 清华大学 半导体结构的形成方法

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