WO2013166630A1 - 半导体器件制造方法 - Google Patents

半导体器件制造方法 Download PDF

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Publication number
WO2013166630A1
WO2013166630A1 PCT/CN2012/000780 CN2012000780W WO2013166630A1 WO 2013166630 A1 WO2013166630 A1 WO 2013166630A1 CN 2012000780 W CN2012000780 W CN 2012000780W WO 2013166630 A1 WO2013166630 A1 WO 2013166630A1
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Prior art keywords
source
semiconductor device
metal layer
metal silicide
metal
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PCT/CN2012/000780
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English (en)
French (fr)
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罗军
邓坚
赵超
李俊峰
陈大鹏
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中国科学院微电子研究所
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Priority to US13/580,963 priority Critical patent/US20130302952A1/en
Publication of WO2013166630A1 publication Critical patent/WO2013166630A1/zh

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H01L21/28017—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon
    • H01L21/28026—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor
    • H01L21/28035—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities
    • H01L21/28044—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer
    • H01L21/28052—Making conductor-insulator-semiconductor electrodes the insulator being formed after the semiconductor body, the semiconductor being silicon characterised by the conductor the final conductor layer next to the insulator being silicon, e.g. polysilicon, with or without impurities the conductor comprising at least another non-silicon conductive layer the conductor comprising a silicide layer formed by the silicidation reaction of silicon with a metal layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
    • H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
    • H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
    • H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
    • H01L21/28518—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising silicides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Definitions

  • the present invention relates to a method of fabricating a semiconductor device, and more particularly to a method of fabricating a semiconductor device that effectively controls lateral extension of metal silicide and reduces source-drain contact resistance.
  • a device structure capable of effectively reducing source-drain resistance is to form a metal silicide in a substrate by a self-aligned silicidation process (SALICIDE), which is usually a corresponding silicide of a nickel-based metal such as Ni, NiPt, NiCo, NiPtCo or the like.
  • the manufacturing method is generally to sputter a nickel-based metal on a gate stack structure and a substrate on both sides of a gate spacer in a device, and then perform rapid thermal annealing at a lower temperature (for example, 450 to 550 ° C) to make a nickel base.
  • the metal reacts with the silicon in the substrate to form a nickel-based metal silicide having a lower sheet resistance, and directly serves as a source and drain region of the device, thereby effectively reducing source-drain contact and parasitic resistance.
  • the nickel-based metal is not only located at the position where the source and drain regions of the substrate are to be formed but also on the gate spacer and the gate stack, and performing rapid thermal annealing during the SALICIDE process described above, the above-mentioned nickel-based metal is not only exposed
  • the substrate reacts, and a portion of it diffuses below the gate spacers, causing the formed nickel-based metal silicide to diffuse laterally, invade below the gate sidewalls, and even into the channel region.
  • the lateral expansion of the nickel-based metal silicide will cause major problems, such as increased gate leakage current, reduced device reliability, possible source-drain junction short-circuit, and gate.
  • the control of the channel region is weakened, eventually causing device failure.
  • the SOI top Si layer is thinner, The low Si content may make the lateral diffusion of metal silicide more serious.
  • One solution to this lateral diffusion problem is to use a two-step annealing process. Specifically, a nickel-based metal layer is deposited on the gate stack structure and the substrate on both sides of the gate spacer and on both sides, and a lower temperature anneal is performed, for example, about 300 ° C, so that the nickel-based metal layer and the lining The Si in the bottom reacts to form a nickel-rich phase metal silicide. Since the first annealing temperature is sufficiently low, the diffusion of the Ni-based metal is inhibited, so that the nickel-rich phase metal silicide formed by the reaction is less extended below the gate sidewall. It will not protrude into the channel region.
  • a second annealing is performed to convert the nickel-rich phase metal silicide into a nickel-based metal silicide having a lower electrical resistance.
  • a second annealing at a higher temperature, for example, 450 to 500 ° C, is performed to convert the nickel-rich phase metal silicide into a nickel-based metal silicide having a lower electrical resistance.
  • an object of the present invention is to provide a method of fabricating a semiconductor device which can effectively suppress lateral extension of a metal silicide.
  • the present invention provides a method of fabricating a semiconductor device, comprising the steps of: forming a gate stack structure on a substrate; forming source and drain regions and gate spacers on both sides of the gate stack structure; Forming a first metal layer; performing a first annealing, causing the first metal layer to react with the source and drain regions, epitaxially growing to form a first metal silicide; depositing a second metal layer on the first metal silicide; performing a second annealing, The second metal layer is caused to react with the first metal silicide and the source and drain regions to form a second metal silicide.
  • the gate spacers include oxides, nitrides, and combinations thereof.
  • the step of forming the source and drain regions and the gate spacer further includes: performing a first source/drain ion implantation using the gate stack structure as a mask, and forming a lightly doped source in the substrate on both sides of the gate stack structure a drain extension region; forming a gate spacer on the substrate on both sides of the gate stack structure; performing a second source/drain ion implantation on the gate sidewall as a mask, forming a substrate on both sides of the gate sidewall Heavy doping source and drain regions; annealing, activation of dopant ions.
  • the substrate includes bulk Si, SOL
  • the first metal layer and/or the second metal layer is a nickel-based metal layer, including Ni, Ni-Pt, Ni-Co, Ni-Pt-Co.
  • the total content of non-Ni elements in the first metal layer is less than or equal to 10
  • the first metal layer has a thickness of 0.5 to 5 nm.
  • the second metal layer has a thickness of 1 to 100 nm.
  • the first metal silicide has a thickness of 1 to 9 nm.
  • the first metal silicide comprises NiSi 2 _ y , NiPtSi 2 - y , NiCoSi 2-y ,
  • NiPtCoSi 2 . y where 0 y ⁇ l.
  • the second metal silicide comprises NiSi, NiPtSi, NiCoSi, NiPtCoSi. According to the semiconductor device manufacturing method of the present invention, by epitaxially growing an ultra-thin metal silicide on the source and drain regions, grain boundaries between silicide grains are reduced or eliminated, and metal diffusion speed and direction are limited, thereby suppressing The lateral growth of the metal silicide further enhances the performance of the device.
  • 1 to 5 are cross-sectional views of respective steps of a method of fabricating a semiconductor device in accordance with the present invention
  • Figure 6 is a flow chart of a method of fabricating a semiconductor device in accordance with the present invention. detailed description
  • a basic MOSFET structure is formed, that is, a gate stack structure 3 is formed on the substrate 1, and source and drain regions 4 are formed in the substrate 1 on both sides of the gate stack structure 3, in the gate stack structure.
  • a substrate 1 is provided, which is a silicon-containing material such as bulk silicon (Si), silicon-on-insulator (SOI), SiGe, Si:, strained silicon, silicon nanotubes, etc., preferably using bulk Si or SOI.
  • An active region isolation 2 is formed in the substrate 1, for example, etching to form a shallow trench and then filling an insulating material such as silicon oxide to form a shallow trench isolation (STI) 2.
  • STI shallow trench isolation
  • a gate insulating layer 3A, a gate filling layer 3B, a gate cap layer 3C, and an etch are sequentially formed on the substrate 1 in the active region by conventional methods such as LPCVD, PECVD, HDPCVD, ALD, MBE, MOCVD, sputtering, or the like.
  • a gate stack structure 3 is formed.
  • the gate stack structure 3 is retained in a subsequent process, so the gate insulating layer 3 A is a silicon oxide or a high-k material, and the high-k material includes, but is not limited to, a nitride (eg, SiN, A1N, TiN), Metal oxides (mainly sub-group and lanthanide metal element oxides, such as A1 2 0 3 , Ta 2 0 5 , Ti0 2 , ZnO, Zr0 2 , Hf0 2 , Ce0 2 , Y 2 0 3 ), perovskites Phase oxide (PZT), Ba x Sn.
  • a nitride eg, SiN, A1N, TiN
  • Metal oxides mainly sub-group and lanthanide metal element oxides, such as A1 2 0 3 , Ta 2 0 5 , Ti0 2 , ZnO, Zr0 2 , Hf0 2 , Ce0 2 , Y 2 0 3
  • PZT Phase oxide
  • the gate filling layer 3B includes doped polysilicon, a metal, a metal alloy, and a metal nitride, wherein the metal includes, for example, W, Cu, Mo, Ti, Al, Ta;
  • the gate cap layer 3C is, for example, silicon nitride for protecting the gate stack structure.
  • the gate stack structure 3 is a dummy gate stack structure, which needs to be etched and then refilled after forming the source and drain regions, so the gate insulating layer 3A is silicon oxide, and the gate filling layer 3B is polysilicon.
  • Microcrystalline silicon, amorphous silicon, and the gate cap layer 3C are still silicon nitride.
  • lightly doped source-drain extension regions 4 A are formed in the substrate 1 on both sides of the gate stack structure 3.
  • An insulating medium is deposited on the gate stack structure 3 and etched to form a gate spacer 5 made of an oxide, a nitride, and a combination thereof, such as silicon nitride, silicon oxynitride, diamond-like amorphous carbon (DLC). ), high stress metal oxides (stress greater than lGPa) and combinations thereof.
  • the gate spacer 5 may be a single layer or a laminate of the above materials, such as an oxide-nitride-oxide ONO structure or a nitride-dLC laminate structure.
  • a high-dose and high-energy second source-drain ion implantation is performed, and a heavily doped source-drain region 4B is formed in the substrate 1 on both sides of the gate spacer 5.
  • the type and concentration of the two ion implantations are appropriately set according to the conductivity type of the device, and annealing is performed after ion implantation to activate the dopant ions, and the annealing temperature and time are determined according to the doping concentration and depth.
  • a first metal layer 6 is formed over the entire device by a conventional method such as PECVD, MOCVD, sputtering, covering the STI 2, the source and drain regions 4, and the gate stack structure 3.
  • the first metal layer 6 is made of a nickel-based metal, and includes, for example, Ni, Ni-Pt, Ni-Co, Ni-Pt-Co, preferably wherein the total content of non-Ni elements (Pt and/or Co) is 10% or less (molar ratio).
  • the thickness of the first metal layer 6 is extremely thin so that the first metal silicide formed by epitaxial growth after annealing is sufficiently thin, substantially no or very few grain boundaries.
  • the thickness of the first metal layer 6 is, for example, only 0.5 to 5 nm.
  • the first annealing is performed such that the first metal layer 6 reacts with Si in the source and drain regions 4 (specifically, the heavily doped source and drain regions 4B) to form the first metal silicide 7.
  • the first annealing is, for example, annealing at 450 to 500 30 for 30 s, so that the ultrathin first metal layer 6 reacts with Si in the heavily doped source and drain regions 4B, and epitaxially grown to form a first metal silicide 7, including NiSi 2 _ y NiPtSi 2 -y, NiCoSi 2 .y, NiPtCoSi 2 . y , where 0 y ⁇ l.
  • the thickness of the first metal silicide 7 is, for example, 1 to 9 nm.
  • the remaining portion of the unreacted first metal layer 6 is subsequently stripped. Since the thickness of the first metal layer 6 is sufficiently thin, Ni is insufficient to diffuse into the channel region at a lower annealing temperature, so as shown in FIG. 3, the first metal silicide 7 is close to the end face and the gate side of the channel region. The side of the wall 5 is flush, that is, the first metal silicide 7 does not extend laterally, and does not enter the channel region.
  • a second metal layer 8 is deposited over the entire device by a conventional method such as PECVD, MOCVD > sputtering to cover STI2, first metal silicide 7, and gate stack 3.
  • the material of the second metal layer 8 may be the same as or similar to the material of the first metal layer 6, for example, also including Ni, Ni-Pt, Ni-Co, Ni-Pt-Co, preferably wherein the non-Ni element (Pt and/or Co) The total content is 10% or less (molar ratio).
  • the thickness of the second metal layer 8 is greater than the thickness of the first metal layer 6, specifically l ⁇ 100 nm, which can provide enough metal to form a thicker metal silicide in the source and drain to reduce the source-drain resistance.
  • the second annealing is performed such that the second metal layer 8 passes through the first metal silicide 7 and the first metal silicide 7 and the source and drain regions 4 (specifically, heavily doped source and drain regions)
  • the Si in 4B) reacts to form a second metal silicide 9.
  • the second annealing is, for example, annealing at 450 to 500 ° C for 30 s, and the formed second metal silicide 9 includes NiSi, NiPtSi, NiCoSi, NiPtCoSi, and has a low electrical resistance. It is worth noting that in the prior art, the diffusion speed of the Ni-based metal through the grain boundary of the metal-rich silicide such as NiSi, Ni 2 Si, etc.
  • Si in the substrate 1, source and drain regions 4 may diffuse through the first metal silicide 7 to react with the second metal layer 8, but due to the first metal silicide 7 It is an epitaxially grown ultra-thin silicon-rich silicide with substantially no or only few grain boundaries.
  • the diffusion rate of the Ni-based metal in the second metal layer 8 to the source and drain regions 4 is greatly reduced, and the Si diffusion rate is less than Ni diffusion speed, the difference in the final diffusion speed
  • the dissimilation will cause the second metal silicide 9 to grow substantially only in the direction of the vertical substrate surface, i.e., substantially or completely inhibit the lateral extension of the second metal silicide 9, thus the second metal silicide 9 and the channel region
  • the end faces are parallel to the sides of the gate spacer and are preferably flush, and the second metal silicide 9 does not extend into the channel region.
  • the unreacted second metal layer 8 is stripped again.
  • the thickness of the second metal silicide 9 is greater than the thickness of the first metal silicide 7, for example, 10 to 50 nm.
  • a subsequent device structure is formed.
  • an interlayer dielectric layer forming a low-k material is deposited on the entire device.
  • the dummy gate stack structure 3 may be removed, a high-k material, a metal nitride barrier layer, a metal work function layer, a final gate stack structure of the cap layer), etching the interlayer dielectric layer to form a source/drain contact hole, depositing a metal and a nitride thereof in the source/drain contact hole to form a contact plug.
  • the semiconductor device manufacturing method of the present invention by epitaxially growing an ultra-thin metal silicide on the source and drain regions, grain boundaries between silicide grains are reduced or eliminated, and metal diffusion speed and direction are limited, thereby suppressing The lateral growth of the metal silicide further enhances the performance of the device.

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Abstract

一种半导体器件制造方法，包括步骤：在衬底（1）上形成栅极堆叠结构（3）；在栅极堆叠结构（3）两侧形成源漏区（4）和栅极侧墙（5）；在源漏区（4）上淀积第一金属层（6）；执行第一退火，使得第一金属层（6）与源漏区（4）反应，外延生长形成第一金属硅化物（7）；在第一金属硅化物（7）上淀积第二金属层（8）；执行第二退火，使得第二金属层（8）与第一金属硅化物（7）及源漏区（4）反应，形成第二金属硅化物（9）。依照该半导体器件制造方法，通过在源漏区上外延生长超薄的金属硅化物，减小或者消除了硅化物晶粒之间的晶界，限制了金属扩散速度和方向，从而抑制了金属硅化物的横向生长，进一步提高了器件的性能。

Description

半导体器件制造方法 优先权要求
本申请要求了 2012年 5月 11日提交的、 申请号为 201210147554.5、 发明名称为 "半导体器件制造方法" 的中国专利申请的优先权， 其全 部内容通过引用结合在本申请中。 技术领域
本发明涉及一种半导体器件制造方法， 特别是涉及一种有效控制 金属硅化物侧向延伸以及降低源漏接触电阻的半导体器件制造方法。 背景技术
IC 集成度不断增大需要器件尺寸持续按比例缩小， 然而电器工作 电压有时维持不变， 使得实际 MOS器件内电场强度不断增大。 高电场 带来一系列可靠性问题， 使得器件性能退化。 例如， MOSFET 源漏区 之间的寄生串联电阻会使得等效工作电压下降， 容易造成器件性能降 低。
一种能有效降低源漏电阻的器件结构是在衬底中利用自对准硅化 工艺 （SALICIDE )形成金属硅化物， 通常为 Ni、 NiPt、 NiCo、 NiPtCo 等镍基金属的相应硅化物。 制造方法通常是在器件中栅极堆叠结构上 和栅极侧墙两侧的衬底上溅射镍基金属， 然后进行较低温度 （例如 450 ~ 550°C ) 的快速热退火， 使得镍基金属与衬底中的硅反应形成具 有较低薄膜电阻的镍基金属硅化物， 并且以此直接作为器件的源漏区， 从而有效降低源漏接触、 寄生电阻。
然而， 由于镍基金属不仅位于衬底待形成源漏区的位置上还位于 栅极侧墙和栅极堆叠上， 以及在上述 SALICIDE 工艺期间执行快速热 退火， 上述镍基金属不仅与暴露出的衬底反应， 而且还会有一部分扩 散进入栅极侧墙下方， 使得形成的镍基金属硅化物横向扩散、 侵犯到 栅极侧墙下方，甚至进入沟道区。而随着器件工艺发展到亚 50nm节点， 上迷镍基金属硅化物的横向扩展将导致重大问题， 例如增大了栅极泄 漏电流、 降低了器件可靠性、 源漏区可能接合短路、 栅极对于沟道区 的控制减弱， 最终造成器件失效。 特别地， 由于 SOI顶 Si层较薄， 较 少的 Si含量可能使得金属硅化物横向扩散问题更严重。
针对这种横向扩散问题， 一种方案是采用两步退火法。 具体地， 在栅极堆叠结构和栅极侧墙两側以及两侧的衬底上沉积镍基金属层， 执行温度较低的笫一退火， 例如约 300°C , 使得镍基金属层与衬底中 Si 反应形成富镍相的金属硅化物， 由于该第一退火温度足够低， 抑制 了 Ni基金属的扩散， 使得反应形成的富镍相金属硅化物较少延展到栅 极侧墙下方、 更不会突入沟道区中。 剥除未反应的镍基金属层之后， 执行温度较高的第二退火， 例如 450 ~ 500°C , 使得富镍相的金属硅化 物转化为具有较低电阻的镍基金属硅化物。 然而在上述方法中， 由于 镍基金属层剥除不完全而在栅极侧墙上有残留、 或者是由于富镍相镍 基金属硅化物中镍基金属含量较高， 在第二退火时， 仍然有少量的镍 基金属硅化物会突入栅极侧墙下方， 严重时甚至会进入沟道区乃至连 通源漏区， 造成器件性能下降或者失效。
综上所述， 现有技术中难以完全抑制镍基金属硅化物的横向延伸， 严重制约了器件性能的提高。 发明内容
由上所述， 本发明的目的在于提供一种能有效抑制金属硅化物横 向延伸的半导体器件制造方法。
为此， 本发明提供了一种半导体器件制造方法， 包括步骤： 在衬 底上形成栅极堆叠结构； 在栅极堆叠结构两侧形成源漏区和栅极侧墙； 在源漏区上淀积第一金属层； 执行第一退火， 使得第一金属层与源漏 区反应， 外延生长形成第一金属硅化物； 在第一金属硅化物上淀积第 二金属层； 执行第二退火， 使得第二金属层与第一金属硅化物及源漏 区反应， 形成第二金属硅化物。
其中， 栅极侧墙包括氧化物、 氮化物及其组合。
其中， 形成源漏区和栅极侧墙的步骤进一步包括： 以栅极堆叠结 构为掩膜， 执行第一源漏离子注入， 在栅极堆叠结构两侧的衬底中形 成轻掺杂的源漏延伸区； 在栅极堆叠结构两側的衬底上形成栅极侧墙； 以栅极側墙为掩膜， 执行第二源漏离子注入， 在栅极側墙两側的衬底 中形成重掺杂源漏区； 退火， 激活掺杂离子。
其中， 衬底包括体 Si、 SOL 其中， 第一金属层和 /或第二金属层为镍基金属层， 包括 Ni、 Ni-Pt、 Ni-Co、 Ni-Pt-Co。 其中， 第一金属层中非 Ni元素的总含量小于等于 10
%。
其中， 第一金属层厚度为 0.5 ~ 5nm。
其中， 第二金属层厚度为 1 ~ 100nm。
其中， 第一金属硅化物厚度为 1 ~ 9nm。
其中， 第一金属硅化物包括 NiSi2_y、 NiPtSi2-y、 NiCoSi2-y、
NiPtCoSi2.y, 其中 0 y<l。
其中， 第二金属硅化物包括 NiSi、 NiPtSi、 NiCoSi、 NiPtCoSi。 依照本发明的半导体器件制造方法， 通过在源漏区上外延生长超 薄的金属硅化物， 减小或者消除了硅化物晶粒之间的晶界， 限制了金 属扩散速度和方向， 从而抑制了金属硅化物的横向生长， 进一步提高 了器件的性能。 附图说明
以下参照附图来详细说明本发明的技术方案， 其中：
图 1至图 5为依照本发明的半导体器件制造方法的各个步骤的剖面 意图； 以及
图 6为依照本发明的半导体器件制造方法的流程图。 具体实施方式
以下参照附图并结合示意性的实施例来详细说明本发明技术方案 的特征及其技术效果， 公开了可有效抑制金属硅化物横向延伸的半导 体器件制造方法。 需要指出的是， 类似的附图标记表示类似的结构， 本申请中所用的术语 "第一" 、 "第二" 、 "上" 、 "下" 等等可用 于修饰各种器件结构或制造工序。 这些修饰除非特别说明并非暗示所 修饰器件结构或制造工序的空间、 次序或层级关系。 示意图。 " 、 ' ' '
参照图 6以及图 1， 形成基础 MOSFET结构， 也即在衬底 1上形成栅 极堆叠结构 3， 在栅极堆叠结构 3的两側村底 1中形成源漏区 4 , 在栅极 堆叠结构两側的衬底 1上栅极侧墙 5。 提供衬底 1 ,衬底 1为含硅材质，例如体硅（ Si )、绝缘体上硅（ SOI )、 SiGe、 Si：、 应变硅、 硅纳米管等等， 优选地采用体 Si或 SOI。 在衬底 1 中形成有源区隔离 2 , 例如先刻蚀形成浅沟槽然后填充氧化硅等绝缘材 质形成浅沟槽隔离 （STI ) 2。
在有源区内的衬底 1上通过 LPCVD、 PECVD、 HDPCVD、 ALD、 MBE、 MOCVD, 溅射等常规方法依次形成栅极绝缘层 3A、 栅极填充 层 3B、 栅极盖层 3C并刻蚀形成栅极堆叠结构 3。 前栅工艺中， 栅极堆叠 结构 3在后续工艺中得以保留， 因此栅极绝缘层 3 A为氧化硅或高 k材料， 高 k材料包括但不限于氮化物（例如 SiN、 A1N、 TiN )、 金属氧化物（主 要为副族和镧系金属元素氧化物，例如 A1203、 Ta205、 Ti02、 ZnO、 Zr02、 Hf02、 Ce02、 Y203 ) 、 钙钛矿相氧化物 （例
Figure imgf000006_0001
( PZT ) 、 BaxSn.xTi03 ( BST ) ) ； 栅极填充层 3B包括掺杂多晶硅、 金属、 金属 合金、 以及金属氮化物， 其中所述金属例如包括W、 Cu、 Mo、 Ti、 Al、 Ta; 栅极盖层 3C例如为氮化硅， 用于保护栅极堆叠结构。 在后栅工艺 中， 栅极堆叠结构 3为伪栅极堆叠结构， 在形成源漏区之后需要刻蚀去 除然后再填充， 因此栅极绝缘层 3A为氧化硅，栅极填充层 3B为多晶硅、 微晶硅、 非晶硅， 栅极盖层 3C仍为氮化硅。
以栅极堆叠结构 3为掩膜， 执行低剂量和低能量的第一次源漏离子 注入， 在栅极堆叠结构 3两侧的衬底 1中形成轻掺杂的源漏延伸区 4 A。
在栅极堆叠结构 3上沉积绝缘介质并刻蚀， 形成栅极侧墙 5 , 其材 质包括氧化物、 氮化物及其组合， 例如为氮化硅、 氮氧化硅、 类金刚 石无定形碳（DLC ) 、 高应力金属氧化物（应力大于 lGPa )及其组合。 栅极侧墙 5可以是单层， 也可以是上述这些材料的叠层， 例如氧化物- 氮化物-氧化物的 ONO结构， 或是氮化物与 DLC的叠层结构等等。
以栅极侧墙 5为掩膜， 执行高剂量和高能量的第二次源漏离子注 入， 在栅极侧墙 5两側的衬底 1中形成重掺杂源漏区 4B。 两次离子注入 的种类和浓度依照器件导电类型需要而合理设定， 并且在离子注入之 后执行退火， 激活掺杂离子， 退火温度以及时间依照掺杂浓度和深度 需要而定。
参照图 6以及图 2， 在整个器件上通过例如 PECVD、 MOCVD、 溅射 的常规方法沉积形成第一金属层 6, 覆盖了 STI2、 源漏区 4以及栅极堆 叠结构 3。 第一金属层 6其材质为镍基金属， 例如包括 Ni、 Ni-Pt、 Ni-Co、 Ni-Pt-Co, 优选地其中非 Ni元素（Pt和 /或 Co )总含量小于等于 10 % (摩 尔比） 。 第一金属层 6的厚度超薄， 以便使得稍后退火而外延生长形成 的第一金属硅化物足够薄， 基本没有或者仅有非常少的晶界 （grain boundaries ) 。 第一金属层 6的厚度例如仅 0.5 ~ 5nm。
参照图 6以及图 3， 执行第一退火， 使得第一金属层 6与源漏区 4 (具 体而言是重掺杂源漏区 4B ) 中的 Si反应形成第一金属硅化物 7。 第一退 火例如是在 450 ~ 500Γ下退火 30s,使得上述超薄的第一金属层 6与重掺 杂源漏区 4B中 Si反应， 外延生长形成第一金属硅化物 7, 包括 NiSi2_y、 NiPtSi2-y、 NiCoSi2.y, NiPtCoSi2.y, 其中 0 y<l。 第一金属硅化物 7的厚 度例如为 l ~ 9nm。 随后剥除未反应的第一金属层 6的残余部分。 由于第 一金属层 6厚度足够薄， Ni在较低的退火温度下不足以扩散进入沟道区 反应， 因此如图 3所示， 第一金属硅化物 7靠近沟道区的端面与栅极侧 墙 5的侧面齐平， 也即第一金属硅化物 7不会横向延伸、 更不会进入沟 道区。
参照图 6以及图 4, 在整个器件上通过例如 PECVD、 MOCVD> 溅射 的常规方法沉积形成笫二金属层 8， 覆盖了 STI2、 第一金属硅化物 7以 及栅极堆叠结构 3。 第二金属层 8材质可以与第一金属层 6材质相同或相 近， 例如也包括 Ni、 Ni-Pt、 Ni-Co、 Ni-Pt-Co, 优选地其中非 Ni元素 ( Pt 和 /或 Co ) 总含量小于等于 10 % (摩尔比） 。 但是， 第二金属层 8的厚 度大于第一金属层 6的厚度， 具体为 l ~ 100nm, 能够提供足够多的金属 以便在源漏中形成较厚的金属硅化物从而降低源漏电阻。
参照图 6以及图 5， 执行第二退火， 使得第二金属层 8穿过第一金属 硅化物 7而与第一金属硅化物 7及源漏区 4 (具体而言是重掺杂源漏区 4B ) 中的 Si反应形成第二金属硅化物 9。 第二退火例如是在 450 ~ 500°C 下退火 30s , 形成的第二金属硅化物 9包括 NiSi、 NiPtSi、 NiCoSi , NiPtCoSi, 具有较低的电阻。 值得注意的是， 在现有技术中， Ni基金属 穿过 NiSi、 Ni2Si等富金属相硅化物的晶界的扩散速度较快， 这也是金 属硅化物横向生长的原因。 而在本发明的第二退火过程中， 衬底 1、 源 漏区 4中的 Si可以扩散穿过该第一金属硅化物 7而与第二金属层 8反应， 但是由于第一金属硅化物 7是外延生长的超薄富硅相硅化物， 基本没有 或者仅有很少的晶界， 第二金属层 8中的 Ni基金属向源漏区 4中扩散速 度大幅降低， 而 Si扩散速度又小于 Ni扩散速度， 最终这种扩散速度的差 异化将导致第二金属硅化物 9基本仅沿着垂直衬底表面的方向生长， 也 即基本或者完全抑制了第二金属硅化物 9的横向延伸， 因此第二金属硅 化物 9与沟道区的端面平行于栅极侧墙的侧面并优选齐平， 第二金属硅 化物 9不会延伸进入沟道区。 最终再剥除未反应的第二金属层 8。 第二 金属硅化物 9的厚度要大于第一金属硅化物 7的厚度，例如为 10 ~ 50nm。
之后， 与传统的 MOSFET工艺类似， 形成后续器件结构。 例如在整 个器件上沉积形成低 k材料的层间介质层、 （后栅工艺中， 还可包括去 除伪栅极堆叠结构 3 , 重新沉积高 k材料、 金属氮化物阻挡层、 金属功 函数层、 盖层的最终栅极堆叠结构） 、 刻蚀层间介质层形成源漏接触 孔、 在源漏接触孔中沉积金属及其氮化物形成接触塞。
依照本发明的半导体器件制造方法， 通过在源漏区上外延生长超 薄的金属硅化物， 减小或者消除了硅化物晶粒之间的晶界， 限制了金 属扩散速度和方向， 从而抑制了金属硅化物的横向生长， 进一步提高 了器件的性能。
尽管已参照一个或多个示例性实施例说明本发明， 本领域技术人 员可以知晓无需脱离本发明范围而对器件结构做出各种合适的改变和 等价方式。 此外， 由所公开的教导可做出许多可能适于特定情形或材 料的修改而不脱离本发明范围。 因此， 本发明的目的不在于限定在作 为用于实现本发明的最佳实施方式而公开的特定实施例， 而所公开的 器件结构及其制造方法将包括落入本发明范围内的所有实施例。

Claims

权 利 要 求
1. 一种半导体器件制造方法， 包括步骤：
在衬底上形成栅极堆叠结构；
在栅极堆叠结构两側形成源漏区和栅极侧墙；
在源漏区上淀积第一金属层；
执行第一退火， 使得第一金属层与源漏区反应， 外延生长形成第 一金属硅化物；
在第一金属硅化物上淀积第二金属层；
执行第二退火， 使得第二金属层与第一金属硅化物及源漏区反应， 形成第二金属硅化物。
2. 如权利要求 1的半导体器件制造方法， 其中， 栅极側墙包括氧化 物、 氮化物及其组合。
3. 如权利要求 1的半导体器件制造方法， 其中， 形成源漏区和栅极 侧墙的步骤进一步包括：
以栅极堆叠结构为掩膜， 执行第一源漏离子注入， 在栅极堆叠结 构两側的衬底中形成轻掺杂的源漏延伸区；
在栅极堆叠结构两侧的衬底上形成栅极侧墙；
以栅杈侧墙为掩膜， 执行第二源漏离子注入， 在栅极側墙两側的 衬底中形成重掺杂源漏区；
退火， 激活掺杂离子。
4. 如权利要求 1的半导体器件制造方法， 衬底包括体 Si、 SOL
5. 如权利要求 1的半导体器件制造方法， 其中， 第一金属层和 /或 第二金属层为镍基金属层， 包括 Ni、 Ni-Pt、 Ni-Co、 Ni-Pt-Co。
6. 如权利要求 5的半导体器件制造方法， 其中， 第一金属层中非 Ni元素的总含量小于等于 10 %。
7. 如权利要求 1的半导体器件制造方法， 其中， 第一金属层厚度为 0.5 ~ 5nm。
8. 如权利要求 1的半导体器件制造方法， 其中， 第二金属层厚度为 1 ~ 100nm。
9. 如权利要求 1的半导体器件制造方法， 其中， 第一金属硅化物厚 度为 1 ~ 9亂
10. 如权利要求 1的半导体器件制造方法， 其中， 第一金属硅化物 包括 NiSi2.y、 NiPtSi2.y、 NiCoSi2-y, NiPtCoSi2.y, 其中 0 y<l。
11. 如权利要求 1的半导体器件制造方法， 其中， 第二金属硅化物 包括 NiSi、 NiPtSi、 NiCoSi、 NiPtCoSio
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