WO2012046841A1 - プリント配線板の製造方法及びそのプリント配線板の製造方法を用いて得られたプリント配線板 - Google Patents

プリント配線板の製造方法及びそのプリント配線板の製造方法を用いて得られたプリント配線板 Download PDF

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Publication number
WO2012046841A1
WO2012046841A1 PCT/JP2011/073218 JP2011073218W WO2012046841A1 WO 2012046841 A1 WO2012046841 A1 WO 2012046841A1 JP 2011073218 W JP2011073218 W JP 2011073218W WO 2012046841 A1 WO2012046841 A1 WO 2012046841A1
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Prior art keywords
wiring board
printed wiring
insulating resin
manufacturing
copper
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PCT/JP2011/073218
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English (en)
French (fr)
Japanese (ja)
Inventor
吉川　和広
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三井金属鉱業株式会社
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Application filed by 三井金属鉱業株式会社 filed Critical 三井金属鉱業株式会社
Priority to KR1020137008689A priority Critical patent/KR101553635B1/ko
Priority to CN201180048731.8A priority patent/CN103155724B/zh
Priority to JP2012537773A priority patent/JP5794740B2/ja
Publication of WO2012046841A1 publication Critical patent/WO2012046841A1/ja

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    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/28—Applying non-metallic protective coatings
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/02—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding
    • H05K3/06—Apparatus or processes for manufacturing printed circuits in which the conductive material is applied to the surface of the insulating support and is thereafter removed from such areas of the surface which are not intended for current conducting or shielding the conductive material being removed chemically or electrolytically, e.g. by photo-etch process
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07—Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0779—Treatments involving liquids, e.g. plating, rinsing characterised by the specific liquids involved
    • H05K2203/0786—Using an aqueous solution, e.g. for cleaning or during drilling of holes
    • H05K2203/0789—Aqueous acid solution, e.g. for cleaning or etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor

Definitions

  • the present invention relates to a printed wiring board manufacturing method and a printed wiring board obtained by using the printed wiring board manufacturing method.
  • the present invention relates to a printed wiring board having excellent adhesion between a solder resist layer and an insulating resin layer surface exposed between circuits.
  • FIG. 6 shows a cross section of the printed wiring board where delamination has occurred. In FIG. 6, it can be clearly observed that a space (delamination DL) exists between the insulating resin base material BM and the solder resist PSR up to the immediate vicinity of the copper circuit CC.
  • Patent Document 1 As techniques for improving the moisture absorption and heat-resistant adhesion between the solder resist layer and the insulating resin layer, there are techniques disclosed in Patent Document 1 and Patent Document 2 below.
  • Patent Document 1 discloses a method for producing a printed wiring board that is advantageous in terms of fine wiring formation, electrical characteristics, and manufacturing cost, and has high reliability.
  • a roughening treatment is performed on the resin surface serving as an adhesive interface with the solder resist layer.
  • Hitachi in which four resin-coated copper foils were applied by coating the resin composition to a thickness of 3.0 ⁇ m and dried at 160 ° C. for about 10 minutes so that the residual solvent was 5% by weight or less.
  • Copper-clad laminate produced by placing glass cloth insulation layer high Tg epoxy resin prepreg GEA-679F (thickness 0.1 mm) made by Kasei Kogyo Co., Ltd. and press-molding at 180 ° C. and 2.5 MPa for 1 hour.
  • the printed wiring board from which unnecessary copper foil was removed with an iron chloride-based etchant was treated with 3% sodium hydroxide + 6% potassium permanganate aqueous solution and chemically roughened on the insulating resin substrate.
  • SR-7200G soldder resist
  • SR-7200G soldder resist manufactured by Seiko Kogyo Co., Ltd. is laminated and treated for 2 hours under the conditions of 121 ° C., 100% humidity and 2 atm. There is a description that no blistering or the like occurs in the solder resist even after treatment for 196 hours under the condition of 2 atm.
  • Patent Document 2 even when a metal foil having a small surface roughness on the surface to be in close contact with the insulating layer can be used, it is possible to ensure the adhesion of the solder resist on the insulating layer after removing the metal foil.
  • the metal foil of the laminated sheet with metal foil bonded to the insulating layer is removed.
  • the circuit board having the formed conductor pattern a circuit board in which a rough surface shape is formed on the exposed insulating layer surface after removing the metal foil and a method for manufacturing the circuit board are disclosed.
  • Patent Document 2 a profile-free copper foil manufactured by Hitachi Chemical Co., Ltd. is provided on both sides of the inner layer core material subjected to blackening treatment via GEA-679FG manufactured by Hitachi Chemical Co., Ltd. as an insulating layer.
  • oxygen plasma treatment was performed on a printed wiring board on which a conductor pattern was formed by a semi-additive method using oxygen as a plasma gas at an output of 1000 W and an atmospheric pressure of 100 Pa for 5 minutes.
  • Patent Document 1 and Patent Document 2 are obtained by etching a metal foil of a metal foil-clad laminate using a metal foil having a small surface roughness and processing the surface of the exposed insulating layer.
  • etching a metal foil of a metal foil-clad laminate using a metal foil having a small surface roughness By obtaining a state having a surface roughness equivalent to the exposed surface of the insulating resin layer with unevenness when using a copper foil that has been roughened, between the insulating resin layer and the solder resist Ensures good moisture absorption and heat-resistant adhesion.
  • the copper foil layer of the copper clad laminate using the copper foil having a small surface roughness is etched to form a circuit shape, and between the circuits.
  • the present inventors have focused on the anticorrosive component of the copper foil remaining on the surface of the insulating resin layer exposed between the circuits after etching the copper foil with a copper etching solution, and the solder resist layer and We have come up with a method to stabilize moisture absorption and heat-resistant adhesion to the surface of insulating resin.
  • the manufacturing method of a printed wiring board according to the present invention is a method of manufacturing a printed wiring board using a copper-clad laminate in which a non-roughened copper foil is laminated, After forming the circuit by etching the roughened copper foil with a copper etchant, the surface of the insulating resin exposed between the circuits is subjected to a purification treatment, and the non-roughened copper foil remaining on the surface of the insulating resin subjected to the purification treatment When surface-treated metal components are semi-quantitatively analyzed with an XPS analyzer (X-ray source: Al (K ⁇ ), acceleration voltage: 15 kV, beam diameter: 50 ⁇ m), each surface-treated metal component is made to be below the detection limit. It is what.
  • Method for producing printed wiring board after formation of solder resist layer according to the present invention The method for producing a printed wiring board after formation of the solder resist layer according to the present invention has been subjected to a purification treatment referred to in the method for producing a printed wiring board described above. A solder resist layer is formed later.
  • the printed wiring board according to the present invention is a printed wiring board after formation of a solder resist layer obtained by the method for manufacturing a printed wiring board according to the present invention, and is 121 ° C. and humidity 100%. No spot delamination with a diameter of 20 ⁇ m or more occurs between the solder resist layer and the surface of the insulating resin when immersed in a solder bath at 260 ° C. for 60 seconds after treatment at 2 atm for 5 hours. It is characterized by.
  • the pressure cooker test (121 ° C., humidity 100%, 2 atm, without roughening the insulating resin surface exposed between the circuits) After the treatment for 5 hours under the above conditions), even if immersed in a solder bath at 260 ° C. for 60 seconds or more, it is possible to stably supply a printed wiring board in which spot-like delamination having a diameter of 20 ⁇ m or more does not occur.
  • the printed wiring board obtained by this manufacturing method has a flat surface between the insulating resin layers exposed between the circuits, and even after the extremely severe pressure cooker test, the insulating resin layer and the solder resist, which are practically problematic, are used. It exhibits the characteristic that spot-like delamination with a diameter of 20 ⁇ m or more does not occur between them, and is excellent in migration resistance. Therefore, it becomes a high-quality product excellent in long-term use stability.
  • a manufacturing method of a printed wiring board according to the present invention is a method of manufacturing a printed wiring board using a copper-clad laminate in which a non-roughened copper foil is laminated, After forming the circuit by etching the roughened copper foil with a copper etchant, the surface of the insulating resin exposed between the circuits is subjected to a purification treatment, and the non-roughened copper foil remaining on the surface of the insulating resin subjected to the purification treatment When surface-treated metal components are semi-quantitatively analyzed with an XPS analyzer (X-ray source: Al (K ⁇ ), acceleration voltage: 15 kV, beam diameter: 50 ⁇ m), each surface-treated metal component is made to be below the detection limit.
  • XPS analyzer X-ray source: Al (K ⁇ ), acceleration voltage: 15 kV, beam diameter: 50 ⁇ m
  • the feature of the printed wiring board according to the present invention is that the surface-treated metal component of the non-roughened copper foil remaining on the surface of the insulating resin exposed between the circuits is removed as much as possible after the circuit is formed by etching. It is in. This is because if the metal component remains on the surface of the insulating resin layer exposed between the circuits, the adhesion between the solder resist layer and the insulating resin layer is adversely affected and the migration resistance during energization is deteriorated.
  • the moisture absorption and heat resistant adhesion between the solder resist layer provided on the surface and the insulating resin layer provided on the outer layer can be kept good.
  • the moisture absorption / heat resistance adhesion in the present invention is determined by combining a predetermined pressure cooker test and a solder heat resistance test.
  • copper-clad laminate laminated with non-roughened copper foil used in the present invention.
  • the term “copper-clad laminate laminated with non-roughened copper foil” as used herein is a general term for copper-clad laminates that use non-roughened copper foil as the outermost copper foil, so-called single-sided copper It includes all the concepts of a laminated laminate, a double-sided copper-clad laminate, and a multilayer copper-clad laminate including an inner layer core substrate.
  • non-roughened copper foil an electrolytic copper foil, a rolled copper foil, and an ultrathin copper foil with a carrier can be used, and the thickness is not particularly limited.
  • the surface treatment of the copper foil is not particularly limited, and as a rust preventive component, nickel-zinc alloy, nickel-cobalt alloy, nickel-zinc-molybdenum alloy, nickel-cobalt-molybdenum alloy, zinc-tin Various alloys such as alloys and chromate treatment can also be used. Furthermore, the contact surface of the copper foil with the insulating resin layer may be provided with a silane coupling agent treatment layer such as an epoxy silane coupling agent, an amino silane coupling agent, or a mercapto silane coupling agent. It is preferable from the viewpoint of improvement.
  • the insulating resin layer used for the production of the copper-clad laminate is not particularly limited with respect to its resin component and skeletal materials such as glass cloth and glass nonwoven fabric disposed in the resin.
  • the insulating resin layer can also contain filler particles.
  • the non-roughened copper foil with primer resin layer should be used in arranging the non-roughened copper foil in the outermost layer of the copper-clad laminate. Is preferred.
  • This non-roughened copper foil with a primer resin layer is a copper foil provided with an extremely thin primer resin layer for ensuring good adhesion to a resin base material on one side of a copper foil that has not been subjected to a roughening treatment. It is.
  • a non-roughened copper foil with a primer resin layer for example, “Multi Foil G: abbreviation MFG” manufactured by Mitsui Mining & Smelting Co., Ltd., “PF-E” manufactured by Hitachi Chemical Co., Ltd., or the like can be used.
  • the primer resin layer exhibits an adhesive force to both the copper foil and the insulating resin, and it is easy to ensure good adhesion between the non-roughened copper foil and the insulating resin layer. Become.
  • a circuit can be formed using a subtractive method or a semi-additive method.
  • the subtractive method first, a non-roughened copper foil in the outermost layer of the copper-clad laminate is etched with a copper etching solution to remove unnecessary copper foil portions, thereby forming a circuit.
  • an etching resist layer is formed on the surface of the outer copper foil, the etching resist pattern is formed by exposure and development, and then a circuit pattern is formed using a copper etching solution. Then, the etching resist is removed to form a printed wiring circuit.
  • a hole will be made in the position which forms the via hole of the copper clad laminated board which bonded the non-roughened copper foil.
  • electroless copper plating is performed, a plating resist layer is formed on the surface of the formed electroless copper plating layer, and the plating resist pattern is exposed and developed.
  • copper is electroplated to form a circuit pattern, the plating resist is removed, and then the non-roughened copper foil is etched away with a copper etchant, thereby forming a printed wiring board circuit.
  • the method for producing a printed wiring board according to the present invention is originally not particularly limited with respect to the type of copper etching solution such as copper chloride etching solution, iron chloride etching solution, sulfuric acid-hydrogen peroxide etching solution, Either use is possible. However, it is most preferably applied when a sulfuric acid-hydrogen peroxide etching solution is used as the copper etching solution.
  • the “sulfuric acid-hydrogen peroxide-based etchant” among copper etchants is an etchant generally used in the semi-additive method because it is suitable for forming a fine pitch circuit.
  • the method for manufacturing a printed wiring board according to the present invention is suitable for a method for manufacturing a printed wiring board assuming that a “sulfuric acid-hydrogen peroxide etching solution” is used as a copper etching solution when forming a circuit. It can be said.
  • the surface-treated metal component of the non-roughened copper foil remaining on the surface of the insulating resin exposed between the circuits is then removed.
  • This operation is referred to as “purification treatment”.
  • the degree of achievement of this purification treatment is determined by using an XPS analyzer (X-ray source: Al (K ⁇ ), acceleration voltage: 15 kV, beam diameter: 50 ⁇ m) for the surface-treated metal component of the non-roughened copper foil remaining on the surface of the insulating resin. Semi-quantitative analysis and judgment. The reason for using such a method is as follows.
  • the exposed insulating resin layer after purification is dissolved with concentrated sulfuric acid, etc., and the amount of remaining metal elements is confirmed using a highly sensitive direct analysis method such as ICP analysis or atomic absorption spectrometry.
  • ICP analysis or atomic absorption spectrometry Is ideal.
  • chemical analysis method is not a method that can be performed in the manufacturing process because the procedure is complicated and time-consuming.
  • XPS analyzer since it can measure simply, it can also be implemented in a manufacturing process.
  • the pressure cooker test (121 ° C., humidity 100%) can be performed without roughening the surface of the insulating resin exposed between the circuits. Even after being immersed in a solder bath at 260 ° C. for 60 seconds or more after 5 hours treatment at 2 atmospheres, no spot-like delamination with a diameter of 20 ⁇ m or more occurs between the insulating resin layer and the solder resist. This is because the effect can be obtained stably.
  • the surface of the insulating resin exposed between the circuits has a value of the surface roughness (ten-point average roughness Rzjis) of the exposed insulating resin surface before the purification treatment.
  • Rz (S) where Rz (C) is the value of the surface roughness (ten-point average roughness Rzjis) of the exposed insulating resin surface after the purification treatment, [Rz (C) / Rz (S)]
  • the value is preferably 1.2 or less.
  • Rz (C) and Rz (S) are values when “ten-point average roughness (Rzjis)” defined in JIS standard (JIS B 0601 2001 ) is measured using a laser non-contact type roughness meter.
  • the lower limit of detection is about 0.02 ⁇ m.
  • the surface roughness of the surface of the insulating resin exposed between the circuits may increase, and the degree of the increase in the surface roughness is represented by [Rz ( C) / Rz (S)].
  • the surface state changes to a level where the value of [Rz (C) / Rz (S)] exceeds 1.2, for example, when plasma treatment is employed, an undercut occurs in the insulating resin layer that supports the circuit. To do. As a result, the fine circuit is not preferable because the adhesion between the circuit and the insulating resin is lowered.
  • Rz (C) is 1.8 ⁇ m or less. If Rz (C) exceeds 1.8 ⁇ m, the above-described semi-additive process is not preferable because the overetching time must be set longer. In order to form a finer circuit, Rz (C) is more preferably 1.0 ⁇ m or less.
  • the “purification treatment” here is intended to remove the metal component remaining on the surface of the insulating resin exposed between the circuits. Therefore, it can be implemented by appropriately selecting from physical processing and chemical processing. Specifically, an ion beam method, an RF beam method, plasma etching, reactive ion etching, reactive ion beam etching, or other plasma treatment, a concentrated hydrochloric acid solution etching method, a desmear method using permanganic acid, or the like is appropriately selected. It is possible. However, it is necessary to select a method capable of uniformly processing the surface of the printed wiring board on which the fine circuit is formed without damaging the circuit.
  • the metal component remaining on the surface of the insulating resin exposed between the circuits is set to be below the detection limit by semi-quantitative analysis using an XPS analyzer, and the surface roughness after the purification treatment described above is used.
  • the etching amount is small, and the metal component remaining on the surface of the insulating resin exposed between the circuits may not be sufficiently removed, which is not preferable.
  • the input energy exceeds 120 J / cm 2 , an undercut occurs in the insulating resin layer that supports the circuit. As a result, the fine circuit is not preferable because the adhesion between the circuit and the insulating resin is lowered. In such a case, the surface roughness of the insulating resin layer is likely to vary, which is not preferable.
  • the gas partial pressure ratio [(CF 4 partial pressure) / (O 2 partial pressure)] of CF 4 and O 2 is preferably 0.2 to 5.0.
  • the value of the gas partial pressure ratio [(CF 4 partial pressure) / (O 2 partial pressure)] is less than 0.2, the function of reacting with a metal cannot be exhibited, which is not preferable.
  • the value of the gas partial pressure ratio between CF 4 and O 2 [(CF 4 partial pressure) / (O 2 partial pressure)] exceeds 5.0, the function of reacting with the metal reaches saturation, and O Since the partial pressure is low, the function of imparting hydrophilicity to the resin surface cannot be exhibited.
  • the atmospheric pressure in the etching chamber in the range of 5.0 Pa to 200 Pa.
  • the atmospheric pressure in the etching chamber is less than 5.0 Pa, the reaction rate is small and the etching rate is slow, and the productivity of the printed wiring board is extremely lowered, which is not preferable.
  • the atmospheric pressure in the etching chamber exceeds 200 Pa, it is not preferable because it becomes difficult to supply plasma.
  • the insulating resin residue generated by the plasma treatment remains on the surface of the insulating resin exposed between the circuits after the plasma etching, the insulating resin residue is removed by wet cleaning. Since the wet cleaning at this time is intended to remove the insulating resin residue generated by the plasma treatment, the ability to dissolve and remove the metal component remaining on the insulating resin surface is not essential.
  • a method that can obtain the optimum effect may be selected from the physical cleaning and chemical cleaning such as chemical treatment. Among them, for the wet cleaning in the present invention, it is preferable to select cleaning using “pickling solution containing a surfactant” and / or “copper microetching solution”. .
  • any one of a nonionic surfactant, a cationic surfactant, and an amphoteric surfactant can be selectively used. It is also possible to use a mixture of these.
  • the nonionic surfactant referred to here has a hydrophilic group that does not ionize in water, and is classified into an ester type, an ether type, an ester-ether type, and others. Specific examples include higher alcohols, alkylphenols, fatty acids, amines, alkylene diamines, fatty acid amides, sulfonamides, polyhydric alcohols, and glucooxide derivatives.
  • the cationic surfactant is a surfactant having a property that a portion having a hydrophobic group in a solution is ionized to a cation. More specifically, lauryl trimethyl ammonium salt, cetyl trimethyl ammonium salt, stearyl trimethyl ammonium salt, lauryl dimethyl ethyl ammonium salt, lauryl dimethyl ammonium betaine, stearyl dimethyl ammonium betaine, dimethyl-benzyl lauryl ammonium salt, octadecyl dimethyl benzyl ammonium salt Trimethylbenzylammonium salt, triethylbenzylammonium salt, laurylbiridinium salt, laurylimidazolinium salt, stearylamine acetate, laurylamine acetate, and the like.
  • the amphoteric surfactant when dissolved in water, shows the properties of an anionic surfactant in the alkaline region and the properties of a cationic surfactant in the acidic region.
  • the alkylcarboxybetaine type the alkylaminocarboxylic acid type, the alkylimidazoline type, and the like.
  • the surfactant described above is contained in a solution capable of cleaning the surface of the printed wiring board such as sulfuric acid, hydrochloric acid, sulfuric acid-hydrogen peroxide aqueous solution, and the concentration of the surfactant is 0.1 g / L to 20 g / L.
  • An acidic solution used for washing can be obtained by adding so as to have a concentration of. If the surfactant concentration at this time is less than 0.1 g / L, the effect of improving the wettability between the surface of the printed wiring board after the plasma treatment and the solution can be obtained by using any of the above-mentioned surfactants. I can't.
  • the cleaning time of the printed wiring board after the plasma treatment using this acidic solution is preferably 15 seconds to 7 minutes. When this cleaning time is less than 15 seconds, the effect of improving the wettability between the surface of the printed wiring board after the plasma treatment and the solution cannot be obtained. On the other hand, if the cleaning time exceeds 7 minutes, erosion of the circuit portion of the printed wiring board after the plasma treatment starts, which is not preferable.
  • the copper circuit is etched and roughened by a thickness in terms of mass of 0.5 ⁇ m or more. If the copper circuit is etched by 0.5 ⁇ m or more in terms of mass, the surface of the copper circuit exhibits a sufficient adhesive force with the solder resist layer and the insulating resin layer when multilayered. On the other hand, under such etching conditions, it is possible to remove contaminants remaining on the circuit surface, etching residues, residues by cleaning treatment of the insulating resin surface exposed between circuits, and the like. As a result, the adhesion between the solder resist layer and the circuit surface and the adhesion between the insulating resin component and the circuit surface are improved at the same time.
  • Manufacturing method of printed wiring board after formation of solder resist layer is necessary using the printed wiring board manufactured by the method provided with the above-described purification treatment. It is characterized in that a solder resist layer is formed on various locations. Thus, if the printed wiring board manufactured by the method provided with the purification treatment described above is used, the metal component remaining on the surface of the insulating resin exposed between the circuits is below the detection limit of the semi-quantitative analysis using the XPS apparatus.
  • the printed wiring board after the formation of the solder resist layer that has good adhesion between the solder resist layer and the insulating resin layer, the adhesion between the solder resist layer and the circuit surface, and the adhesion between the insulating resin component and the circuit surface. Obtainable.
  • the printed wiring board was prepared using a semi-additive method. The manufacturing procedure of this printed wiring board is common to both the example and the comparative example.
  • a plating resist layer is formed on the surface of the outer layer copper foil of the copper-clad laminate, and exposed and developed using an exposure film for resist pattern for forming a grid-like wiring having a line width / space width of 500 ⁇ m / 1200 ⁇ m, Copper electroplating was performed so that the total thickness was 15 ⁇ m. Then, after removing the plating resist, the exposed non-roughened copper foil was removed by etching using a sulfuric acid-hydrogen peroxide etching solution (CPE800: manufactured by Mitsubishi Gas Chemical Co., Ltd.) to form a circuit.
  • CPE800 sulfuric acid-hydrogen peroxide etching solution
  • Example 2 the non-roughened copper foil with the primer resin layer used in Example 1 was replaced with PF-E-3 manufactured by Hitachi Chemical Co., Ltd. instead of MFG-DMT3F manufactured by Mitsui Mining & Smelting Co., Ltd.
  • a printed wiring board sample was prepared in the same manner as in Example 1.
  • the above-described printed wiring board sample is subjected to purification treatment in the same manner as in Example 1 to produce a purification treatment sample, and the amount of residual metal components on the surface of the insulating resin layer exposed between the circuits of the purification treatment sample is analyzed semi-quantitatively. Further, the surface roughness (Rzjis) was measured. The occurrence of delamination was evaluated in the same manner as in Example 1. Table 1 below shows the surface state of the insulating resin layer exposed between the circuits, and Table 2 shows the evaluation results of delamination and the purification treatment conditions.
  • Example 3 the sample of the printed wiring board produced in Example 1 was used, and only the purification treatment conditions were changed.
  • a microetching liquid (CZ8101B: manufactured by MEC Co., Ltd.) was sprayed for 30 seconds, washed with water and dried to prepare a purification treatment sample.
  • FIG. 3 shows a scanning electron microscope image of the surface of the insulating resin layer exposed between the circuits immediately after the circuit formation
  • FIG. 2 shows a scanning electron microscope image of the surface of the insulating resin layer exposed between the circuits immediately after the plasma etching
  • FIG. 1 shows a scanning electron microscope observation image of the surface of the insulating resin layer exposed between the circuits immediately after microetching.
  • Example 1 Thereafter, in the same manner as in Example 1, the amount of residual metal components on the surface of the insulating resin layer exposed between the circuits of the purification sample was semi-quantitatively analyzed, and the surface roughness (Rzjis) was further measured. The occurrence of delamination was evaluated in the same manner as in Example 1.
  • Table 1 below shows the surface state of the insulating resin layer exposed between the circuits of the purification treatment sample
  • Table 2 below shows the evaluation results of delamination and the purification treatment conditions.
  • Example 3 the sample of the printed wiring board produced in Example 1 was used, and only the purification treatment conditions were changed.
  • the above-mentioned printed wiring board sample was immersed in a potassium permanganate (KMnO 4 ) solution (Rohm and Haas Electronic Materials Co., Ltd.) having a liquid temperature of 80 ° C. for 1 minute, and then the liquid temperature was 45 ° C.
  • the sample was immersed in a neutralizing solution (made by Rohm and Haas Electronic Materials Co., Ltd.) for 5 minutes, washed with water and dried to prepare a purification sample.
  • Example 1 Thereafter, in the same manner as in Example 1, the amount of residual metal components on the surface of the insulating resin layer exposed between the circuits of the purification sample was semi-quantitatively analyzed, and the surface roughness (Rzjis) was further measured. The occurrence of delamination was evaluated in the same manner as in Example 1.
  • Table 1 below shows the surface state of the insulating resin layer exposed between the circuits of the purification treatment sample
  • Table 2 below shows the evaluation results of delamination and the purification treatment conditions.
  • Comparative Example 1 In Comparative Example 1, the purification treatment performed in Example 1 was not performed. The occurrence of delamination was evaluated in the same manner as in Example 1.
  • FIG. 4 shows a surface observation image obtained by observing the generated delamination from the solder resist side using transmitted light. Table 1 below shows the surface state of the insulating resin layer exposed between the circuits, and Table 2 shows the evaluation results of delamination and the purification treatment conditions.
  • Comparative Example 2 In Comparative Example 2, a purification sample was prepared by changing the purification treatment time of 60 minutes performed in Example 1 to 10 minutes. Thereafter, in the same manner as in Example 1, the amount of residual metal components on the surface of the insulating resin layer exposed between the circuits of the purification treatment sample was semi-quantitatively analyzed, and the surface roughness was further measured. The occurrence of delamination was evaluated in the same manner as in Example 1.
  • FIG. 5 shows a surface observation image obtained by observing the generated delamination from the solder resist layer side using transmitted light. Table 1 below shows the surface state of the insulating resin layer exposed between the circuits, and Table 2 shows the evaluation results of delamination and the purification treatment conditions.
  • Comparative Example 3 In Comparative Example 3, a purification treatment sample in which microetching was omitted from the purification treatment performed in Example 3 was produced. Thereafter, in the same manner as in Example 1, the amount of residual metal components on the surface of the insulating resin layer exposed between the circuits of the purification treatment sample was semi-quantitatively analyzed, and the surface roughness was further measured. The occurrence of delamination was evaluated in the same manner as in Example 1. Table 1 below shows the surface state of the insulating resin layer exposed between the circuits, and Table 2 shows the evaluation results of delamination and the purification treatment conditions.
  • Comparative Example 4 In Comparative Example 4, a purification treatment sample in which plasma etching was omitted from the purification treatment performed in Example 3 was produced. Thereafter, in the same manner as in Example 1, the amount of residual metal components on the surface of the insulating resin layer exposed between the circuits of the purification treatment sample was semi-quantitatively analyzed, and the surface roughness was further measured. The occurrence of delamination was evaluated in the same manner as in Example 1. The surface state of the insulating resin layer exposed between the circuits is shown in Table 1 below, and the evaluation results of delamination and the purification treatment conditions are shown in Table 2 below.
  • Comparative Example 3 in which the amount of residual metal component after purification treatment is 5.4 atom%, spot-like delamination is observed at a 300 ⁇ m diameter level, and in Comparative Example 4 in which the amount of residual metal component after purification treatment is 8.0 atom%.
  • Comparative Example 1 where the amount of residual metal component not subjected to purification treatment is 8.4 atom%, spot-like delamination exceeding 1.0 mm is observed. That is, the larger the amount of residual metal components detected on the surface of the insulating resin after the purification treatment, the larger the delamination spot diameter tends to be seen.
  • the adhesion between the “solder resist” and the “insulating resin layer surface exposed between the circuits” is influenced by the metal component remaining on the surface of the insulating resin layer exposed between the circuits. Have received a lot.
  • the microscopic shape changes within a range where the value of [Rz (C) / Rz (S)] is less than 1.2. It can be said that there is almost no influence on the adhesion of.
  • the method for producing a printed wiring board according to the present invention is to purify a printed wiring board with a metal element remaining on the exposed surface of the insulating resin, and to determine the amount of the remaining metal component to be below the limit of quantification by semi-quantitative analysis using an XPS apparatus. By doing so, it is possible to obtain good adhesion to a “solder resist layer” that is subsequently provided on the surface of the printed wiring board without roughening the surface of the insulating resin layer. Therefore, it is possible to obtain a good adhesion with the “resin layer that is laminated afterwards when multilayered” that is provided on the surface of the printed wiring board, and to provide a high-quality printed wiring board. To do.

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Laminated Bodies (AREA)
  • Non-Metallic Protective Coatings For Printed Circuits (AREA)
PCT/JP2011/073218 2010-10-08 2011-10-07 プリント配線板の製造方法及びそのプリント配線板の製造方法を用いて得られたプリント配線板 WO2012046841A1 (ja)

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CN201180048731.8A CN103155724B (zh) 2010-10-08 2011-10-07 印刷线路板的制造方法以及用该印刷线路板的制造方法得到的印刷线路板
JP2012537773A JP5794740B2 (ja) 2010-10-08 2011-10-07 プリント配線板の製造方法及びそのプリント配線板の製造方法を用いて得られたプリント配線板

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Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5470493B1 (ja) * 2013-07-23 2014-04-16 Ｊｘ日鉱日石金属株式会社 樹脂基材、プリント配線板、プリント回路板、銅張積層板及びプリント配線板の製造方法
CN114143982A (zh) * 2022-02-08 2022-03-04 江油星联电子科技有限公司 一种多层印刷电路板的生产制作方法
CN115023058A (zh) * 2022-06-20 2022-09-06 清华大学深圳国际研究生院 一种高精度电路转移至柔性可拉伸基底上的方法

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2022014648A1 (ja) * 2020-07-16 2022-01-20 三井金属鉱業株式会社 銅張積層板及びプリント配線板

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0528835A (ja) * 1990-09-12 1993-02-05 Kakogawa Plast Kk フイルム状銅蒸着基材
JPH0629647A (ja) * 1992-07-08 1994-02-04 Hitachi Ltd フォトレジストの剥離方法
JP2006196761A (ja) * 2005-01-14 2006-07-27 Nitto Denko Corp 配線回路基板の製造方法
JP2006287099A (ja) * 2005-04-04 2006-10-19 Fujikura Ltd レジスト付きプリント配線板の製造方法
JP2008078276A (ja) * 2006-09-20 2008-04-03 Sumitomo Metal Mining Co Ltd 高耐熱密着力を有する銅被覆ポリイミド基板

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN101024800A (zh) * 2006-02-21 2007-08-29 联华电子股份有限公司 清洗液以及移除等离子体工艺后的残余物的方法
JPWO2007148666A1 (ja) * 2006-06-20 2009-11-19 日本化薬株式会社 プライマー樹脂層付銅箔及びそれを使用した積層板
WO2009084533A1 (ja) * 2007-12-28 2009-07-09 Mitsui Mining & Smelting Co., Ltd. 樹脂付銅箔および樹脂付銅箔の製造方法

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0528835A (ja) * 1990-09-12 1993-02-05 Kakogawa Plast Kk フイルム状銅蒸着基材
JPH0629647A (ja) * 1992-07-08 1994-02-04 Hitachi Ltd フォトレジストの剥離方法
JP2006196761A (ja) * 2005-01-14 2006-07-27 Nitto Denko Corp 配線回路基板の製造方法
JP2006287099A (ja) * 2005-04-04 2006-10-19 Fujikura Ltd レジスト付きプリント配線板の製造方法
JP2008078276A (ja) * 2006-09-20 2008-04-03 Sumitomo Metal Mining Co Ltd 高耐熱密着力を有する銅被覆ポリイミド基板

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5470493B1 (ja) * 2013-07-23 2014-04-16 Ｊｘ日鉱日石金属株式会社 樹脂基材、プリント配線板、プリント回路板、銅張積層板及びプリント配線板の製造方法
JP5544444B1 (ja) * 2013-07-23 2014-07-09 Ｊｘ日鉱日石金属株式会社 樹脂基材、プリント配線板、プリント回路板、銅張積層板及びプリント配線板の製造方法
JP2015043401A (ja) * 2013-07-23 2015-03-05 Jx日鉱日石金属株式会社 樹脂基材、プリント配線板、プリント回路板、銅張積層板及びプリント配線板の製造方法
CN114143982A (zh) * 2022-02-08 2022-03-04 江油星联电子科技有限公司 一种多层印刷电路板的生产制作方法
CN115023058A (zh) * 2022-06-20 2022-09-06 清华大学深圳国际研究生院 一种高精度电路转移至柔性可拉伸基底上的方法
CN115023058B (zh) * 2022-06-20 2023-04-18 清华大学深圳国际研究生院 一种高精度电路转移至柔性可拉伸基底上的方法

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KR20130067302A (ko) 2013-06-21
CN103155724B (zh) 2016-01-13
TWI524823B (zh) 2016-03-01
JPWO2012046841A1 (ja) 2014-02-24
JP5794740B2 (ja) 2015-10-14
KR101553635B1 (ko) 2015-09-16
TW201223365A (en) 2012-06-01

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