WO2012043124A1 - Procédé de fabrication de dispositif de conversion photoélectrique - Google Patents

Procédé de fabrication de dispositif de conversion photoélectrique Download PDF

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WO2012043124A1
WO2012043124A1 PCT/JP2011/069811 JP2011069811W WO2012043124A1 WO 2012043124 A1 WO2012043124 A1 WO 2012043124A1 JP 2011069811 W JP2011069811 W JP 2011069811W WO 2012043124 A1 WO2012043124 A1 WO 2012043124A1
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layer
silicon
thin film
intrinsic
photoelectric conversion
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PCT/JP2011/069811
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English (en)
Japanese (ja)
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雅士 吉見
満 市川
俊彦 宇都
山本　憲治
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株式会社カネカ
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Priority to US13/877,148 priority Critical patent/US8691613B2/en
Priority to ES11828685.5T priority patent/ES2625473T3/es
Priority to JP2012536290A priority patent/JP5456168B2/ja
Priority to CN201180045445.6A priority patent/CN103119727B/zh
Priority to EP11828685.5A priority patent/EP2624307B1/fr
Publication of WO2012043124A1 publication Critical patent/WO2012043124A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/1804—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof comprising only elements of Group IV of the Periodic Table
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/068—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells
    • H01L31/0684—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN homojunction type, e.g. bulk silicon PN homojunction solar cells or thin film polycrystalline silicon PN homojunction solar cells double emitter cells, e.g. bifacial solar cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/04—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices
    • H01L31/06—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers
    • H01L31/072—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type
    • H01L31/0745—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells
    • H01L31/0747—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof adapted as photovoltaic [PV] conversion devices characterised by potential barriers the potential barriers being only of the PN heterojunction type comprising a AIVBIV heterojunction, e.g. Si/Ge, SiGe/Si or Si/SiC solar cells comprising a heterojunction of crystalline and amorphous materials, e.g. heterojunction with intrinsic thin layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00—Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/18—Processes or apparatus specially adapted for the manufacture or treatment of these devices or of parts thereof
    • H01L31/186—Particular post-treatment for the devices, e.g. annealing, impurity gettering, short-circuit elimination, recrystallisation
    • H01L31/1868—Passivation
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02E—REDUCTION OF GREENHOUSE GAS [GHG] EMISSIONS, RELATED TO ENERGY GENERATION, TRANSMISSION OR DISTRIBUTION
    • Y02E10/00—Energy generation through renewable energy sources
    • Y02E10/50—Photovoltaic [PV] energy
    • Y02E10/547—Monocrystalline silicon PV cells
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
    • Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
    • Y02P70/50—Manufacturing or production processes characterised by the final manufactured product

Definitions

  • the present invention relates to a method for manufacturing a crystalline silicon photoelectric conversion device having a heterojunction on the surface of a single crystal silicon substrate.
  • a crystalline silicon photoelectric conversion device provided with a crystalline silicon substrate has high photoelectric conversion efficiency, and is widely put into practical use as a photovoltaic power generation system.
  • a crystalline silicon photoelectric conversion device having a conductive amorphous silicon-based layer having a band gap different from that of single-crystal silicon on the surface of a single-crystal silicon substrate is called a heterojunction solar cell.
  • those having an intrinsic amorphous silicon-based layer between a conductive amorphous silicon-based layer and a crystalline silicon substrate are in the form of a crystalline silicon photoelectric conversion device having the highest conversion efficiency.
  • the Defect levels are generated by depositing the conductive amorphous silicon layer by forming an intrinsic amorphous silicon layer between the crystalline silicon substrate and the conductive amorphous silicon layer.
  • defects mainly silicon dangling bonds
  • existing on the surface of the crystalline silicon substrate are terminated with hydrogen (passivation).
  • the presence of the intrinsic amorphous silicon-based layer can prevent the carrier-introduced impurity from diffusing to the surface of the crystalline silicon substrate when forming the conductive amorphous silicon-based layer.
  • Patent Document 1 hydrogen plasma treatment is performed on the surface of the crystalline silicon substrate before forming an intrinsic amorphous silicon-based layer on the crystalline silicon substrate. It has been proposed to clean and clean the substrate surface.
  • Patent Document 2 proposes to control the hydrogen concentration profile in the amorphous silicon-based layer by changing the hydrogen dilution ratio at the time of forming the amorphous silicon-based layer in multiple steps. Patent Document 2 describes that by controlling the hydrogen concentration profile, the dangling bonds of silicon in the film are terminated and carrier recombination is suppressed, thereby improving conversion characteristics.
  • Patent Document 3 proposes that an amorphous silicon-based thin film having a film thickness of less than 1 nm is formed and hydrogen plasma treatment is repeatedly performed. Such a method of repeating film formation and hydrogen plasma treatment is also referred to as “chemical annealing”. According to the chemical annealing, defects in the amorphous silicon-based layer are reduced.
  • the present inventors tried to improve the photoelectric conversion characteristics by a method of performing plasma treatment on the surface of the silicon substrate.
  • sufficient improvement of the characteristics could not be achieved. This is because the hydrogen plasma treatment provides a cleaning effect on the surface of the crystalline silicon substrate, but the substrate surface suffers plasma damage, resulting in defects at the interface between the crystalline silicon substrate and the intrinsic amorphous silicon-based layer. It was estimated that it was not reduced.
  • the film quality of the silicon-based thin film can be improved.
  • chemical annealing improves the film quality only in the range of less than 1 nm from the treated surface.
  • the thickness of the intrinsic amorphous silicon-based layer is required to be at least about 3 nm. It is. Therefore, in order to improve the film quality of the intrinsic amorphous silicon-based layer by chemical annealing, it is necessary to repeat the film formation and the hydrogen plasma treatment many times, and there is a problem that the productivity is inferior.
  • an object of the present invention is to improve photoelectric conversion characteristics by reducing interface defects between a single crystal silicon substrate and a silicon thin film layer in a crystalline silicon photoelectric conversion device.
  • the present inventors can improve the photoelectric conversion characteristics by improving the method for forming an intrinsic amorphous silicon-based layer in the method for manufacturing a crystalline silicon-based photoelectric conversion device. It discovered that there was and made this invention.
  • the present invention has a one conductivity type layer-side intrinsic silicon-based layer and a one conductivity type silicon based layer in this order on one surface of a one conductivity type single crystal silicon substrate, and the other surface of the one conductivity type single crystal silicon substrate.
  • the present invention also relates to a method of manufacturing a crystalline silicon photoelectric conversion device having a reverse conductivity type layer-side intrinsic silicon layer and a reverse conductivity type silicon layer in this order.
  • At least one of the one-conductivity-type-layer-side intrinsic silicon-based layer forming step and the reverse-conductivity-type-layer-side intrinsic silicon-based layer forming step includes the following first intrinsic silicon-based thin film layer forming step and plasma processing step And a second intrinsic silicon-based thin film layer forming step in this order.
  • First intrinsic silicon-based thin film layer forming step a step of forming a first intrinsic silicon-based thin film layer having a thickness of 1 nm to 10 nm on the one-conductivity-type single crystal silicon substrate.
  • Plasma treatment step a step in which the one-conductivity-type single crystal silicon substrate on which the first intrinsic silicon thin film layer is formed is subjected to plasma treatment in a gas atmosphere containing hydrogen as a main component.
  • Second intrinsic silicon-based thin film layer forming step a step of forming a second intrinsic silicon-based thin film layer on the first intrinsic silicon-based thin film layer.
  • the total thickness of the first intrinsic silicon-based thin film layer and the second intrinsic silicon-based thin film layer is preferably 16 nm or less.
  • the plasma discharge is once stopped, and then the plasma discharge is restarted to perform the plasma processing step.
  • the passivation effect of the single crystal silicon substrate of the crystalline silicon photoelectric conversion device is improved, and interface defects between the single crystal silicon substrate and the silicon thin film layer can be reduced. For this reason, the crystalline silicon type photoelectric conversion apparatus excellent in photoelectric conversion efficiency can be provided.
  • an intrinsic silicon-based layer 2 is formed on one surface of a one-conductivity single-crystal silicon substrate 1, and an intrinsic silicon-based layer 4 is formed on the other surface.
  • an intrinsic silicon-based layer 4 is formed on the other surface.
  • a one-conductivity-type silicon-based layer 3 and a reverse-conductivity-type silicon-based layer 5 are formed on each surface of the intrinsic silicon-based layer 2 and the intrinsic silicon-based layer 4.
  • the intrinsic silicon-based layer 2 between the one-conductivity-type single crystal silicon substrate 1 and the one-conductivity-type silicon-based layer 3 is referred to as “one-conductivity-type layer-side intrinsic silicon-based layer” and is opposite to the one-conductivity-type single crystal silicon substrate 1
  • the intrinsic silicon layer 4 between the conductive silicon layer 5 and the conductive silicon layer 5 may be referred to as a “reverse conductivity type layer-side intrinsic silicon layer”.
  • transparent electrode layers 6 and 8 are formed on the surface of each of the one-conductivity-type silicon-based layer 3 and the reverse-conductivity-type silicon-based layer 5, and collector electrodes 7 and 9 are formed thereon.
  • a single crystal silicon substrate contains impurities that supply charges to silicon and has conductivity.
  • a p-type single crystal silicon substrate having an impurity (for example, boron atom) into which is introduced is introduced. That is, “one conductivity type” in this specification means either n-type or p-type.
  • the heterojunction on the incident side where the light incident on the single crystal silicon substrate is absorbed most is a reverse junction. If the heterojunction on the light incident side is a reverse junction, a strong electric field is provided, and electron / hole pairs can be efficiently separated and recovered. On the other hand, when holes and electrons are compared, electrons having smaller effective mass and scattering cross section generally have higher mobility. From the above viewpoint, it is preferable that the single conductivity type single crystal silicon substrate 1 used in the present invention is an n type single crystal silicon substrate.
  • the collector electrode 9 / transparent electrode layer 8 / p-type amorphous silicon-based layer 5 / non-doped amorphous silicon examples thereof include a system layer 4 / n-type single crystal silicon substrate 1 / non-doped amorphous silicon system layer 2 / n-type amorphous silicon system layer 3 / transparent electrode layer 6 / collecting electrode 7 in this order.
  • the n-type amorphous silicon-based layer (also referred to as n layer) side is the back surface side.
  • a collector electrode 9 / transparent electrode layer 8 / n-type amorphous silicon substrate is used as a collector electrode 9 / transparent electrode layer 8 / n-type amorphous silicon substrate.
  • the n-layer side is preferably the incident surface side from the viewpoint of increasing the carrier recovery efficiency with the reverse junction as the light incident side.
  • a texture is formed on the surface of the single crystal silicon substrate.
  • the single crystal silicon substrate is preferably cut out so that the incident surface is a (100) plane. This is because when a single crystal silicon substrate is etched, a texture structure is easily formed by anisotropic etching using the difference in etching rate between the (100) plane and the (111) plane.
  • One conductivity type layer side intrinsic silicon-based layer 2 and one conductivity type silicon based layer 3 are formed on one surface of single crystal silicon substrate 1, and the opposite conductivity type layer side intrinsic silicon based layer 4 is formed on the other surface. Then, the reverse conductivity type silicon-based layer 5 is formed.
  • the method for forming these silicon-based layers is not particularly limited, but it is preferable to use a plasma CVD method. When the silicon-based layer is formed by plasma CVD, the production process can be simplified because the silicon-based layer can be formed in the same chamber and the hydrogen plasma treatment described later can be performed. .
  • a substrate temperature of 100 to 300 ° C., a pressure of 20 to 2600 Pa, and a high frequency power density of 0.003 to 0.5 W / cm 2 are preferably used.
  • a silicon-containing gas such as SiH 4 or Si 2 H 6 is used as a source gas for forming the silicon-based layer.
  • the source gas diluted with H 2 or the like may be introduced into the chamber.
  • B 2 H 6 or PH 3 is preferably used as a dopant gas for forming a conductive type (p-type or n-type) silicon-based layer.
  • a mixed gas in which the dopant gas is previously diluted with a raw material gas or H 2 can also be used.
  • a gas containing a different element such as CH 4 , CO 2 , NH 3 , GeH 4
  • a silicon alloy layer such as silicon carbide, silicon nitride, silicon germanium or the like is manufactured as a silicon-based layer. It may be membraned.
  • the intrinsic silicon layers 2 and 4 are substantially intrinsic non-doped silicon thin films.
  • the intrinsic silicon-based layers 2 and 4 are preferably non-doped hydrogenated amorphous silicon substantially consisting of silicon and hydrogen.
  • the substrate is heated for a predetermined time if necessary. Thereafter, the first intrinsic silicon-based thin film layer 21 is formed.
  • This first intrinsic silicon-based thin film layer has a role as a protective layer for reducing plasma damage to the surface of the single crystal silicon during the hydrogen plasma treatment.
  • the first intrinsic silicon-based thin film layer 21 is preferably formed with a thickness of 1 nm to 10 nm.
  • the film thickness of the first intrinsic silicon-based thin film layer is more preferably 2 nm or more. If the film thickness of the first intrinsic silicon-based thin film layer is too small, the coverage of the single crystal silicon substrate surface becomes insufficient, and the single crystal silicon surface tends to be easily damaged by plasma during the hydrogen plasma treatment. In particular, when the texture is formed on the surface of the single crystal silicon substrate, if the thickness of the first intrinsic silicon-based thin film layer is small, the coverage of the bottom or top of the texture tends to be insufficient.
  • the first intrinsic silicon-based thin film layer 21 is preferably formed with a thickness of 1.5 nm or more, and formed with a thickness of 2 nm or more. It is preferred that The film thickness of the first intrinsic silicon-based thin film layer is more preferably 8 nm or less, further preferably 6 nm or less, particularly preferably 5 nm or less, and most preferably 4 nm or less. If the film thickness of the first intrinsic silicon thin film layer is too large, the passivation effect of the single crystal silicon substrate by hydrogen plasma treatment and the defect reduction effect at the interface between the single crystal silicon substrate and the first intrinsic silicon thin film layer are sufficiently obtained. It may not be possible.
  • the first intrinsic silicon-based thin film layer 21 After the formation of the first intrinsic silicon-based thin film layer 21, a plasma treatment is performed in a gas atmosphere mainly containing hydrogen.
  • the surface thereof is subjected to hydrogen plasma treatment, whereby the conversion characteristics of the crystalline silicon-based photoelectric conversion device, particularly the open circuit voltage (Voc), is improved.
  • the hydrogen plasma treatment is performed after the formation of the first intrinsic silicon-based thin film layer is compared with the case where the hydrogen plasma treatment is performed on the surface of the single crystal silicon substrate. It has been found that the conversion characteristics of the crystalline silicon photoelectric conversion device are improved. This is presumably because the first intrinsic silicon-based thin film layer acts as a protective layer that reduces plasma damage to the single crystal silicon surface during the hydrogen plasma treatment.
  • the high frequency power density and the plasma processing time in the plasma processing step can be appropriately set within a range where the effects of the present invention can be obtained.
  • the high-frequency power density during the plasma treatment is preferably 0.052W / cm 2 or less, 0.039W / cm 2 or less being more preferred.
  • the plasma treatment time is preferably 140 seconds or less, and more preferably 120 seconds or less.
  • the lower limit value of the high frequency power density at the time of plasma processing is not particularly limited as long as it is within a range where hydrogen plasma can be generated.
  • high-frequency power density in the plasma processing step is preferably 0.01 W / cm 2 or more, 0.016W / cm 2 or more is more preferable.
  • the lower limit value of the plasma processing time is not particularly limited, and is appropriately set in consideration of the film thickness of the first intrinsic silicon thin film layer and the high frequency power density in the plasma processing step. From the viewpoint of improving the hydrogen passivation effect on the crystalline silicon substrate, the plasma treatment time is preferably 3 seconds or more, and more preferably 10 seconds or more.
  • “Gas atmosphere mainly composed of hydrogen” in the plasma treatment step may contain an inert gas such as nitrogen, helium, or argon as long as the hydrogen concentration in the atmosphere is 70% by volume or more. A small amount of dopant gas such as B 2 H 6 or PH 3 may be contained.
  • the source gas such as SiH 4 is not introduced into the chamber and the source gas used for forming the first intrinsic silicon thin film layer does not remain in the chamber. . Even if the source gas is included in the gas atmosphere of the plasma treatment step, it is preferable that the silicon-based layer is not substantially formed during the plasma discharge.
  • the allowable range of the content of the source gas in the plasma treatment step depends on other film forming parameters, but is preferably 1/100 or less of hydrogen and more preferably 1/500 or less in volume ratio. Preferably, it is 1/2000 or less.
  • the intrinsic silicon-based layer 2 is preferably non-doped hydrogenated amorphous silicon.
  • the first intrinsic silicon-based thin film layer 21 is amorphous silicon. Even when the film is formed, a part of the first intrinsic silicon-based thin film layer may be crystallized by the hydrogen plasma treatment. The presence of the crystallized component can be confirmed by, for example, cross-sectional observation of the sample with a high-resolution transmission electron microscope (TEM), X-ray diffraction, Raman scattering spectroscopy, or the like.
  • TEM transmission electron microscope
  • X-ray diffraction X-ray diffraction
  • Raman scattering spectroscopy or the like.
  • a second intrinsic silicon thin film layer 22 is formed on the first intrinsic silicon thin film layer 21.
  • the total thickness of the intrinsic silicon-based layer 2 is increased by forming the second intrinsic silicon-based thin film 22 layer after the hydrogen plasma treatment. Therefore, the diffusion of impurity atoms to the single crystal silicon substrate 1 is suppressed during the formation of the conductive silicon-based layer 3.
  • the second intrinsic silicon-based thin film layer 22 is preferably formed with a thickness of 1 nm to 15 nm.
  • the thickness of the second intrinsic silicon-based thin film layer is preferably 2 nm to 14 nm, more preferably 2.5 nm to 12 nm, and further preferably 3 nm to 10 nm.
  • the total thickness of the first intrinsic silicon-based thin film layer 21 and the thickness of the second intrinsic silicon-based thin film layer 22, that is, the thickness of the intrinsic silicon-based layer 2 is preferably 6 nm or more.
  • the film thickness of the intrinsic silicon-based layer 2 is preferably 16 nm or less.
  • the film thickness of the intrinsic silicon-based layer is more preferably 3 nm to 14 nm, and further preferably 5 nm to 12 nm.
  • the first intrinsic silicon-based thin film layer forming step, the plasma processing step, and the second intrinsic silicon-based thin film layer forming step are continuously performed in the same film forming chamber. It is preferable that the plasma discharge is once stopped after the first intrinsic silicon-based thin film layer forming step and before the plasma processing step is started. That is, it is preferable that the supply of the raw material gas is stopped in a state where the plasma discharge is stopped, the discharge is restarted after the inside of the chamber becomes a gas atmosphere mainly containing hydrogen, and the plasma treatment process is started.
  • the plasma processing step is subsequently performed without stopping the plasma discharge after forming the first intrinsic silicon-based thin film layer, the first intrinsic silicon-based thin film layer and the second intrinsic silicon are caused by the source gas remaining in the chamber.
  • An interface layer having a relatively high hydrogen concentration may be formed between the system thin film layer. This interface layer may cause the conversion characteristics to deteriorate. Therefore, if plasma discharge is not stopped before the start of the plasma treatment process, the source gas is exhausted out of the chamber in a short time by a method such as temporarily increasing the hydrogen gas flow rate after forming the first intrinsic silicon-based thin film layer. Thus, it is preferable that the atmospheric gas is replaced.
  • the process of forming the intrinsic silicon-based layer has been described by taking the one-conductivity-type layer-side intrinsic silicon-based layer 2 as an example.
  • At least one of the formation of the reverse conductivity type layer-side intrinsic silicon-based layer 4 has three steps: a first intrinsic silicon-based thin film layer forming step, a plasma processing step, and a second intrinsic silicon-based thin film layer forming step. It only has to be.
  • both the formation process of the one-conductivity-type-layer-side intrinsic silicon-based layer 2 and the reverse-conductivity-type-layer-side intrinsic silicon-based layer 4 have the above three processes, further improvement of conversion characteristics An effect can be obtained.
  • the method for forming the conductive silicon layers 3 and 5 on the intrinsic silicon layers 2 and 4 is not particularly limited.
  • a hydrogenated amorphous silicon layer, an oxidized amorphous silicon layer, an amorphous silicon carbide layer, or the like is formed. Further, not only the amorphous layer but also a microcrystalline layer partially containing a crystalline component may be formed.
  • Transparent electrode layers 6 and 8 are formed on the conductive silicon-based layers 3 and 5.
  • the transparent electrode layer contains a conductive oxide.
  • the conductive oxide for example, zinc oxide, indium oxide, or tin oxide can be used alone or in combination.
  • a conductive doping agent may be added to these conductive oxides.
  • examples of the doping agent added to zinc oxide include aluminum, gallium, boron, silicon, and carbon.
  • examples of the doping agent added to indium oxide include zinc, tin, titanium, tungsten, molybdenum, and silicon. Fluorine etc. are mentioned as a doping agent added to a tin oxide.
  • These conductive oxides may be formed as a single film, or a plurality of layers may be formed.
  • the film thickness of the transparent electrode layer is preferably 10 nm or more and 140 nm or less from the viewpoint of transparency and conductivity.
  • the transparent electrode layer only needs to have conductivity necessary for transporting carriers to the collector electrode. If the film thickness of the transparent electrode layer is too large, the transmittance may decrease due to absorption loss of the transparent electrode layer itself, which may cause a decrease in photoelectric conversion efficiency.
  • a physical vapor deposition method such as a sputtering method, a chemical vapor deposition (MOCVD) using a reaction between an organometallic compound and oxygen or water is preferable.
  • MOCVD chemical vapor deposition
  • energy by heat, plasma discharge or the like may be used for film formation.
  • Collector electrodes 7 and 9 are formed on the transparent electrode layers 6 and 8.
  • the collector electrode can be produced by a known technique such as inkjet, screen printing, wire bonding, spraying, etc., but screen printing is preferable from the viewpoint of productivity.
  • screen printing method a process of printing a conductive paste composed of metal particles and a resin binder by screen printing is preferably used.
  • the photoelectric conversion device obtained by the production method of the present invention can find some differences in physical properties as compared with the photoelectric conversion device produced by the conventional method.
  • a photoelectric conversion device obtained by the manufacturing method of the present invention tends to have a long carrier lifetime. This is presumably because the hydrogen passivation effect on the surface of the single crystal silicon substrate is improved, so that interface defects between the single crystal silicon substrate and the intrinsic silicon-based layer are reduced, and the carrier recombination rate at the interface is reduced.
  • the carrier lifetime can be measured by a ⁇ -PCD method, a QSSPC (Quasi Steady State Photo-conductivity) method, or the like.
  • the film thickness was obtained by observing the cross section with a transmission electron microscope (TEM). Note that it is difficult to identify the interface between the first intrinsic silicon thin film layer and the second intrinsic silicon thin film layer and the interface between the second intrinsic silicon thin film layer and the conductive silicon layer by TEM observation. Therefore, the film thicknesses of these layers were calculated from the ratio between the total thickness of each layer determined from TEM observation and the film formation time. For the layer formed on the surface of the silicon substrate on which the texture was formed, the direction perpendicular to the texture slope was defined as the film thickness direction.
  • TEM transmission electron microscope
  • the output characteristics of the photoelectric conversion device were measured at a sample temperature of 25 ° C. under light irradiation of AM 1.5 and 100 mW / cm 2 .
  • Example 1 In Example 1, a crystalline silicon-based photoelectric conversion device schematically shown in FIG. 1 was manufactured.
  • n-type single crystal silicon substrate having a plane orientation of the incident surface of (100) and a thickness of 200 ⁇ m was washed in acetone. Thereafter, the substrate was immersed in a 2 wt% HF aqueous solution for 3 minutes to remove the silicon oxide film on the surface, and then rinsed with ultrapure water twice. Next, the silicon substrate was immersed in a 5/15 wt% KOH / isopropyl alcohol aqueous solution maintained at 70 ° C. for 15 minutes, and the substrate surface was etched to form a texture. Thereafter, rinsing with ultrapure water was performed twice. When the surface of the single crystal silicon substrate 1 was observed with an atomic force microscope (AFM manufactured by Pacific Nanotechnology), the substrate surface was most etched, and a pyramidal texture with the (111) face exposed was formed. It had been.
  • AFM atomic force microscope
  • the single crystal silicon substrate 1 that has been etched is introduced into the CVD apparatus, and a non-doped amorphous silicon thin film layer having a thickness of 4 nm is formed on one surface (incident surface side) as the first intrinsic silicon thin film layer 41.
  • the film forming conditions were a substrate temperature of 150 ° C., a pressure of 120 Pa, a SiH 4 / H 2 flow rate ratio of 3/10, and a high frequency power density of 0.011 W / cm 2 .
  • the plasma discharge was once stopped and the supply of SiH 4 was stopped. Only hydrogen gas was introduced into the CVD apparatus for about 30 seconds, and the gas in the apparatus was replaced. Thereafter, plasma discharge was resumed and hydrogen plasma treatment was performed.
  • the conditions for the hydrogen plasma treatment were a substrate temperature of 150 ° C., a pressure of 120 Pa, a high frequency power density of 0.026 W / cm 2 , and a treatment time of 60 seconds.
  • a non-doped amorphous silicon thin film layer was formed as a second intrinsic silicon thin film layer 42 with a film thickness of 6 nm.
  • the film forming conditions for the non-doped amorphous silicon thin film layer 42 were the same as the film forming conditions for the non-doped amorphous silicon thin film layer 41.
  • a p-type amorphous silicon layer 5 having a thickness of 4 nm was formed on the second non-doped amorphous silicon thin film layer 42.
  • the deposition conditions for the p-type amorphous silicon layer were as follows: the substrate temperature was 150 ° C., the pressure was 60 Pa, the SiH 4 / dilution B 2 H 6 flow rate ratio was 1/3, and the high-frequency power density was 0.011 W / cm 2 . .
  • As the diluted B 2 H 6 gas a gas diluted with H 2 to a B 2 H 6 concentration of 5000 ppm was used.
  • a first non-doped amorphous silicon thin film layer 21 having a thickness of 4 nm is formed on the other surface (back surface side) of the single crystal silicon substrate 1 and hydrogen plasma treatment is performed.
  • a thin silicon film layer 22 having a thickness of 6 nm was formed.
  • an n-type amorphous silicon layer 3 was formed with a thickness of 4 nm.
  • the film forming conditions for the n-type amorphous silicon layer were a substrate temperature of 150 ° C., a pressure of 60 Pa, a SiH 4 / dilution PH 3 flow rate ratio of 1/3, and a high frequency power density of 0.011 W / cm 2 .
  • As the diluted PH 3 gas a gas diluted with H 2 to a PH 3 concentration of 5000 ppm was used.
  • ITO Indium tin composite oxide
  • ITO Indium tin composite oxide
  • Argon / oxygen was introduced as a carrier gas at 50/1 sccm, and film formation was performed under conditions of a substrate temperature of 150 ° C., a pressure of 0.2 Pa, and a high frequency power density of 0.5 W / cm 2 .
  • a silver paste was screen-printed as collector electrodes 7 and 9 on the respective surfaces of the transparent electrode layers 6 and 8 to form comb-shaped electrodes. Finally, an annealing treatment was performed at 150 ° C. for 1 hour to obtain a photoelectric conversion device.
  • Comparative Example 1 a crystalline silicon photoelectric conversion device was manufactured in the same manner as in Example 1, but each of the non-doped amorphous silicon layers 2 and 4 was formed to a thickness of 10 nm by one film formation. It was. That is, in Comparative Example 1, the following steps were different from Example 1.
  • a non-doped amorphous silicon layer 2 having a thickness of 10 nm was formed on the back side of the single crystal silicon substrate 1. Thereafter, the hydrogen plasma treatment and the formation of the second non-doped amorphous silicon thin film layer were not performed, and the n-type amorphous silicon layer 3 was formed. Similarly, a non-doped amorphous silicon layer 4 having a thickness of 10 nm was formed on the surface side of the single crystal silicon substrate 1, and a p-type amorphous silicon layer 5 was formed thereon.
  • Comparative Example 2 a crystalline silicon-based photoelectric conversion device was manufactured as in Example 1. However, after hydrogen plasma treatment was performed directly on the single crystal silicon substrate 1, non-doped amorphous silicon layers 2 and 4 were produced. Each was formed to a film thickness of 10 nm by one film formation. That is, in Comparative Example 2, the following steps were different from Example 1.
  • non-doped amorphous silicon layer 2 Before the non-doped amorphous silicon layer 2 was formed, hydrogen plasma treatment was performed directly on the back surface side of the single crystal silicon substrate 1. The conditions for the hydrogen plasma treatment were the same as the conditions for the hydrogen plasma treatment of Example 1. Thereafter, a non-doped amorphous silicon layer 2 was formed with a thickness of 10 nm. Thereafter, the n-type amorphous silicon layer 3 was formed on the non-doped amorphous silicon layer 2 without performing hydrogen plasma treatment or forming a non-doped amorphous silicon thin film.
  • the single crystal silicon substrate 1 is subjected to hydrogen plasma treatment on the surface side, and then a non-doped amorphous silicon layer 4 is formed to a thickness of 10 nm, on which a p-type amorphous silicon layer 5 is formed. Formed.
  • Comparative Example 3 In Comparative Example 3, a crystalline silicon photoelectric conversion device was manufactured in the same manner as in Example 1. However, the first intrinsic silicon thin film layers 21 and 41 and the second intrinsic silicon thin film layers 22 and 42 were produced. Instead of hydrogen plasma treatment between the films, a non-doped amorphous silicon thin film was formed under high hydrogen concentration conditions. That is, the comparative example 3 was different from the example 1 in that the intrinsic silicon layers 2 and 4 were formed in the following steps.
  • a non-doped amorphous silicon thin film layer having a thickness of 4 nm was formed on one surface of the single crystal silicon substrate 1 as the first intrinsic silicon thin film layer 41. Thereafter, the SiH 4 / H 2 flow rate ratio is changed to 3/75, the high frequency power density is changed to 0.026 W / cm 2 while the plasma discharge is performed, and the non-doped amorphous silicon thin film having a thickness of 2 nm is changed. A layer (interface layer) was formed. Thereafter, the SiH 4 / H 2 flow rate ratio and the high frequency power density were changed, and a non-doped amorphous silicon thin film layer having a thickness of 4 nm was formed as the second intrinsic silicon thin film layer 42.
  • the film forming conditions for the non-doped amorphous silicon thin film layer 42 were the same as the film forming conditions for the non-doped amorphous silicon thin film layer 41.
  • a first non-doped amorphous silicon thin film layer 21 having a thickness of 4 nm, an interface layer having a thickness of 2 nm, and a non-doped amorphous film having a thickness of 4 nm are also provided.
  • the silicon thin film layer 22 was sequentially formed.
  • Comparative Example 4 In Comparative Example 4, as in Comparative Example 3, as the intrinsic silicon-based layers 2 and 4, a crystalline silicon-based material having a first non-doped amorphous silicon thin film layer, an interface layer, and a second non-doped amorphous silicon thin-film layer. A photoelectric conversion device was manufactured. However, Comparative Example 4 was different from Comparative Example 3 in that the film forming conditions of these layers were changed to the following (a) to (d).
  • the photoelectric conversion characteristics (open circuit voltage (Voc), short circuit current density (Jsc), fill factor (FF), and conversion efficiency (Eff)) of the photoelectric conversion devices obtained in Example 1 and Comparative Examples 1 to 4 Evaluation was performed using a simulator. Table 1 shows the evaluation results. Each photoelectric conversion characteristic in Table 1 is shown as a relative value with respect to Comparative Example 1.
  • Example 1 and Comparative Examples 1 and 2 the non-doped amorphous silicon layers 2 and 4 have the same total film thickness.
  • the photoelectric conversion device of Example 1 in which the hydrogen plasma treatment was performed after the formation of the first non-doped amorphous silicon thin film layer, the hydrogen plasma treatment was not performed, and the non-doped amorphous silicon layer 2 was formed by one film formation. Compared with the photoelectric conversion device of Comparative Example 1, the conversion efficiency was improved.
  • the photoelectric conversion device of Comparative Example 2 in which the hydrogen plasma treatment was directly performed on the single crystal silicon substrate before the non-doped amorphous silicon layer was formed has a lower conversion efficiency than the photoelectric conversion device of Comparative Example 1. Was.
  • Table 1 also shows the carrier lifetime measurement results of the photoelectric conversion devices of Example 1 and Comparative Examples 1 and 2.
  • the lifetime value has a high correlation with the open circuit voltage (Voc). It is considered that these differences are caused by the passivation effect of the single crystal silicon substrate, that is, the difference in interface defect density between the single crystal silicon substrate and the non-doped amorphous silicon layer.
  • the short circuit current densities of Example 1 and Comparative Examples 1 and 2 were within a range of ⁇ 1%, and no significant difference was observed. From this, it is considered that there is no significant difference between Example 1 and Comparative Examples 1 and 2 in the film physical properties such as optical characteristics of the non-doped amorphous silicon layer. From these results, in the manufacturing method of the present invention, the hydrogen plasma treatment reduces the defect density at the interface between the single crystal silicon substrate and the intrinsic silicon-based layer, which contributes to improvement in conversion efficiency. Conceivable.
  • Comparative Example 2 in which the hydrogen plasma treatment was directly performed on the single crystal silicon substrate, the open-circuit voltage was lower than that in Comparative Example 1 despite the hydrogen plasma treatment being performed. This is presumably because a good interface state is not obtained due to the influence of plasma damage to the surface of the single crystal silicon substrate.
  • the hydrogen plasma treatment is performed after the first non-doped amorphous silicon thin film layer is formed as in the first embodiment, the first non-doped amorphous silicon thin film layer acts as a protective layer to cause plasma damage. It is thought that the influence of is suppressed.
  • the manufacturing method of the present invention it is considered that plasma damage to the single crystal silicon substrate is suppressed, the hydrogen passivation effect is improved, and interface defects are reduced.
  • Comparative Example 3 in which the interface layer was formed under the high hydrogen condition between the first non-doped amorphous silicon thin film layer and the second non-doped amorphous silicon thin film layer, the conversion efficiency as in Example 1 was improved. There was no improvement, but rather the conversion efficiency was lower than that of Comparative Example 1. In Comparative Example 4, the same tendency as in Comparative Example 3 was observed. Since the high-frequency power density at the time of forming the interface layer in Comparative Example 3 is the same as the high-frequency power density in the hydrogen plasma processing step of Example 1, in Example 1, in a hydrogen gas atmosphere that does not substantially contain a source gas. It is thought that the fact that the plasma treatment step was performed contributed to the improvement of the conversion efficiency.
  • Examples 2 to 6 and Comparative Examples 5 and 6 A photoelectric conversion device was produced in the same manner as in Example 1 except that the film thicknesses of the first non-doped amorphous silicon thin film layers 21 and 41 were changed as shown in Table 2.
  • the photoelectric conversion characteristics of the photoelectric conversion devices of these Examples and Comparative Examples are shown in Table 2 together with the photoelectric conversion characteristics of the photoelectric conversion device of Example 1.
  • Each photoelectric conversion characteristic in Table 2 is shown as a relative value with respect to Comparative Example 1 described above.
  • the open-circuit voltage in the region where the film thickness of the first non-doped amorphous silicon thin film layer is 4 nm or less, the open-circuit voltage once increases as the film thickness increases, and when the film thickness exceeds 6 nm, the open-circuit voltage decreases.
  • the increase in open-circuit voltage accompanying the increase in the thickness of the first non-doped amorphous silicon thin film layer (first intrinsic silicon thin film layer) is caused by the influence of plasma damage on the surface of the single crystal silicon substrate by the first intrinsic silicon thin film layer. It is thought that this is due to the role as a protective layer that reduces the amount of light.
  • the film thickness of the first intrinsic silicon-based thin film layer is 6 nm or more, the open circuit voltage decreases because the hydrogen plasma treatment is performed as the film thickness of the first intrinsic silicon-based thin film layer increases. This is considered to be because the passivation effect and the interface defect reduction effect due to the above are blocked. From the above results, the film thickness of the first non-doped amorphous silicon thin film layer is particularly preferably in the range of 2 nm to 5 nm, and most preferably in the range of 2 to 4 nm.
  • Example 7 to 11 A photoelectric conversion device was produced in the same manner as in Example 1 except that the film thicknesses of the second non-doped amorphous silicon thin film layers 22 and 42 were changed as shown in Table 3.
  • each of the first non-doped amorphous silicon thin film layers 21 and 41 was formed with a film thickness of 4 nm, and then hydrogen plasma treatment was performed. Thereafter, the n-type amorphous silicon layer 3 and the p-type amorphous silicon layer 5 were formed without forming the second non-doped amorphous silicon thin film layers 22 and 42. Other than that was carried out similarly to Example 1, and produced the photoelectric conversion apparatus.
  • Table 3 shows the photoelectric conversion characteristics of the photoelectric conversion devices of Examples 7 to 11 and Comparative Example 7 together with the photoelectric conversion characteristics of the photoelectric conversion device of Example 1. Each photoelectric conversion characteristic in Table 3 is shown as a relative value with respect to Comparative Example 1 described above.
  • Comparative Example 7 in which the second non-doped amorphous silicon thin film layer (second intrinsic silicon-based thin film layer) was not formed, the photoelectric conversion characteristics, in particular, the open-circuit voltage was lowered as compared with each Example. This is considered to be due to the diffusion of doped impurity atoms when the conductive silicon-based layer is formed on the intrinsic silicon-based layer because the thickness of the intrinsic silicon-based layer is small.
  • the film thickness of the second intrinsic silicon-based thin film layer increases, the total film thickness with the first intrinsic silicon-based thin film layer (that is, the film thickness of the intrinsic silicon-based layer) increases.
  • the decrease in the short-circuit current is considered to be due to an increase in light absorption loss due to an increase in the thickness of the intrinsic silicon layer.
  • the decrease in the fill factor is considered to be due to an increase in resistance in the film thickness direction of the intrinsic silicon-based layer. From these results, the film thickness of the second intrinsic silicon thin film layer is set so that the short circuit current and the fill factor do not decrease excessively in consideration of the total film thickness with the first intrinsic silicon thin film layer. It can be said that it is preferable.
  • Example 12 to 19 A photoelectric conversion device was produced in the same manner as in Example 1 except that the high-frequency power density and the plasma treatment time in the hydrogen plasma treatment step were changed as shown in the fourth example.
  • the photoelectric conversion characteristics of the photoelectric conversion devices of these examples are shown in Table 4 together with the photoelectric conversion characteristics of the photoelectric conversion device of Example 1.
  • Each photoelectric conversion characteristic of Table 4 is shown as a relative value with respect to Comparative Example 1 described above.
  • the open-circuit voltage is mainly changed by changing the high-frequency power density and the plasma processing time in the hydrogen plasma processing step. This is considered to be because when the high frequency power density is low or when the plasma processing time is short, the hydrogen passivation and defect reduction effects by the hydrogen plasma processing are small and the open circuit voltage improvement effect is small. Conversely, if the high-frequency power density is excessively large or if the plasma treatment time is excessively long, the effect of plasma damage on the single crystal silicon surface will increase, offsetting the effect of increasing open-circuit voltage due to passivation and interface defect reduction. This is considered to be because of this.
  • Example 20 a crystalline silicon-based photoelectric conversion device was manufactured as in Example 1, but the first non-doped amorphous silicon thin film layers 21 and 41 were formed to a thickness of 2 nm, and hydrogen plasma treatment was performed. After being performed, the second non-doped amorphous silicon thin film layers 22 and 42 were different from Example 1 in that they were formed with a film thickness of 8 nm.
  • Reference Example 1 a crystalline silicon-based photoelectric conversion device was manufactured as in Example 20, but in the formation of the non-doped amorphous silicon layers 2 and 4, the formation of the non-doped amorphous silicon thin film layer and It was different from Example 20 in that the hydrogen plasma treatment was repeatedly performed. That is, in Reference Example 1, after a non-doped amorphous silicon thin film layer is formed with a thickness of 2 nm, hydrogen plasma treatment is performed, and thereafter, a non-doped amorphous silicon thin film layer with a thickness of 2 nm is further manufactured. A membrane and hydrogen plasma treatment was performed. An amorphous silicon layer having a thickness of 4 nm was further formed thereon. An n-type amorphous silicon layer 3 and a p-type amorphous silicon layer 5 were formed on the non-doped amorphous silicon layers 2 and 4 thus formed.
  • Reference Example 2 In Reference Example 2, as in Reference Example 1, the formation of the non-doped amorphous silicon thin film layer and the hydrogen plasma treatment were repeatedly performed. In Reference Example 2, after a non-doped amorphous silicon thin film layer having a thickness of 2 nm and a hydrogen plasma treatment were repeated three times, an amorphous silicon layer having a thickness of 2 nm was formed thereon. It was different from Reference Example 1 in that a film was formed.
  • Table 5 shows the total of the photoelectric conversion characteristics of the photoelectric conversion devices of Example 20 and Reference Examples 1 and 2 and the time (including plasma processing time) required to form the non-doped amorphous silicon layers 2 and 4.
  • Each photoelectric conversion characteristic and time in Table 6 are shown as relative values with respect to Example 16.
  • Example 16 and Reference Examples 1 and 2 There is no clear difference in photoelectric conversion characteristics between Example 16 and Reference Examples 1 and 2, and an improvement effect is seen by repeatedly forming the non-doped amorphous silicon thin film layer and hydrogen plasma treatment. There wasn't. From this, the improvement of the photoelectric conversion characteristics by the manufacturing method of the present invention is not due to the film quality improvement by chemical annealing, but the passivation effect of the surface of the single crystal silicon substrate by the hydrogen plasma treatment, the single crystal silicon substrate and the intrinsic silicon This is thought to be due to the effect of reducing defects at the interface with the system layer.
  • SYMBOLS 1 1 conductivity type (n type) single crystal silicon substrate 2 1 conductivity type (n type) layer side intrinsic silicon system layer 4 Reverse conductivity type (p type) layer side intrinsic silicon system layer 21, 41 1st intrinsic silicon system thin film layer 22, 42 Second intrinsic silicon-based thin film layer 3 One conductivity type (n-type) silicon-based layer 5 Reverse conductivity type (p-type) silicon-based layer 6, 8 Transparent electrode layer 7, 9 Collector electrode

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Abstract

La présente invention porte sur un procédé de fabrication d'un dispositif de conversion photoélectrique au silicium cristallin. Le dispositif de conversion photoélectrique au silicium cristallin selon la présente invention comprend une couche de silicium intrinsèque côté couche d'un premier type de conductivité et une couche de silicium du premier type de conductivité dans cet ordre sur une surface d'un substrat en silicium monocristallin du premier type de conductivité, tout en comprenant une couche de silicium intrinsèque côté couche du type de conductivité opposé et une couche de silicium du type de conductivité opposé dans cet ordre sur l'autre surface du substrat en silicium monocristallin du premier type de conductivité. L'étape de formation de la couche de silicium intrinsèque côté couche du premier type de conductivité et/ou l'étape de formation de la couche de silicium intrinsèque côté couche du type de conductivité opposé comprennent, dans l'ordre suivant : une étape à laquelle une première couche mince de silicium intrinsèque qui présente une épaisseur de film de 1-10 nm est formée sur le substrat en silicium monocristallin du premier type de conductivité par un procédé CVD assisté par plasma ; une étape à laquelle un traitement par plasma est réalisé dans une atmosphère gazeuse qui est principalement composée d'hydrogène ; et une étape à laquelle une seconde couche mince de silicium intrinsèque est formée sur la première couche mince de silicium intrinsèque par un procédé CVD assisté par plasma.
PCT/JP2011/069811 2010-10-01 2011-08-31 Procédé de fabrication de dispositif de conversion photoélectrique WO2012043124A1 (fr)

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ES11828685.5T ES2625473T3 (es) 2010-10-01 2011-08-31 Método para fabricar un dispositivo de conversión fotoeléctrica
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JPWO2014002256A1 (ja) * 2012-06-29 2016-05-30 パナソニックＩｐマネジメント株式会社 太陽電池
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JPWO2016052635A1 (ja) * 2014-09-30 2017-07-13 株式会社カネカ 結晶シリコン系太陽電池の製造方法、及び太陽電池モジュールの製造方法
WO2016052635A1 (fr) * 2014-09-30 2016-04-07 株式会社カネカ Procédé de fabrication de cellule solaire à base de silicium cristallin et procédé de fabrication de module de cellules solaires
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JPWO2017110456A1 (ja) * 2015-12-24 2018-08-09 株式会社カネカ 光電変換装置の製造方法
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US10658537B2 (en) 2015-12-24 2020-05-19 Kaneka Corporation Method for manufacturing photoelectric conversion device
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JPWO2012043124A1 (ja) 2014-02-06
US20130210185A1 (en) 2013-08-15
US8691613B2 (en) 2014-04-08
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EP2624307A4 (fr) 2014-08-13
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