WO2011158284A1 - スイッチング電源装置および半導体装置 - Google Patents
スイッチング電源装置および半導体装置 Download PDFInfo
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- WO2011158284A1 WO2011158284A1 PCT/JP2010/003962 JP2010003962W WO2011158284A1 WO 2011158284 A1 WO2011158284 A1 WO 2011158284A1 JP 2010003962 W JP2010003962 W JP 2010003962W WO 2011158284 A1 WO2011158284 A1 WO 2011158284A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/36—Means for starting or stopping converters
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/22—Conversion of dc power input into dc power output with intermediate conversion into ac
- H02M3/24—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters
- H02M3/28—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac
- H02M3/325—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal
- H02M3/335—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/33507—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters
- H02M3/33523—Conversion of dc power input into dc power output with intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode to produce the intermediate ac using devices of a triode or a transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of the output voltage or current, e.g. flyback converters with galvanic isolation between input and output of both the power stage and the feedback loop
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0048—Circuits or arrangements for reducing losses
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/10—Technologies improving the efficiency by using switched-mode power supplies [SMPS], i.e. efficient power electronics conversion e.g. power factor correction or reduction of losses in power supplies or efficient standby modes
Definitions
- the present invention relates to a switching power supply that generates an adjusted output voltage by intermittently performing a switching operation for supplying and cutting off an input voltage using a switching element, and a semiconductor device for controlling such a switching power supply.
- a switching power supply that generates an adjusted output voltage by intermittently performing a switching operation for supplying and cutting off an input voltage using a switching element, and a semiconductor device for controlling such a switching power supply.
- a switching power supply device having a semiconductor device that controls (stabilizes) a voltage is widely used.
- a low load state such as a standby load
- the energy loss as a switching power source is predominantly the switching loss due to the switching operation.
- One well-known technique for improving power supply efficiency at light loads such as standby loads is intermittent oscillation control in which switching operation is intermittently performed at light loads.
- FIG. 16 is a functional block diagram showing a configuration example of the switching power supply apparatus 900 including a control circuit 901 for performing general intermittent oscillation. With reference to the timing chart of FIG. 17, the switching operation by the intermittent oscillation control in the switching power supply apparatus 900 will be briefly described.
- the switching operation is performed by current mode quasi-resonant control (also referred to as bottom-on control).
- the quasi-resonant control in the current mode is to turn off the switching element 2 when the current ID flowing through the switching element 2 reaches a target value, and ringing generated in the switching element 2 when the switching element 2 is in the off state. This is control for turning on the switching element 2 at the bottom, which is the minimum point of the voltage.
- the bottom of the ringing voltage is detected by the bottom detection circuit 17 and indicated by the Bottom signal output from the bottom detection circuit 17.
- the output voltage V out increases as the output current I out decreases from the rated load state.
- a feedback signal I FB indicating the magnitude of the output voltage V out (for example, a current signal in an outflow direction that increases as the output voltage V out increases) is input from the output voltage detection circuit 6 to the FB terminal, and the feedback control circuit 12 Based on the feedback signal I FB , the control signal V EAO indicating a smaller limit value for the current I D flowing through the switching element 2 is output as the output voltage V out is higher.
- the intermittent oscillation control circuit 18 changes the Enable signal to the L level instructing the stop of the switching operation.
- the Enable signal becomes L level
- the Bottom signal is blocked by the turn-on control circuit 93. Thereby, the switching operation in the switching element 2 is stopped.
- the edge at which the Enable signal changes to the L level instructing the stop of the switching operation is also called an intermittent stop signal, and the stop of the switching operation in the intermittent oscillation control is also called the intermittent stop.
- the intermittent oscillation control circuit 18 changes the Enable signal to the H level that instructs execution of the switching operation.
- the intermittent return circuit 91 outputs an Up signal that is a one-shot pulse at the rising edge of the Enable signal.
- the switching element 2 is forcibly turned on by the Up signal, and thereafter, the switching operation by the pseudo resonance control in which the switching element 2 is turned on according to the Bottom signal from the bottom detection circuit 17 is executed.
- the edge at which the Enable signal changes to the H level instructing execution of the switching operation is also referred to as an intermittent return signal, and the restart of the switching operation in the intermittent oscillation control is also referred to as intermittent return.
- the second standby state in which the stop period of the switching operation is longer than that in the first standby state is set.
- the lighter the load the longer the intermittent control cycle composed of the execution period and the stop period of the switching operation of the switching element 2 is controlled.
- the intermittent recovery circuit 91 detects the ringing voltage generated in the switching element 2 in response to the Enable signal changing to the H level in order to restart the switching operation in the intermittent oscillation control. Outputs an Up signal irrespectively. Therefore, in the worst case, the switching element 2 may be turned on at the top, which is the maximum point of the ringing voltage, and the power loss generated in the switching element 2 becomes a problem.
- the switching element 2 includes
- This power loss will occur. This power loss is also referred to as power loss due to the capacitance C or loss due to the capacitance between the input and output of the switching element.
- performing intermittent oscillation control at light load is an effective means for improving the power supply efficiency at light load, but when the voltage at the time of turning on the switching element 2 is high at the time of intermittent recovery. As a result, a large power loss due to the capacitance C occurs. In particular, when the intermittent control period is shortened according to the load state, the power loss is increased.
- Patent Literature 1 and Patent Literature 2 disclose switching power supply devices that reduce power loss due to the capacitance C that can occur during intermittent recovery.
- FIG. 18 is a functional block diagram showing an example of the configuration of a conventional switching power supply device 910 that reduces power loss that may occur during intermittent recovery.
- the switching power supply device 910 is obtained by changing the switching power supply device 900 of FIG. 16 according to the concept disclosed in Patent Document 1 and Patent Document 2, and the intermittent return circuit 92 in the control circuit 911 is changed.
- FIG. 19A and 19B will be described with reference to the timing charts of FIGS. 19A and 19B when the switching power supply 910 of FIG. 18 is controlled according to the control method of Patent Document 1 and Patent Document 2.
- FIG. 19A is described with reference to the timing charts of FIGS. 19A and 19B when the switching power supply 910 of FIG. 18 is controlled according to the control method of Patent Document 1 and Patent Document 2.
- FIG. 19A is described with reference to the timing charts of FIGS. 19A and 19B when the switching power supply 910 of FIG. 18 is controlled according to the control method of Patent Document 1 and Patent Document 2.
- the intermittent return circuit 92 measures a predetermined waiting time t (transformer reset detection time in Patent Documents 1 and 2) starting from an intermittent stop signal (falling edge of the Enable signal).
- the intermittent return circuit 92 indicates that the waiting time t is being measured by outputting an L level Mask signal. If the intermittent return signal (rising edge of the Enable signal) arrives before the intermittent return circuit 92 finishes counting the waiting time t, the turn-on control circuit 94 outputs a Bottom signal output after the intermittent return signal (Patent Literature).
- the switching element 2 is turned on by outputting the 1 and 2 transformer reset signals as the TurnOn signal (FIG. 19A).
- the intermittent return circuit 92 uses the subsequent intermittent return signal as the one-shot pulse Up.
- a signal (intermittent end pulse of Patent Document 1 and Patent Document 2) is output, and the turn-on control circuit 94 outputs the Up signal as a TurnOn signal to turn on the switching element 2 (FIG. 19B).
- Patent Document 1 discloses a time constant circuit having a constant current source and a capacitor
- Patent Document 2 discloses a counter circuit for counting the number of bottoms of the ringing voltage. It is disclosed.
- the switching power supply device 910 can intermittently return at the bottom of the ringing voltage of the switching element when the intermittent return signal arrives within the waiting time starting from the intermittent stop signal. Therefore, the loss due to the capacitance between the input and output of the switching element is reduced during intermittent recovery.
- the switching power supply device 910 incorporating the concepts disclosed in Patent Document 1 and Patent Document 2 may cause the following problems. The problem will be described with reference to FIGS. 20 (a) and 20 (b).
- the loss at the time of intermittent return can be reduced, but if the number of counts is too large, the ringing of the voltage of the switching element 2 disappears as shown by the broken line A in FIG. The bottom is not detected after t and the inconvenience of being unable to return intermittently occurs.
- the layout area for configuring the counter also increases, which increases the cost of the semiconductor chip.
- Patent Document 1 and Patent Document 2 it is difficult to optimally set the circuit time constant and the number of counts for determining the waiting time t for all power supply specifications. It can be said that the concept of Patent Document 2 is effective only in a limited load range (intermittent oscillation region).
- the present invention has been made in view of such circumstances, and if the switching power supply device performs intermittent oscillation control and performs intermittent recovery based on bottom detection, the switching operation at the time of continuous oscillation is the conventional example. It can be applied not only to the quasi-resonant control mentioned above but also to a switching power supply device based on PWM control, PFM control, secondary duty control, etc., and depends on the capacity between the input and output of the switching element at the time of intermittent return.
- An object of the present invention is to provide a switching power supply device and a semiconductor device having a suitable configuration for reducing loss.
- one aspect of the semiconductor device of the present invention is configured to adjust the input DC voltage by intermittently performing a switching operation for supplying and blocking the input DC voltage using a switching element.
- a semiconductor device for controlling a switching power supply that converts to an output DC voltage, the intermittent oscillation control circuit alternately instructing execution and stop of the switching operation, and the switching element when the switching element is in an OFF state A bottom detection circuit for detecting a bottom that is a minimum point of the ringing voltage generated in the period, and a period in which the bottom of the ringing voltage is to be monitored, starting from the time when the execution of the switching operation is instructed from the intermittent oscillation control circuit
- a bottom monitoring time measuring circuit for measuring a bottom monitoring time which is the length of the bottom, and the bottom During measurement of the viewing time, only in response to the bottom of the ringing voltage by said bottom detecting circuit is detected, and a turn-on control circuit for turning on the switching element.
- the bottom monitoring time is measured from the time when the execution of the switching operation is instructed, and the bottom of the ringing voltage detected during the measurement of the bottom monitoring time. Since the switching element is turned on, after the elapse of the waiting time measured from the time when the stop of the switching operation is instructed, which is a conventional operation, regardless of whether the bottom of the ringing voltage can be detected or not. Compared with the case where the switching element is immediately turned on in response to an instruction to execute the switching operation, it is possible to reduce inconvenience that the switching element is turned on at a high voltage that is not the bottom of the ringing voltage. As a result, loss due to the capacitance between the input and output of the switching element at the time of intermittent return can be reduced.
- the bottom monitoring time counting circuit may count a length of one or more cycles of the ringing voltage as the bottom monitoring time.
- the switching element since the bottom of the ringing voltage is monitored for a length of one period or more of the ringing voltage, as long as the ringing of the switching element continues during the intermittent return, the switching element It can be reliably turned on at the bottom of the ringing voltage, so that power loss is minimized.
- the turn-on control circuit may turn on the switching element regardless of the bottom of the ringing voltage when the timing of the bottom monitoring time is completed.
- the switching element when the intermittent return is instructed, even if the voltage ringing of the switching element has disappeared, the switching element can be forcibly turned on to perform the intermittent return. it can. Furthermore, by measuring the length of the ringing voltage of one period or more as the bottom monitoring time, an effect of reliably reducing power loss by preventing forced turn-on too early can be obtained.
- the bottom monitoring time counting circuit may stop counting the bottom monitoring time in response to the gate signal of the switching element being turned on during the bottom monitoring time.
- the bottom monitoring time counting circuit may include a constant current source and a capacitor, and may count the bottom monitoring time based on a time constant determined by a current value of the constant current source and a capacitance value of the capacitor.
- Such a configuration is suitable when the bottom monitoring time is measured using an analog time constant circuit including a constant current source and a capacitor.
- the bottom monitoring time measuring circuit is a time from the first bottom to the second bottom of the ringing voltage detected by the bottom detection circuit after an instruction to stop the switching operation is given from the intermittent oscillation control circuit.
- the bottom monitoring time measuring circuit may measure a time corresponding to the measured ringing period as the bottom monitoring time.
- one period of the ringing voltage measured when the intermittent stop is performed is counted as the bottom monitoring time when the intermittent recovery is performed immediately after that, so that the response time when the intermittent recovery is performed can be set as the load time. It can be minimized by adapting to the situation.
- the ringing period measuring circuit includes a constant current source and a capacitor, and the capacitor is charged with a current generated by the constant current source in response to detection of the first bottom by the bottom detection circuit. And the charging of the capacitor may be stopped in response to detection of the second bottom by the bottom detection circuit.
- the measured ringing period can be held as the voltage value of the capacitor.
- the bottom monitoring time counting circuit starts discharging the capacitor with a current generated by the constant current source in response to an instruction to execute the switching operation from the intermittent oscillation control circuit.
- the timing of the bottom monitoring time may be completed when the voltage drops below the voltage at the start of charging by the ringing period measuring circuit.
- the time corresponding to the measured ringing period can be measured as the bottom monitoring time by using the voltage value held in the capacitor as a medium.
- the bottom monitoring time measuring circuit is configured to connect the capacitor to the ringing period measuring circuit in response to a gate signal of the switching element being turned on after the execution of the switching operation is instructed from the intermittent oscillation control circuit. You may initialize to the initial voltage which is a voltage at the time of the charge start by.
- timing of the bottom monitoring time is stopped, so that the bottom of the ringing voltage is detected and the switching element is turned on. Completion of timing of the bottom monitoring time can further avoid the problem that the switching element is turned on.
- the semiconductor device further includes an oscillation circuit that indicates when the switching element should be turned on or off by performing an oscillation operation regardless of the bottom of the ringing voltage, and the oscillation circuit includes the intermittent circuit
- the oscillation operation is stopped in response to an instruction from the oscillation control circuit to stop the switching operation, and after the execution of the switching operation is instructed from the intermittent oscillation control circuit, the gate signal of the switching element becomes on level. In response, the oscillation operation may be resumed.
- the semiconductor device may include the switching element, and the semiconductor device including the switching element may be formed on a single semiconductor substrate.
- control circuit of the switching power supply device can be realized with a smaller number of parts.
- the present invention can be realized not only as such a semiconductor device, but also by converting such an input AC voltage generated by switching the input DC voltage with the switching element into an output AC voltage. It can also be realized as a switching power supply device that includes a converter that converts the output AC voltage to the output DC voltage.
- the present invention can also be realized as a control method for controlling such a switching power supply device.
- the switching power supply for converting the input DC voltage to the adjusted output DC voltage is controlled by intermittently performing the switching operation of supplying and cutting off the input DC voltage using the switching element.
- the bottom monitoring time is measured from the time when the execution of the switching operation is instructed, and the bottom of the ringing voltage detected during the time of the bottom monitoring time is Turn on the switching element.
- the inconvenience in the conventional operation that is, the switching operation is performed regardless of whether or not the bottom of the ringing voltage can be detected after the elapse of the waiting time measured from the time when the stop of the switching operation is instructed.
- the switching element is immediately turned on in response to an instruction to execute, the inconvenience that the switching element is turned on at a high voltage that is not the bottom of the ringing voltage can be reduced.
- loss due to the capacitance between the input and output of the switching element at the time of intermittent return can be reduced.
- FIG. 1 is a functional block diagram showing a configuration example of a switching power supply device including the semiconductor device according to the first embodiment of the present invention.
- FIG. 2 is a circuit diagram showing a configuration example of the feedback control circuit in the semiconductor device of the first embodiment.
- FIG. 3 is a schematic diagram showing a current flowing through the switching element with respect to a feedback current in the switching power supply device including the semiconductor device of the first embodiment.
- FIG. 4 is a circuit diagram showing a configuration example of the intermittent oscillation control circuit in the semiconductor device of the first embodiment.
- FIG. 5 is a circuit diagram showing a configuration example of the bottom detection circuit in the semiconductor device of the first embodiment.
- FIG. 6 is a circuit diagram showing a configuration example of a bottom monitoring time measuring circuit in the semiconductor device of the first embodiment.
- FIG. 7A and 7B are timing charts for explaining an operation example of the switching power supply device including the semiconductor device of the first embodiment.
- FIG. 8 is a functional block diagram showing a configuration example of the switching power supply device including the semiconductor device according to the second embodiment of the present invention.
- FIG. 9 is a circuit diagram showing a configuration example of a bottom monitoring time measuring circuit including a ringing period measuring circuit in the semiconductor device of the second embodiment.
- FIGS. 10A and 10B are timing charts for explaining an operation example of the switching power supply device including the semiconductor device of the second embodiment.
- FIG. 11 is a functional block diagram showing a configuration example of the switching power supply device including the semiconductor device according to the third embodiment of the present invention.
- FIG. 12 is a circuit diagram showing a configuration example of a bottom monitoring time measuring circuit in the semiconductor device of the third embodiment.
- FIG. 13 is a circuit diagram showing a configuration example of an oscillation circuit in the semiconductor device of the third embodiment.
- FIG. 14 is a timing chart for explaining an operation example including one configuration example of the oscillation circuit in the semiconductor device of the third embodiment.
- FIGS. 15A and 15B are timing charts for explaining an operation example of the switching power supply device including the semiconductor device of the third embodiment.
- FIG. 16 is a functional block diagram showing a configuration example of a switching power supply device including a semiconductor device having a conventional intermittent oscillation control circuit.
- FIG. 17 is a timing chart for explaining a state of intermittent oscillation of a switching element in a switching power supply device including a semiconductor device having a conventional intermittent oscillation control circuit.
- FIG. 18 is a functional block diagram showing a configuration example of a switching power supply device including a semiconductor device having a conventional intermittent oscillation control circuit.
- FIGS. 19A and 19B are timing charts for explaining a preferable operation at the time of intermittent return in a switching power supply device including a semiconductor device having a conventional intermittent oscillation control circuit.
- FIGS. 20A and 20B are timing charts for explaining an operation which becomes a problem at the time of intermittent recovery in a switching power supply device including a semiconductor device having a conventional intermittent oscillation control circuit.
- Embodiment 1 A switching power supply device according to Embodiment 1 of the present invention will be described.
- FIG. 1 is a circuit diagram showing a configuration example of the switching power supply device 100 including the semiconductor device 101 according to the first embodiment.
- the semiconductor device 101 functions as a control circuit for the switching power supply device 100.
- a control circuit realized by the semiconductor device 101 is referred to as the control circuit 101 using the same reference numerals as those of the semiconductor device.
- the transformer 1 has a primary winding 1a, a secondary winding 1b, and an auxiliary winding 1c, and the polarities of the primary winding 1a and the secondary winding 1b are reversed.
- the AC voltage obtained from the secondary winding 1 b is converted into an output DC voltage by the output voltage generator 7 composed of the rectifier diode 7 a and the capacitor 7 b and supplied to the load 8.
- the switching power supply apparatus 100 is a flyback type.
- the switching element 2 is connected to the primary winding 1a, and the gate which is the control electrode of the switching element 2 is subjected to on / off switching control when a gate signal is given from the gate driver 24.
- the control circuit 101 includes a switching element 2.
- the switching element 2 is a switching element such as a power MOSFET, and may be integrated on the same semiconductor substrate together with other parts of the control circuit 101. Further, the semiconductor device functioning as the control circuit 101 has five terminals, ie, a DRAIN terminal, a GND terminal, a VCC terminal, an FB terminal, and a TR terminal as external input / output terminals.
- the DRAIN terminal is a terminal connected to the connection point between the primary winding 1 a of the transformer 1 and the switching element 2, that is, the drain of the switching element 2.
- the GND terminal is a terminal that connects the source of the switching element 2 and the GND of the control circuit 101 to the ground (ground) level, and is connected to the low potential side of the input DC voltage Vin.
- the VCC terminal is a terminal for connecting the output of the rectifying / smoothing circuit 4 composed of the rectifying diode 4a and the capacitor 4b and the regulator 9 built in the control circuit 101.
- the auxiliary winding 1c is switched by the switching operation of the switching element 2. This is a terminal for supplying the control circuit 101 with an auxiliary power supply voltage generated by rectifying and smoothing the AC voltage generated at the control circuit 101.
- the FB terminal is a terminal for supplying a feedback signal (for example, a current by a phototransistor) output from the output voltage detection circuit 6 to the feedback control circuit 12 of the control circuit 101.
- a feedback signal for example, a current by a phototransistor
- the TR terminal detects a ringing voltage generated after the switching element 2 is turned off and the secondary current no longer flows through the secondary winding 1b of the transformer 1, and generates a pulse for turning on the switching element 2.
- Reference numeral 17 denotes a terminal for supplying an input voltage used for detecting the ringing voltage.
- the voltage induced in the auxiliary winding 1c of the transformer 1 by the switching operation of the switching element 2 is constituted by resistors 5a and 5b. A voltage obtained by dividing by the auxiliary winding voltage dividing circuit 5 is applied.
- the auxiliary winding voltage dividing circuit 5 suppresses the input voltage to the TR terminal, and applies a current limit when the voltage of the auxiliary winding 1c fluctuates negatively by the resistor 5a, thereby latching up the control circuit 101. It is provided to prevent
- the Bottom signal which is a pulse signal output from the bottom detection circuit 17, is supplied to the set input S of the RS flip-flop 22 as a TurnOn signal via the turn-on control circuit 29. Due to this TurnOn signal, the output Q of the RS flip-flop 22 becomes H level, and the H level is applied to the first input of the NAND circuit 23.
- Regulator 9 DRAIN terminal of the switching element 2, VCC terminal, activation is connected between the internal circuit voltage source 10 of the stop circuit 11 and the control circuit 101, the input DC voltage V in via the transformer 1 DRAIN terminal Is applied to the capacitor 4b of the rectifying / smoothing circuit 4 that outputs the auxiliary power supply voltage VCC from the DRAIN terminal via the VCC terminal, thereby raising the auxiliary power supply voltage VCC.
- the current supply from the DRAIN terminal to the VCC terminal is cut, and the current supply to the internal circuit is performed by the capacitor 4b of the rectifying and smoothing circuit 4 that outputs the auxiliary power supply voltage VCC.
- the VCC terminal voltage drops to the stop voltage, current is supplied from the DRAIN terminal to the VCC terminal as before the start-up, and the VCC terminal voltage rises again.
- the internal circuit voltage source 10 is controlled by the regulator 9 so as to be a constant voltage.
- the start / stop circuit 11 monitors the voltage applied to the VCC terminal, and controls the oscillation and stop of the switching element 2 according to the voltage level of the VCC terminal.
- an H level signal is applied to the second input of the NAND circuit 23, and when the voltage at the VCC terminal drops to the stop voltage, the second input of the NAND circuit 23 is at the L level. Apply the signal.
- the feedback control circuit 12 outputs in response to a feedback signal output from the output voltage detection circuit 6 and applied via the FB terminal of the control circuit 101 (for example, I FB flowing out from the FB terminal to the output voltage detection circuit 6).
- the level of the current flowing through the switching element 2 is determined so as to stabilize the DC voltage V out, and the voltage V EAO representing the determined limit level is applied to the negative input of the comparator 13.
- the output voltage V EAO from the feedback control circuit 12 reduces the current flowing through the switching element 2 when the load is light and the output voltage V out increases, and when the output voltage V out decreases because the load is heavy. 2 is used for the control to increase the current flowing through 2.
- FIG. 2 is a circuit diagram showing an example of a specific circuit configuration of the feedback control circuit 12.
- the feedback control circuit 12 includes constant current sources 121 and 122, P-type MOSFETs 123 and 124, N-type MOSFETs 125, 129, 126 and 127, constant voltage sources 128 and 132, a resistor 133, and an NPN bipolar transistor 131.
- the N-type MOSFET 127, the resistor 133, the NPN bipolar transistor 131, and the constant voltage source 132 constitute an IV converter 130.
- the pair of P-type MOSFETs 123 and 124 and the pair of N-type MOSFETs 126 and 127 are current mirror circuits, respectively.
- the constant current sources 121 and 122 are for limiting current when the FB terminal is short-circuited to GND.
- the voltage V EAO that is voltage-converted by the IV converter 130 from the current I FB flowing out from the FB terminal is determined by the current flowing through the resistor 133 and varies according to Equation 2.
- V EAO Output voltage of IV converter
- V R0 Constant voltage value of constant voltage source 132
- V be Voltage between BEs of NPN bipolar transistor
- R 0 Resistance value of resistor 133
- I 0 Current flowing through resistor 133
- the current flowing through the switching element 2 is controlled as described above by the feedback signal from the output voltage detection circuit 6, that is, by the current IFB flowing out from the FB terminal.
- FIG. 3 is a graph showing the relationship between the current flowing through the resistor 133, that is, the FB terminal current I FB, and the limit level I LIMIT of the drain current flowing through the switching element 2. The description will be continued with reference to FIGS.
- the drain current detection circuit 14 which is a current detection circuit of the switching element 2, flows to the switching element 2 by detecting, for example, an ON voltage determined by the product of the drain current flowing through the switching element 2 and the ON resistance of the switching element 2. Detect drain current. Then, a voltage signal proportional to the magnitude of the drain current is applied to the plus input of the comparator 13. The comparator 13 outputs an H level signal to the first input of the AND circuit 16 when the output signal of the drain current detection circuit 14 becomes equal to the output voltage V EAO of the feedback control circuit 12.
- the on-time blanking pulse generation circuit 15 has a second input of the AND circuit 16 for a certain blanking time after the Gate signal output from the gate driver 24 becomes H level for turning on the switching element 2.
- the switching element 2 is prevented from being erroneously turned off due to erroneous detection of a capacitive spike current or the like due to the capacitance of the switching element 2 itself.
- a blanking signal of H level is output from the blanking pulse generation circuit 15 at the time of ON to the second input of the AND circuit 16.
- the on-time blanking pulse generation circuit 15 After the blanking time set by the on-time blanking pulse generation circuit 15 has elapsed since the switching element 2 was turned on, and the current of the limit level I LIMIT determined by the feedback control circuit 12 flows to the switching element 2. Since the input signals of the AND circuit 16 are both at the H level, the output signal from the AND circuit 16 is at the H level.
- FIG. 4 is a circuit diagram showing an example of a specific circuit configuration of the intermittent oscillation control circuit 18.
- the intermittent oscillation control circuit 18 includes constant current sources 181 and 182, a resistor 183, a comparator 184, and a P-type MOSFET 185.
- the constant current sources 181 and 182 output constant currents I 1 and I 2 , respectively, and the resistor 183 has a resistance value R 1 .
- the intermittent oscillation control circuit 18 compares the output voltage V EAO from the feedback control circuit 12 with the reference voltage V R1 of the comparator 184, and outputs the comparison result as an Enable signal.
- the reference voltage VR1 of the comparator has the following hysteresis. That is, when V EAO > V R1 , the Enable signal is at the H level, so the P-type MOSFET 185 is in the off state, and the reference voltage V R1 is
- Intermittent oscillation control circuit 18 in accordance with the hysteresis mentioned above, when V EAO is high, that is, outputs the H level of the Enable signal for instructing the switching operation state when the output load is heavy, when V EAO is low, that is, When the output load is light, an Enable signal of L level that instructs to stop the switching operation is output.
- the intermittent oscillation control circuit 18 applies the Enable signal to the second input of the AND circuit 21 and the bottom monitoring time measuring circuit 32.
- the bottom monitoring time counting circuit 32 counts the bottom monitoring time t starting from the rise of the Enable signal, and applies the Up signal, which is a pulse signal, to the OR circuit 20 when the timing of the bottom monitoring time t is completed.
- the OR circuit 20 applies an H level signal to the first input of the AND circuit 21 when at least one of the Bottom signal and the Up signal is at the H level.
- a specific circuit configuration example of the bottom monitoring time counting circuit 32 will be described in detail in the operation description of the switching power supply device 100 described later.
- FIG. 5 is a circuit diagram showing an example of a specific circuit configuration of the bottom detection circuit 17.
- the bottom detection circuit 17 includes constant current sources 171 and 172, a resistor 173, a comparator 174, a P-type MOSFET 175, and a pulse generator 176.
- the pulse generator 176 outputs a one-shot pulse at the falling edge of the input signal with a well-known configuration including three inverter circuits and a NOR circuit.
- the constant current sources 171 and 172 output constant currents I 3 and I 4 respectively, and the resistor 173 has a resistance value R 2 .
- a voltage induced in the auxiliary winding 1c of the transformer 1 by the switching operation of the switching element 2 is divided by the auxiliary winding voltage dividing circuit 5 constituted by the resistors 5a and 5b. dividing voltage V TR obtained is applied. This voltage V TR is compared with a reference voltage V R2 of the comparator 174.
- Reference voltage V R2 of the comparator 174 has a hysteresis as follows. That is, when the voltage at the TR terminal is V TR and V TR > V R2 , the output signal of the comparator 174 is at the H level, so the Bottom signal output from the pulse generator 176 is at the L level. Yes. At this time, P-type MOSFET175 is off, the reference voltage V R2 is
- the output signal from the comparator 174 switches from H level to L level.
- the pulse generator 176 outputs a Bottom signal that is a one-shot pulse at the falling edge of the output signal from the comparator 174. That is, the Bottom signal is output as a one-shot pulse signal when the voltage V TR at the TR terminal becomes lower than the reference voltage VR2 . Since the P-type MOSFET 175 is turned on, the reference voltage V R2 is
- the startup / stop circuit 11 applies an H level signal to the first input of the NAND circuit 23. Actually, the start pulse is output at this time, but the description is omitted here. Since an overload condition occurs at startup, an H level signal is applied from the intermittent oscillation control circuit 18 to the second input of the AND circuit 21.
- the Turn On signal of H level is applied to the set input S of the RS flip-flop 22 through the OR circuit 20 and the AND circuit 21 by the bottom detection circuit 17, the output Q of the RS flip-flop 22 is The signal becomes H level, and the H level signal is also applied to the first input of the NAND circuit 23.
- the output signal of the NAND circuit 23 becomes L level
- the output signal of the gate driver 24 becomes H level, and the switching element 2 is turned on.
- the output Q of the RS flip-flop 22 is switched to the L level, and the first input of the NAND circuit 23 becomes the L level, so that the output signal of the gate driver 24 becomes the L level, and the switching element 2 is turned off.
- the switching operation of the switching element 2 is performed by the signal processing as described above.
- the secondary winding 1b of the transformer 1 is connected to an output voltage generation unit 7 composed of a rectifier diode 7a and a capacitor 7b, and an alternating current induced in the secondary winding 1b by the switching operation of the switching element 2.
- the output DC voltage Vout is generated by rectifying and smoothing the voltage by the output voltage generator 7, and the output DC voltage Vout is supplied to the load 8.
- the output voltage detection circuit 6 is composed of, for example, a LED and a Zener diode or the like, detects the voltage level of the output DC voltage V out, the control circuit 101 is switched to the output DC voltage V out is stabilized to a predetermined voltage A feedback signal necessary for controlling the switching operation of the element 2 is output.
- an AC power of a commercial can be rectified by a rectifier such as a diode bridge, smoothed by the input capacitor, is the DC voltage V in, the transformer 1 for power conversion It is assumed that it is given to the primary winding 1a.
- control circuit 101 and the switching power supply device 100 configured as described above and shown in FIG. 1 will be described.
- a start-up pulse is generated based on the output signal from the start-stop circuit 11, and the switching element 2 is turned on.
- the output voltage Vout on the secondary side is low at the time of startup, the feedback signal from the output voltage detection circuit 6 is not applied to the feedback control circuit 12. Therefore, the output voltage V EAO of the IV converter 130 in the feedback control circuit 12 is set high, and the negative input voltage of the comparator 13 is set high.
- the energy stored in the primary winding 1a of the transformer 1 is transmitted to the secondary winding 1b when the switching element 2 is turned on. Thereafter, when the secondary current stops flowing in the secondary winding 1b, the inductance L of the primary winding 1a of the transformer 1 and the capacitance value of the resonance capacitor 31 connected between the DRAIN terminal and the source terminal of the switching element 2 Ringing, which is the determined resonance operation, is started.
- the bottom detection circuit 17 detects the drop of the drain voltage of the switching element 2, that is, the bottom of the ringing voltage, based on the timing at which the voltage of the auxiliary winding 1c of the transformer 1 switches from positive to negative. As a result, the TurnOn signal is applied to the set input S of the RS flip-flop 22, and the switching element 2 is turned on again.
- phase shift capacitor (not shown) is connected to the TR terminal to adjust the output timing of the Bottom signal by the bottom detection circuit 17, and when the DRAIN voltage of the switching element 2 becomes substantially zero volts, the switching element Preferably, 2 is turned on.
- the output voltage Vout increases.
- the output voltage detection circuit 6 controls the current IFB to flow out from the FB terminal of the control circuit 101 as a feedback signal.
- the conversion output voltage V EAO by the IV converter in the feedback control circuit 12 decreases, so the negative input voltage of the comparator 13 decreases, and therefore flows to the switching element 2.
- the current decreases.
- the on-duty of the switching element 2 changes to an appropriate state. That is, the switching element 2 is turned on by the Bottom signal from the bottom detection circuit 17, and the turning off is performed when the current flowing through the switching element 2 reaches a current level determined by the amount of current flowing out from the FB terminal. .
- control circuit 101 performs control such as controlling the current flowing through the switching element 2 and changing the on-duty in accordance with the power supplied to the load 8 of the switching power supply device.
- the output voltage V EAO of I-V converter 130 of the feedback control circuit 12 becomes lower than the reference voltage V R1 of the comparator 184 of the intermittent oscillation control circuit 18.
- the Enable signal switches from the H level instructing execution of the switching operation to the L level instructing stop of the switching operation.
- FIG. 6 is a circuit diagram showing a configuration example of the bottom monitoring time counting circuit 32. As shown in FIG.
- the bottom monitoring time counting circuit 32 includes an inverter circuit 321, a pulse generator 322, an RS flip-flop 323, a constant current source 324, a P-type MOSFET 325, an N-type MOSFET 326, a capacitor 327, and a buffer circuit 328.
- the constant current source 324 outputs a constant current of I 5, capacitor 327 has a capacitance value C 1.
- the Gate signal is periodically applied to the reset input of the RS flip-flop 323, and the output Q of the RS flip-flop 323 is kept at the H level.
- the N-type MOSFET 326 is turned on, the capacitor 327 is discharged, and an L level Up signal is output from the buffer circuit 328.
- the Enable signal applied to the bottom monitoring time measuring circuit 32 changes to L level, that is, when an intermittent stop signal arrives, the output of the inverter circuit 321 becomes H level.
- the set input of the RS flip-flop 323 remains at the L level, charging of the capacitor 327 is not started, and the Up signal does not change from the L level.
- the pulse generator 322 applies a one-shot pulse to the set input of the RS flip-flop 323 at the falling edge of the output signal of the inverter circuit 321, and the Q output of the RS flip-flop 323 becomes L level.
- the P-type MOSFET 325 is turned on, and the electric charge is stored in the capacitor 327 by the constant current source 324. Therefore, the voltage on the high potential side of the capacitor 327 is the current value of the constant current source 324 and the capacitance value of the capacitor 327. It rises at a speed corresponding to the determined time constant.
- the Up signal output from the bottom monitoring time measuring circuit 32 changes to the H level.
- the time from the arrival of the intermittent return signal until the Up signal changes to H level corresponds to the bottom monitoring time. That is, the bottom monitoring time counting circuit 32 counts the bottom monitoring time based on a time constant determined by the current value of the constant current source 324 and the capacitance value of the capacitor 327.
- the Gate signal of the switching element 2 is applied to the reset input R of the RS flip-flop 323. Therefore, when the switching operation is restarted during the time of the bottom monitoring time, the RS flip-flop 323 is reset by the Gate signal, and the N-type MOSFET 326 is turned on, whereby the charge of the capacitor 327 is instantaneously discharged. The time measurement is stopped. In this case, the Up signal output from the bottom monitoring time counting circuit 32 remains unchanged at the L level.
- the bottom monitoring time t which is the time from when the Enable signal changes to H level to when the Up signal changes to H level, is expressed by Equation 7.
- C 1 capacitance value of capacitor 327
- V th threshold value of buffer circuit 328
- I 5 current value flowing through constant current source 324
- the bottom monitoring time counting circuit 32 starts counting the bottom monitoring time t expressed by Expression 7. .
- the switching element 2 is turned on at the bottom of the ringing voltage.
- the Up signal output from the bottom monitoring time counting circuit 32 is maintained at the L level and does not change to the H level.
- the bottom monitoring time counting circuit 32 is When the bottom monitoring time t has elapsed, the Up signal is changed to the H level. Since the Up signal output from the bottom monitoring time counting circuit 32 is applied to the OR circuit 20 in FIG. 1, the TurnOn signal is applied to the set input S of the RS flip-flop 22 via the AND circuit 21 and switching is performed. Element 2 is turned on. At this time, the RS flip-flop 323 is reset by the Gate signal and the N-type MOSFET 326 is turned on, whereby the charge of the capacitor 327 is instantaneously discharged, and the Up signal changes to the L level.
- the bottom monitoring time counting circuit 32 changes the Up signal to the H level when the bottom monitoring time t elapses. Therefore, the switching element 2 is forcibly turned on.
- the bottom detection circuit 17 performs switching within the bottom monitoring time t counted by the bottom monitoring time counting circuit 32, starting from when the Enable signal changes from L level to H level.
- the bottom of the ringing voltage of the element 2 is detected, it is turned on at that timing, and the bottom of the ringing voltage of the switching element 2 is turned on by the bottom detection circuit 17 within the bottom monitoring time t counted by the bottom monitoring time counting circuit 32. Is not detected, the switching element 2 is forcibly turned on when the bottom monitoring time counting circuit 32 completes the timing of the bottom monitoring time t.
- the bottom monitoring time counting circuit 32 measures the bottom monitoring time t having a length equal to or longer than one cycle of the ringing of the switching element 2.
- the Enable signal of the intermittent oscillation control circuit 18 changes from L level to H level. If the bottom of the ringing voltage is detected by the bottom detection circuit 17 during one ringing cycle, the switching element 2 is always turned on by the Bottom signal applied from the bottom detection circuit 17. In other words, the switching element 2 is always turned on at the bottom of the ringing voltage as long as the ringing of the switching element 2 continues when the intermittent return signal arrives without performing the forced turn-on too early.
- a capacitor used for counting the bottom monitoring time t can be externally attached, and the adjustment range of the bottom monitoring time t may be expanded.
- the bottom of the ringing voltage of the switching element 2 is not detected by the bottom detection circuit 17 during one ringing cycle, it means that the ringing of the switching element 2 has already disappeared.
- the Up signal is output, the switching element 2 is turned on, and the switching operation is resumed.
- the voltage of the switching element 2 is equal to the input voltage V in, the switching element 2 will be turned on at a voltage V in.
- the state in which the voltage ringing of the switching element 2 disappears in this way is a state that occurs when the intermittent stop period is very long (that is, the frequency of intermittent return is very low).
- the capacity loss due to switching is negligibly small as a loss ratio.
- FIG. 8 is a circuit diagram showing a configuration example of the switching power supply device 200 including the semiconductor device 201 of the second embodiment.
- the semiconductor device 201 functions as a control circuit for the switching power supply device 200.
- a control circuit realized by the semiconductor device 201 is referred to as the control circuit 201 using the same reference numerals as those of the semiconductor device.
- a ringing period measuring circuit 34 is added inside the bottom monitoring time measuring circuit 33.
- the bottom monitoring time measuring circuit 32 measures the bottom monitoring time t expressed by Equation 7, whereas in the second embodiment, the ringing period measuring circuit 34 performs switching in the stop state of the switching operation. The time of one cycle of ringing of the element 2 is measured, and the time corresponding to the measured time is counted as the bottom monitoring time in the bottom monitoring time counting circuit 33.
- the basic idea for reducing the loss due to the capacitance between the input and output of the switching element 2 at the time of intermittent recovery is the same as that of the switching power supply device 100 described above in the switching power supply device 200. I will explain only.
- the components described in the first embodiment are denoted by the same reference numerals as those used in the first embodiment, and the description thereof is omitted as appropriate.
- FIG. 9 is a circuit diagram showing an example of a specific circuit configuration of the bottom monitoring time measuring circuit 33 including the ringing period measuring circuit 34. As shown in FIG.
- the Enable signal applied from the intermittent oscillation control circuit 18 is maintained at the H level, so that an L level signal is applied to the reset input R of the RS flip-flop 333 via the pulse generator 332. Applied. Further, since an H level Gate signal for turning on the switching element 2 is periodically applied to the set input S of the RS flip-flop 333, the output Q of the RS flip-flop 333 is kept at the H level.
- the N-type MOSFET 334 is in the on state, and the voltage Vc on the high potential side of the capacitor 337 is initialized to the initial voltage Vinit that is the voltage of the constant voltage source 335.
- the comparator 336 outputs an L level signal when the same voltage is applied to the plus input and the minus input.
- the bottom monitoring time counting circuit 33 outputs the signal output from the comparator 336 as an Up signal.
- the pulse generator 332 applies an H level pulse signal to the reset input R of the RS flip-flop 333.
- the output Q of the RS flip-flop 333 becomes L level, and the N-type MOSFET 334 is turned off.
- the P-type MOSFET 346 is turned off when an H level gate signal is applied via the inverter circuit 331.
- the pulse signal from the pulse generator 332 is also applied to the set input S of the RS flip-flop 341, and the output ⁇ Q of the RS flip-flop 341 becomes L level. As a result, the reset input R of the D flip-flop 343 becomes L level, and the D flip-flop 343 is released from the reset state and becomes operable.
- an H level gate signal is applied to the P-type MOSFET 347 via the inverter circuit 338, and the RS flip-flop 341 via the pulse generator 345.
- An L level signal is applied to the reset input R.
- the bottom detection circuit 17 applies the bottom signal to the clock input CK of the D flip-flop 343 as the first bottom of the ringing voltage of the switching element 2 is detected. Further, the ⁇ Bottom signal is applied to the clock input ⁇ CK of the D flip-flop 343 via the inverter 342. At this time, the output Q of the D flip-flop 343 is switched from the L level to the H level, the gate signal of the P-type MOSFET 347 is changed to the L level via the inverter circuit 338, and the P-type MOSFET 347 is turned on. Accordingly, electric charge is stored in the capacitor 337 at a constant speed from the constant current source 344 through the P-type MOSFET 347.
- the capacitor 337 is charged from the constant current source 344 during one ringing cycle of the switching element 2, and the capacitor 337 holds a voltage corresponding to the time of one ringing cycle.
- the P-type MOSFET 346 is turned on by being applied with the L level gate signal via the inverter circuit 331.
- the current of the constant current source 344 draws out the electric charge stored in the capacitor 337 at a constant speed by the N-type MOSFETs 348 and 349 constituting the mirror circuit.
- the mirror ratio of the N-type MOSFETs 348 and 349 is desirably 1: 1.
- the bottom monitoring time counting circuit 33 counts the time corresponding to the time of one ringing period of the switching element 2 as the bottom monitoring time.
- the timing chart of FIG. 10A when the Bottom signal arrives within one ringing period of the switching element 2 from the rise of the Enable signal, the timing chart of FIG. 10B shows the switching from the rise of the Enable signal. The case where the Bottom signal does not arrive within the time of one period of ringing of the element 2 is shown.
- the ringing period measurement circuit 34 performs the ringing period measurement circuit during the intermittent stop.
- the electric charge charged in the capacitor 337 in 34 is extracted at a constant rate, and the voltage Vc of the capacitor 337 gradually decreases.
- the Bottom signal is applied from the bottom detection circuit 17 before the voltage Vc of the capacitor 337 drops below the initial voltage Vinit (that is, the voltage of the constant voltage source 335).
- the TurnOn signal is applied to the set input S of the RS flip-flop 22 via the AND circuit 21, and the switching element 2 is Turn on.
- the switching element 2 when the bottom of the ringing voltage of the switching element 2 is detected by the bottom detection circuit 17 within one cycle time t of the ringing of the switching element 2 measured by the ringing period measuring circuit 34 when intermittently returning, the intermittent return is performed.
- the switching element 2 will turn on at the bottom of the ringing voltage. This is an operation in which the timing of the bottom monitoring time is stopped. In this operation, the Up signal output from the bottom monitoring time counting circuit 33 is maintained at the L level and does not change to the H level.
- the Up signal that is the output signal of the comparator 336 is H Become a level.
- the TurnOn signal is applied to the set input S of the RS flip-flop 22 via the AND circuit 21, and switching is performed.
- Element 2 is turned on. That is, when the signal from the bottom detection circuit 17 is not output within one cycle time t of the ringing of the switching element 2 measured by the ringing period measurement circuit 34 when intermittently returning, one cycle time of the ringing of the switching element 2 is output. After t, the switching element 2 is forcibly turned on.
- an H level Gate signal is applied to the set input S of the RS flip-flop 333 of the bottom monitoring time measuring circuit 33 shown in FIG. 9, and the N-type MOSFET 334 is connected to the RS flip-flop 333.
- An H level gate signal is applied from the output Q to turn it on, and the voltage Vc on the high potential side of the capacitor 337 is initialized to the initial voltage Vinit that is the voltage of the constant voltage source 335.
- the ringing cycle measuring circuit 34 measures one ringing cycle of the switching element 2, thereby expanding the applicable range compared to the first embodiment. It will be. That is, in the first embodiment, since the bottom monitoring time t is fixedly provided, it is difficult to set the optimum time for all power supply specifications, whereas in the second embodiment, the power supply specifications and the ambient temperature Even if the operating environment of the device changes, it is possible to monitor one cycle of the ringing of the switching element 2 and make the bottom monitoring time t follow the one cycle time of the ringing of the switching element 2. It is possible to adapt to.
- the second embodiment compared with the first embodiment, since it has a followability to the ringing period, excellent power supply characteristics such as high responsiveness at the time of sudden change of output load and small output ripple can be obtained. Can do.
- FIG. 11 is a circuit diagram showing a configuration example of the switching power supply device 300 including the semiconductor device of the third embodiment.
- the semiconductor device 301 functions as a control circuit for the switching power supply device 300.
- a control circuit realized by the semiconductor device 301 is referred to as the control circuit 301 by using the same reference numerals as those of the semiconductor device.
- the control circuit 301 of the third embodiment is different from the control circuit 101 of the first embodiment in that the oscillation circuit 26 is added and the bottom monitoring time counting circuit 35 is changed.
- the switching power supply device 100 and the switching power supply device 200 according to the first and second embodiments are adapted to quasi-resonant control in which the switching element 2 is turned on at the bottom of the ringing, whereas the switching power supply device 300 according to the third embodiment is It is assumed that it is applicable to PWM control.
- FIG. 12 is a circuit diagram showing an example of a specific circuit configuration of the bottom monitoring time measuring circuit 35 in FIG. Compared with the bottom monitoring time counting circuit 32 shown in FIG. 6, the bottom monitoring time counting circuit 35 has an AND circuit 351 and an OR circuit 352 added thereto, and the Bottom signal that arrives during the bottom monitoring time counting is used as the Up signal. It is the composition to output.
- FIG. 13 is a circuit diagram showing an example of a specific circuit configuration of the oscillation circuit 26.
- the Enable signal applied from the intermittent oscillation control circuit 18 is at the H level, that is, during execution of the switching operation, the L level signal is applied to the set input S of the RS flip-flop 262 via the inverter circuit 261.
- the Gate signal is applied to the reset input R of the RS flip-flop 262
- the output Q of the RS flip-flop 262 is kept at the L level.
- the N-type MOSFET 263 is in an OFF state because an L level gate signal is applied.
- the P-type MOSFETs 269 and 275 are both turned on when the L level gate signal is applied. Note that the Clock signal output from the pulse generator 276 is at the L level.
- the P-type MOSFET 268 is applied with an H level gate signal via the inverter circuit 272 and is turned off.
- the constant current I 7 due to the constant current source 265 through the P-type MOSFET269 is charged in the capacitor 264, the voltage Vb of the high potential side of the capacitor 264 rises.
- the constant current values of the constant current sources 266 and 267 are I 8 and I 9 , and the resistance value of the resistor 273 is R
- the reference voltage Va of the comparator 274 is changed from R ⁇ I 8 to R ⁇ (I 8 + I 9 ).
- the output of the comparator 274 changes from the L level to the H level, and accordingly, the P-type MOSFETs 275 and 269 are at the H level.
- the gate signal is applied to turn off.
- the P-type MOSFET 268 is turned on when an L level gate signal is applied via the inverter circuit 272.
- the constant current I 7 from the constant current source 265 flows to the N-type MOSFET 270 through the P-type MOSFET 268, and the constant current flows to the N-type MOSFET 271 constituting the mirror circuit. That is, the N-type MOSFET 271 draws charges at a constant speed from the capacitor 264, and the voltage Vb on the high potential side of the capacitor 264 decreases.
- the reference voltage Va of the comparator 274 is changed from R ⁇ (I 8 + I 9 ) to R ⁇ I 8 .
- the voltage Vb on the high potential side of the capacitor 264 becomes a triangular wave, and the clock signal is output by the pulse generator 276 at the timing when the output signal of the comparator 274 switches from the H level to the L level.
- the clock signal is output from the oscillation circuit 26 at a constant cycle in this way.
- the set input S of the RS flip-flop 262 is input to the set input S of the RS flip-flop 262 via the inverter circuit 261.
- a signal is applied. Accordingly, the output Q of the RS flip-flop 262 becomes H level, the N-type MOSFET 263 is turned on, and the voltage Vb on the high potential side of the capacitor 264 is fixed to the GND level.
- FIG. 14 shows an example of waveforms of the voltage Vb, the Clock signal, the Enable signal, the Gate signal, the Reset signal, the Up signal, and the TurnOn signal applied to the reset input R of the RS flip-flop 22 in FIG. .
- the Clock signal is applied to the set input S of the RS flip-flop 22 as the TurnOn signal, and the Gate signal is output.
- the Enable signal changes to the L level, the voltage Vb of the capacitor 264 in the oscillation circuit 26 becomes the GND level.
- the bottom monitoring time counting circuit 35 causes the Enable signal to rise.
- the bottom monitoring time t is counted as a starting point, and when the timing of the bottom monitoring time t is completed, an H level Up signal is output via the OR circuit 352.
- the Bottom monitoring time counting circuit 35 completes the bottom monitoring time t and completes the Bottom monitoring time t.
- the Bottom signal is output as an Up signal via the OR circuit 352.
- the TurnOn signal is applied to the set input S of the RS flip-flop 22 via the OR circuit 20 and the AND circuit 21 in FIG. 2 turns on.
- the Gate signal is applied to the reset input R of the RS flip-flop 323 in the bottom monitoring time measuring circuit 35, and the Up signal which is the output Q of the RS flip-flop 323 is switched to the L level.
- the Gate signal is also applied to the reset input R of the RS flip-flop 262 in the oscillation circuit 26. Therefore, the output Q of the RS flip-flop 262 changes to the L level, and the N-type MOSFET 263 switches to the off state. At the same time, the constant current I 7 of the constant current source 265 is charged in the capacitor 264 through the P-type MOSFET 269, and the voltage Vb on the high voltage side of the capacitor 264 increases. In this way, the switching operation is resumed.
- FIGS. 15A and 15B are timing charts including the waveform of the drain voltage of the switching element 2. As in the timing charts of FIGS. The case where the Bottom signal arrives within the bottom monitoring time represented (FIG. 15A) and the case where the Bottom signal does not arrive within the bottom monitoring time (FIG. 15B) are shown.
- the switching element 2 detects the bottom of the detected ringing voltage. Will turn on.
- the bottom monitoring time measuring circuit 35 determines the bottom monitoring time.
- the output of the buffer circuit 328 becomes H level, and an H level Up signal is output via the OR circuit 352, whereby the switching element 2 is turned on.
- the time is measured by the bottom monitoring time counting circuit 35.
- the bottom detection circuit 17 turns on at that timing and detects the bottom within the bottom monitoring time t measured by the bottom monitoring time counting circuit 35.
- the switching element 2 is controlled to be forcibly turned on after the bottom monitoring time t counted by the bottom monitoring time counting circuit 35.
- the time for the bottom detection of the switching element 2 by the bottom detection circuit 17 at the time of intermittent return is set to the time for one period of the ringing of the switching element 2 using the ringing period measurement circuit 34. It does not matter.
- PWM control has been described in the second embodiment, it is also effective for switching power supply control methods such as PFM control and secondary duty control.
- the switching power supply device and the semiconductor device of the present invention are effectively used for a switching power supply device such as an AC-DC converter and a DC-DC converter.
Abstract
Description
本発明の実施の形態1のスイッチング電源装置を説明する。
VEAO:I-Vコンバータの出力電圧
VR0:定電圧源132の定電圧値
Vbe:NPNバイポーラトランジスタのBE間電圧
R0:抵抗133の抵抗値
I0:抵抗133に流れる電流
C1:コンデンサ327の容量値
Vth:バッファ回路328の閾値
I5:定電流源324に流れる電流値
次に、本発明の実施の形態2のスイッチング電源装置を説明する。
本発明の実施の形態3のスイッチング電源装置を説明する。
1a 一次巻線
1b 二次巻線
1c 補助巻線
2 スイッチング素子
4 整流平滑回路
4a、7a 整流ダイオード
4b、7b、31、264、327、337 コンデンサ
5 補助巻線電圧分圧回路
5a、5b、133、173、183、273 抵抗
6 出力電圧検出回路
7 出力電圧生成部
8 負荷
9 レギュレータ
10 内部回路電圧源
11 起動停止回路
12 フィードバック制御回路
13、174、184、274、336 比較器
14 ドレイン電流検出回路
15 オン時ブランキングパルス発生回路
16、21、351 AND回路
17 ボトム検出回路
18 間欠発振制御回路
20、352 OR回路
22、262、323、333、341 RSフリップフロップ
23 NAND回路
24 ゲートドライバ
26 発振回路
121、122、171、172、181、182、265、266、267、324、344 定電流源
29 ターンオン制御回路
32、33、35 ボトム監視時間計時回路
34 リンギング周期測定回路
91、92、 間欠復帰回路
100、200、300、900、910 スイッチング電源装置
101、201、301、901、911 制御回路(半導体装置)
123、124、175、185、268、269、275、325、346、347 P型MOSFET
125、126、127、129、263、270、271、326、334、348、349 N型MOSFET
128、132、335 定電圧源
130 I-Vコンバータ
131 NPNバイポーラトランジスタ
176、276、322、332、345 パルス発生器
261、272、321、331、338、342 インバータ回路
328 バッファ回路
343 Dフリップフロップ
Claims (14)
- スイッチング素子を用いて入力直流電圧を供給および遮断するスイッチング動作を間欠的に行うことにより前記入力直流電圧を調整された出力直流電圧に変換するスイッチング電源を制御するための半導体装置であって、
前記スイッチング動作の実行および停止を交互に指示する間欠発振制御回路と、
前記スイッチング素子がオフ状態にあるときに前記スイッチング素子に発生するリンギング電圧の極小点であるボトムを検出するボトム検出回路と、
前記間欠発振制御回路から前記スイッチング動作の実行が指示された時点を起点として、前記リンギング電圧のボトムが監視されるべき期間の長さであるボトム監視時間を計時するボトム監視時間計時回路と、
前記ボトム監視時間の計時中は、前記ボトム検出回路にて前記リンギング電圧のボトムが検出されるに応じてのみ、前記スイッチング素子をターンオンさせるターンオン制御回路と
を備える半導体装置。 - 前記ボトム監視時間計時回路は、前記ボトム監視時間として前記リンギング電圧の1周期以上の長さを計時する
請求項1に記載の半導体装置。 - 前記ターンオン制御回路は、前記ボトム監視時間の計時が完了したときに、前記リンギング電圧のボトムとは無関係に、前記スイッチング素子をターンオンさせる
請求項1および請求項2に記載の半導体装置。 - 前記ボトム監視時間計時回路は、前記ボトム監視時間の計時中に前記スイッチング素子のゲート信号がオンレベルになるに応じて前記ボトム監視時間の計時を中止する
請求項1から請求項3のいずれか1項に記載の半導体装置。 - 前記ボトム監視時間計時回路は、定電流源とコンデンサとを有し、前記定電流源の電流値と前記コンデンサの容量値とで決まる時定数により前記ボトム監視時間を計時する
請求項1から請求項4のいずれか1項に記載の半導体装置。 - 前記ボトム監視時間計時回路は、前記間欠発振制御回路から前記スイッチング動作の停止が指示された後、前記ボトム検出回路で検出される前記リンギング電圧の最初のボトムから2番目のボトムまでの時間をリンギング周期として測定するリンギング周期測定回路を有し、
前記ボトム監視時間計時回路は、前記測定されたリンギング周期に対応する長さの時間を前記ボトム監視時間として計時する
請求項1に記載の半導体装置。 - 前記リンギング周期測定回路は、定電流源とコンデンサとを有し、前記ボトム検出回路で前記最初のボトムが検出されるに応じて前記定電流源にて生成される電流で前記コンデンサの充電を開始し、前記ボトム検出回路で前記2番目のボトムが検出されるに応じて前記コンデンサの充電を停止する
請求項6に記載の半導体装置。 - 前記ボトム監視時間計時回路は、前記間欠発振制御回路から前記スイッチング動作の実行が指示されるに応じて前記定電流源にて生成される電流で前記コンデンサの放電を開始し、前記コンデンサの電圧が、前記リンギング周期測定回路による充電開始時の電圧以下に低下したときに前記ボトム監視時間の計時を完了する
請求項7に記載の半導体装置。 - 前記ボトム監視時間計時回路は、前記間欠発振制御回路から前記スイッチング動作の実行が指示された後、前記スイッチング素子のゲート信号がオンレベルになるに応じて、前記コンデンサを前記リンギング周期測定回路による充電開始時の電圧である初期電圧に初期化する
請求項6から請求項8のいずれか1項に記載の半導体装置。 - 前記半導体装置は、さらに、
前記リンギング電圧のボトムとは無関係に発振動作を行うことによって、前記スイッチング素子がターンオンまたはターンオフすべき時点を指示する発振回路を備え、
前記発振回路は、前記間欠発振制御回路からスイッチング動作の停止が指示されるに応じて前記発振動作を停止し、前記間欠発振制御回路からスイッチング動作の実行が指示された後、前記スイッチング素子のゲート信号がオンレベルになるに応じて、前記発振動作を再開する
請求項1に記載の半導体装置。 - 前記半導体装置は、前記スイッチング素子を含み、
前記スイッチング素子を含む前記半導体装置は、1つの半導体基板上に形成されている
請求項1から請求項10のいずれか1項に記載の半導体装置。 - 請求項1から請求項11のいずれか1項に記載の半導体装置と、
前記入力直流電圧を前記スイッチング素子にてスイッチングすることにより生成された入力交流電圧を出力交流電圧に変換する変換器と、
前記出力交流電圧を前記出力直流電圧に変換する平滑回路と
を備えるスイッチング電源装置。 - スイッチング素子を用いて入力直流電圧を供給および遮断するスイッチング動作を間欠的に行うことにより前記入力直流電圧を調整された出力直流電圧に変換するスイッチング電源を制御するための制御方法であって、
前記スイッチング動作の実行および停止を交互に指示する間欠発振制御ステップと、
前記スイッチング素子がオフ状態にあるときに前記スイッチング素子に発生するリンギング電圧の極小点であるボトムを検出するボトム検出ステップと、
前記間欠発振制御ステップにて前記スイッチング動作の実行が指示された時点を起点として、前記リンギング電圧のボトムが監視されるべき期間の長さであるボトム監視時間を計時するボトム監視時間計時ステップと、
前記ボトム監視時間の計時中は、前記ボトム検出ステップにて前記リンギング電圧のボトムが検出されるに応じてのみ、前記スイッチング素子をターンオンさせるターンオン制御ステップと
を含む制御方法。 - さらに、前記ボトム監視時間の計時が完了したときに、前記リンギング電圧のボトムとは無関係に、前記スイッチング素子をターンオンさせる強制ターンオン制御ステップを含む
請求項13に記載の制御方法。
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