WO2011132418A1 - 成膜方法 - Google Patents
成膜方法 Download PDFInfo
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- WO2011132418A1 WO2011132418A1 PCT/JP2011/002321 JP2011002321W WO2011132418A1 WO 2011132418 A1 WO2011132418 A1 WO 2011132418A1 JP 2011002321 W JP2011002321 W JP 2011002321W WO 2011132418 A1 WO2011132418 A1 WO 2011132418A1
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- Prior art keywords
- target
- film
- film forming
- thin film
- sputtering
- Prior art date
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- 238000000151 deposition Methods 0.000 title abstract description 5
- 239000010409 thin film Substances 0.000 claims abstract description 73
- 239000000758 substrate Substances 0.000 claims abstract description 53
- 229910044991 metal oxide Inorganic materials 0.000 claims abstract description 27
- 150000004706 metal oxides Chemical class 0.000 claims abstract description 27
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 claims abstract description 27
- 229910001868 water Inorganic materials 0.000 claims abstract description 22
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- 238000004544 sputter deposition Methods 0.000 claims description 73
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- 229910052738 indium Inorganic materials 0.000 claims description 34
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 claims description 33
- 229910052751 metal Inorganic materials 0.000 claims description 29
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- 238000004519 manufacturing process Methods 0.000 claims description 26
- 239000002184 metal Substances 0.000 claims description 26
- 239000001301 oxygen Substances 0.000 claims description 26
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 claims description 25
- 229910052725 zinc Inorganic materials 0.000 claims description 24
- HCHKCACWOHOZIP-UHFFFAOYSA-N Zinc Chemical compound [Zn] HCHKCACWOHOZIP-UHFFFAOYSA-N 0.000 claims description 23
- ATJFFYVFTNAWJD-UHFFFAOYSA-N Tin Chemical compound [Sn] ATJFFYVFTNAWJD-UHFFFAOYSA-N 0.000 claims description 15
- GYHNNYVSQQEPJS-UHFFFAOYSA-N Gallium Chemical compound [Ga] GYHNNYVSQQEPJS-UHFFFAOYSA-N 0.000 claims description 14
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- 238000000137 annealing Methods 0.000 claims description 13
- 239000012528 membrane Substances 0.000 claims 1
- 239000010410 layer Substances 0.000 description 29
- 230000000052 comparative effect Effects 0.000 description 10
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical group [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 9
- 238000010438 heat treatment Methods 0.000 description 9
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- 230000000694 effects Effects 0.000 description 6
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- 238000001755 magnetron sputter deposition Methods 0.000 description 6
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- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 4
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- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
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- 229910052804 chromium Inorganic materials 0.000 description 3
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- 230000008021 deposition Effects 0.000 description 3
- 239000001257 hydrogen Substances 0.000 description 3
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- 229910052719 titanium Inorganic materials 0.000 description 3
- 238000001039 wet etching Methods 0.000 description 3
- 239000011787 zinc oxide Substances 0.000 description 3
- 229910018072 Al 2 O 3 Inorganic materials 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 description 2
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 2
- 230000008901 benefit Effects 0.000 description 2
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- 238000001312 dry etching Methods 0.000 description 2
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- 229910052759 nickel Inorganic materials 0.000 description 2
- 229910052757 nitrogen Inorganic materials 0.000 description 2
- 239000002245 particle Substances 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 239000000523 sample Substances 0.000 description 2
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- OFIYHXOOOISSDN-UHFFFAOYSA-N tellanylidenegallium Chemical compound [Te]=[Ga] OFIYHXOOOISSDN-UHFFFAOYSA-N 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- 241001175904 Labeo bata Species 0.000 description 1
- 229910018068 Li 2 O Inorganic materials 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- 229910006404 SnO 2 Inorganic materials 0.000 description 1
- 229910002367 SrTiO Inorganic materials 0.000 description 1
- -1 Ta 2 O 5 Inorganic materials 0.000 description 1
- 229910010413 TiO 2 Inorganic materials 0.000 description 1
- 229910000147 aluminium phosphate Inorganic materials 0.000 description 1
- 229910052788 barium Inorganic materials 0.000 description 1
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- 238000011161 development Methods 0.000 description 1
- AJNVQOSZGJRYEI-UHFFFAOYSA-N digallium;oxygen(2-) Chemical compound [O-2].[O-2].[O-2].[Ga+3].[Ga+3] AJNVQOSZGJRYEI-UHFFFAOYSA-N 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 238000009826 distribution Methods 0.000 description 1
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- 238000011156 evaluation Methods 0.000 description 1
- 229910001195 gallium oxide Inorganic materials 0.000 description 1
- 229910052732 germanium Inorganic materials 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 229910052735 hafnium Inorganic materials 0.000 description 1
- 230000006872 improvement Effects 0.000 description 1
- 229910003437 indium oxide Inorganic materials 0.000 description 1
- PJXISJQVUVHSOJ-UHFFFAOYSA-N indium(iii) oxide Chemical compound [O-2].[O-2].[O-2].[In+3].[In+3] PJXISJQVUVHSOJ-UHFFFAOYSA-N 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000005001 laminate film Substances 0.000 description 1
- 229910052747 lanthanoid Inorganic materials 0.000 description 1
- 150000002602 lanthanoids Chemical class 0.000 description 1
- 229910052749 magnesium Inorganic materials 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012545 processing Methods 0.000 description 1
- 229910052761 rare earth metal Inorganic materials 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 229910052706 scandium Inorganic materials 0.000 description 1
- 229910052708 sodium Inorganic materials 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 229910052712 strontium Inorganic materials 0.000 description 1
- 239000000126 substance Substances 0.000 description 1
- 229910052726 zirconium Inorganic materials 0.000 description 1
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
Definitions
- the present invention relates to a film forming method.
- Field effect transistors are widely used as unit electronic elements, high-frequency signal amplifying elements, liquid crystal driving elements, etc. for semiconductor memory integrated circuits, and are the most widely used electronic devices at present.
- LCD liquid crystal display devices
- EL electroluminescence display devices
- FED field emission displays
- TFTs Thin film transistors
- an amorphous silicon-based semiconductor thin film has been used in a liquid crystal driving transistor of a large liquid crystal display device.
- amorphous silicon is lacking in mobility, so that image writing is not in time.
- organic electroluminescence (organic EL) displays a technology for increasing the size is in progress, and a material having a large area, a uniform area, and high mobility is required more than ever for the backplane. Therefore, a transparent semiconductor thin film made of a metal oxide, particularly an oxide made of indium oxide, zinc oxide, or gallium oxide, which can be enlarged as an amorphous silicon-based semiconductor thin film and has the second highest mobility after crystalline silicon.
- Semiconductor thin films are attracting attention.
- an oxide semiconductor film used for a TFT active layer is generally formed in an atmosphere into which oxygen gas is introduced in order to control electrical characteristics of the film.
- oxygen gas is introduced in order to control electrical characteristics of the film.
- the carrier concentration in the film changes greatly due to a slight fluctuation of the oxygen partial pressure, and the semiconductor characteristics fluctuate.
- Patent Document 1 As a means for solving this problem, it is known to increase the power density at the time of sputter film formation to moderate the oxygen partial pressure dependence of the carrier concentration in the film (Patent Document 1). However, when the power density is increased, the film formation rate is increased and the oxygen supply rate is relatively decreased, so that the carrier concentration in the film is approximately 10 18 cm ⁇ 3 or more. There was a problem that good characteristics could not be obtained.
- the carrier concentration 10 18 cm ⁇ 3 or less.
- the oxygen partial pressure must be increased.
- the film forming speed is lowered and the productivity is deteriorated. Therefore, it has been difficult to manufacture a favorable thin film transistor using an oxide semiconductor in a state where the power density at the time of sputtering film formation is increased and the film formation speed is increased.
- Patent Document 3 discloses an amorphous oxide semiconductor containing at least one of In and Zn, and hydrogen. However, these are all technologies applied to a target of 4 inches or less, and there is room for improvement in high-speed film formation assuming actual production.
- a thin film transistor having a bottom gate configuration and a bottom contact configuration is disclosed.
- a thin film transistor formed by introducing a partial pressure of water vapor has an electric field mobility of about 3 cm 2 / Vs, which is lower than that when oxygen is introduced, and is not suitable for use in a large-area and high-definition display device. It is enough.
- the size of the base when manufacturing flat displays such as liquid crystal displays is increasing year by year due to the increase in size of the display and intense cost reduction competition.
- liquid crystals using a glass base of 3 m square or more are used. Panel manufacturing is needed.
- the substrate size is increased, it becomes difficult to uniformly form the film thickness and film quality of the channel layer (semiconductor layer), and another variation in characteristics due to non-uniform film thickness and film quality increases. was there.
- Non-patent Document 1 when manufacturing a channel etch type transistor with a low manufacturing cost, the channel layer (semiconductor layer) is exposed to an etching solution, so that the problem of non-uniformity when the base is enlarged is significant (non- Patent Document 2).
- a channel layer is usually formed with a thin film thickness of 50 nm or less (Non-Patent Document 3), and a thick film of the channel layer is thick (for example, 50 nm or more, further Thin film transistors having good characteristics such as mobility and threshold voltage have been demanded.
- Patent Documents 4 and 5 disclose production examples of large area ITO using an AC sputtering apparatus.
- control of oxygen vacancies is more important, and it has been unclear how the carrier concentration of the semiconductor affects the power and frequency.
- An object of the present invention is to provide a method for forming an oxide semiconductor film that does not decrease the film formation speed even when the power density at the time of sputtering film formation is high and suppresses the carrier concentration in the film to 10 18 cm ⁇ 3 or less. Is to provide.
- Another object of the present invention is to provide a thin film transistor having good transistor characteristics such as mobility even when the channel layer (semiconductor layer) is thick.
- the inventors of the present invention have introduced a film without reducing the film formation speed even when the power density at the time of sputtering film formation is high by appropriately introducing water vapor instead of introducing oxygen at the time of sputtering film formation. It was found that the carrier concentration inside can be 10 18 cm ⁇ 3 or less. Further, the present inventors have found a method for manufacturing a semiconductor film that is stable without extending the manufacturing time by using the film forming method.
- the following film forming method and the like are provided.
- 3. The film forming method according to 1 or 2, wherein the sputtering is direct current sputtering. 4).
- the film forming method according to 3 wherein the direct current power density is 1 to 5 W / cm 2 . 6).
- the substrate is sequentially transferred to a position facing three or more targets arranged in parallel in the vacuum chamber at a predetermined interval, A method of forming a thin film on the surface of the substrate by alternately applying a negative potential and a positive potential to each target from an AC power source to generate plasma on the target,
- the film formation method according to 4 wherein the film formation is performed while switching a target to which a potential is applied between two or more targets branched and connected to at least one of the outputs from the AC power source. . 7).
- the metal oxide contains at least one element selected from the group consisting of gallium element (Ga), zinc element (Zn) and tin element (Sn), and indium element (In), 12.
- the film forming method according to any one of 1 to 11, wherein the indium element content in the target satisfies the following atomic ratio. 0.2 ⁇ [In] / all metal atoms ⁇ 0.8 (In the formula, [In] is the number of atoms of indium element in the target. The total metal atom is the number of atoms of all metal atoms included in the target. ) 13.
- the metal oxide contains indium element (In), gallium element (Ga) and zinc element (Zn); 12.
- the film forming method according to any one of 1 to 11, wherein the contents of indium element, gallium element and zinc element in the target satisfy the following atomic ratio. 0 ⁇ [In] / [Ga] ⁇ 0.5 0.2 ⁇ [In] / ([In] + [Ga] + [Zn]) ⁇ 0.9 (In the formula, [In] is the number of atoms of indium element in the target, [Ga] is the number of atoms of gallium element in the target, and [Zn] is the number of atoms of zinc element in the target.) 14
- the metal oxide contains indium element (In), tin element (Sn), and zinc element (Zn), 12.
- a method for producing an oxide semiconductor thin film comprising annealing a thin film obtained by the film forming method according to any one of 1 to 14 at 150 to 400 ° C. for 5 to 120 minutes. 16. 16. The method for producing an oxide semiconductor thin film according to 15, wherein the annealing treatment is performed in an atmosphere containing at least oxygen.
- a field effect thin film transistor element comprising an oxide semiconductor thin film obtained by the method for producing a thin film according to 17.15 or 16. 18. 18.
- a thin film transistor having favorable transistor characteristics such as mobility can be provided even when the channel layer (semiconductor layer) is thick.
- the film forming method of the present invention comprises a metal oxide in a gas atmosphere containing a rare gas atom and a water molecule, and the water molecule content is 0.1 to 10% in a partial pressure ratio with respect to the rare gas atom.
- a target is sputtered to form a thin film on the substrate.
- the partial pressure ratio of water molecules to rare gas atoms is represented by [H 2 O] / ([H 2 O] + [rare gas atoms]), where [H 2 O] is the water molecule in the gas atmosphere. It is a partial pressure, and [rare gas atom] is a partial pressure of a rare gas atom in a gas atmosphere.
- the film forming method of the present invention when used, by introducing a small amount of water molecules, OH groups are taken into the film, and oxygen vacancies are generated more efficiently than when oxygen is introduced (film formation of carriers). Occurrence) can be avoided. Further, since the amount of water molecules introduced is small, for example, a semiconductor film can be formed without reducing the sputtering rate.
- the gas atmosphere during sputtering contains rare gas atoms and water molecules, and the content of water molecules is 0.1 to 10%, preferably 0.5 to 7%, as a partial pressure ratio with respect to the rare gas atoms. More preferably, it is 1.0 to 5%, and particularly preferably 1.0 to 3.0%.
- the partial pressure of water during sputtering is preferably 5 ⁇ 10 ⁇ 3 to 5 ⁇ 10 ⁇ 1 Pa. When the pressure is less than 5 ⁇ 10 ⁇ 3 Pa, the amount of OH groups taken into the film decreases, so that the degree of oxidation of the thin film becomes insufficient and the carrier concentration tends to increase.
- the optimum moisture pressure varies depending on various sputtering conditions such as the power density of discharge and the TS distance. For example, when the discharge power density is 2.5 W / cm 2 , the moisture pressure is preferably 3 ⁇ 10 ⁇ 3 Pa to 1.5 ⁇ 10 ⁇ 2 Pa, and the discharge power density is 5.0 W / cm 2.
- the moisture pressure is preferably 1 ⁇ 10 ⁇ 2 Pa to 1 ⁇ 10 ⁇ 1 Pa, and when the discharge power density is 7.4 W / cm 2 , the moisture pressure is preferably 2.0 ⁇ 10 -2 Pa to 3.5 ⁇ 10 -2 Pa.
- the carrier concentration of the obtained thin film can be in the latter half of the 10 17 cm ⁇ 3 unit, and a high field effect mobility of 10 cm 2 / Vs or more can be obtained when a TFT element is formed. it can.
- the rare gas atom is not particularly limited, but is preferably an argon atom.
- oxygen and nitrogen may be included within a range that does not affect the TFT element.
- the pressure in the gas atmosphere is not particularly limited as long as the plasma can be stably discharged, but is preferably 0.1 to 5.0 Pa.
- the sputtering pressure refers to the total pressure in the system at the start of sputtering after introducing argon, water, oxygen or the like.
- the film formation rate of sputtering is usually 1 to 250 nm, preferably 1 to 100 nm / min, more preferably 10 to 80 nm / min, and particularly preferably 30 to 30 nm in the direction perpendicular to the film formation surface of the substrate. 60 nm / min.
- the film formation rate is less than 1 nm / min, the film formation rate is low, and thus productivity may be deteriorated.
- the film formation rate exceeds 250 nm / min, the film formation rate becomes too high, resulting in poor controllability of the film thickness, and OH groups are not uniformly incorporated into the film, resulting in impaired in-plane uniformity of characteristics. There is a risk of being. Further, if the film formation rate is too high, OH groups are not sufficiently taken into the film, so that it is necessary to introduce an excessive amount of water molecules during sputtering film formation.
- the distance between the target and the substrate is preferably 1 to 15 cm, more preferably 5 to 15 cm, and further preferably 4 to 8 cm in the direction perpendicular to the film formation surface of the substrate.
- this distance is less than 1 cm, the kinetic energy of the target constituent element particles reaching the substrate increases, and there is a possibility that good film characteristics cannot be obtained, and in-plane distribution of film thickness and electrical characteristics occurs. There is a risk that.
- the distance between the target and the substrate exceeds 15 cm, the kinetic energy of the target constituent element particles reaching the substrate becomes too small to obtain a dense film, and good film characteristics can be obtained. It may not be possible.
- the magnetic field strength is less than 300 gauss, the plasma density becomes low, so there is a possibility that sputtering cannot be performed in the case of a high resistance sputtering target.
- it exceeds 1000 gauss the controllability of the film thickness and electrical characteristics in the film may be deteriorated.
- the method of sputtering is not particularly limited, and any of DC sputtering with low plasma activity and high-frequency sputtering with a frequency of 10 MHz or less may be used.
- the sputtering may be pulse sputtering.
- DC sputtering refers to a sputtering method (DC sputtering) performed by applying a DC power supply
- RF sputtering high-frequency sputtering
- Pulse sputtering refers to sputtering performed by applying a pulse voltage.
- RF sputtering Since RF sputtering has a higher plasma density and lower discharge voltage than DC sputtering, lattice disturbance and the like can be reduced, and carrier mobility can be increased. In general, RF sputtering tends to provide a film with good in-plane uniformity. Therefore, a film obtained by RF sputtering is expected to have high field effect mobility when used as a TFT element. However, since RF sputtering is generally slower than DC sputtering, DC sputtering is industrially adopted.
- the power density applied to the target during DC sputtering film formation is preferably 1 to 10 W / cm 2 , more preferably 2 to 5 W / cm 2 . Particularly preferred is 2.5 to 5 W / cm 2 . If the power density is less than 1 W / cm 2 , the film formation rate may be slowed, resulting in poor productivity, and the discharge may not be stable. On the other hand, when the sputtering power density is more than 10 W / cm 2 , the film formation rate becomes too fast, and the film thickness controllability and the uniformity of characteristics may be deteriorated.
- Suitable alternating current sputtering include the following methods.
- the substrate is sequentially transported to a position facing three or more targets arranged in parallel at a predetermined interval in the vacuum chamber, and negative and positive potentials are alternately applied to each target from an AC power source, Plasma is generated on the target to form a film on the substrate surface.
- film formation is performed while switching a target to which a potential is applied between two or more targets branched and connected to at least one of the outputs from the AC power supply. That is, at least one of the outputs from the AC power supply is branched and connected to two or more targets, and film formation is performed while applying different potentials to adjacent targets.
- an apparatus that can be used for this sputtering for example, an AC (alternating current) sputtering apparatus for large-area production described in Patent Document 3 can be cited.
- AC alternating current
- the AC sputtering apparatus includes a vacuum chamber, a substrate holder disposed inside the vacuum chamber, and a sputtering source disposed at a position facing the substrate holder.
- a main part of the sputtering source is shown in FIG.
- the sputter source has a plurality of sputter units, each of which has plate-like targets 100a to 100f.
- the sputter surfaces of the targets are on the same plane. It is arranged to be located.
- Each of the targets 100a to 100f is formed in an elongated rectangular parallelepiped having a longitudinal direction, each target has the same shape, and edge portions (side surfaces) in the longitudinal direction of the sputtering surface are arranged in parallel with a predetermined distance from each other. Therefore, the side surfaces of the adjacent targets 100a to 100f are parallel.
- AC power supplies 300a to 300c are arranged outside the vacuum chamber, and two corresponding electrodes are connected to each of these AC power supplies. Of the two terminals of each of the AC power supplies 300a to 300c, one terminal is connected to one of the two adjacent electrodes, and the other terminal is connected to the other electrode.
- the two terminals of each AC power source 300a to 300c output voltages having different positive and negative polarities, and the targets 100a to 100f are attached in close contact with the electrodes. AC voltages having different polarities are applied to 100f from the AC power supplies 300a to 300c. Accordingly, when one of the targets 100a to 100f adjacent to each other is placed at a positive potential, the other is placed at a negative potential.
- the magnetic field forming means 200a to 200f are arranged on the surface of the electrode opposite to the targets 100a to 100f.
- Each of the magnetic field forming means 200a to 200f has an elongated ring-shaped magnet whose outer periphery is substantially equal to the outer periphery of the targets 100a to 100f, and a rod-shaped magnet shorter than the length of the ring-shaped magnet.
- Each ring-shaped magnet is arranged in parallel with the longitudinal direction of the targets 100a to 100f at a position directly behind the corresponding one of the targets 100a to 100f. As described above, since the targets 100a to 100f are arranged in parallel at a predetermined interval, the ring magnets are also arranged at the same interval as the targets 100a to 100f.
- the power density is preferably 3 to 20 W / cm 2 .
- the film formation rate is slow, which is not economical for production. If it exceeds 20 W / cm 2 , the target may be damaged.
- the power density is more preferably 5 to 20 W / cm 2 , further preferably 4 to 10 W / cm 2 .
- the frequency of AC sputtering is preferably in the range of 10 kHz to 1 MHz. If it is less than 10 kHz, there is a risk of noise problems. If the frequency exceeds 1 MHz, plasma spreads too much, so that sputtering is performed at a position other than the desired target position, and uniformity may be impaired.
- a more preferable frequency of AC sputtering is 20 kHz to 500 kHz.
- the deposition rate is preferably 70 to 250 nm / min, more preferably 100 to 200 nm / min.
- the target used in the film forming method of the present invention is not particularly limited as long as it is a target made of a metal oxide, and is preferably the following first to third targets.
- a first target that can be suitably used in the film formation method of the present invention is a target made of a metal oxide, and the metal oxide includes a gallium element (Ga), a zinc element (Zn), and a tin element ( Sn) contains at least one element selected from the group and indium element (In), and the content of indium element in the target satisfies the following atomic ratio.
- 0.2 ⁇ [In] / all metal atoms ⁇ 0.8 In the formula, [In] is the number of atoms of indium element in the target.
- the total metal atom is the number of atoms of all metal atoms included in the target.
- the atomic ratio is preferably 0.25 ⁇ [In] / all metal atoms ⁇ 0.75, and more preferably 0.3 ⁇ [In] / all metal atoms ⁇ 0.7.
- [In] / total metal atoms (atomic ratio) is less than 0.2, the carrier concentration may be lower than that of the semiconductor region.
- [In] / total metal atoms (atomic ratio) is more than 0.8, the sputtered thin film is likely to be crystallized, and in-plane electrical characteristics may be non-uniform when formed in a large area. There is.
- the second target that can be suitably used in the film forming method of the present invention is a target made of a metal oxide, and the metal oxide contains indium element (In), gallium element (Ga), and zinc element ( Zn) and the contents of indium element, gallium element and zinc element in the target satisfy the following atomic ratio. 0 ⁇ [In] / [Ga] ⁇ 0.5 0.2 ⁇ [In] / ([In] + [Ga] + [Zn]) ⁇ 0.9 (In the formula, [In] is the number of atoms of indium element in the target, [Ga] is the number of atoms of gallium element in the target, and [Zn] is the number of atoms of zinc element in the target.)
- the metal oxide of the second target preferably satisfies the following atomic ratio. 0 ⁇ [In] / [Ga] ⁇ 0.45 0.3 ⁇ [In] / ([In] + [Ga] + [Zn]) ⁇ 0.9 More preferably, the metal oxide of the second target satisfies the following atomic ratio. 0 ⁇ [In] / [Ga] ⁇ 0.35 0.4 ⁇ [In] / ([In] + [Ga] + [Zn]) ⁇ 0.9
- the composition ratio of the second target is, for example, 0 ⁇ [In] / [Ga] ⁇ 0.45 and 0.3 ⁇ [In] / ([In] + [Ga] + [Zn]) ⁇ 0.9
- the field effect mobility can be 5 to 10 cm 2 / Vs, and 0 ⁇ [In] / [Ga] ⁇ 0.35 and 0.4 ⁇ [In] / ([In] + [Ga] + [Zn ]) ⁇ 0.9 is desirable because the field effect mobility can be 10 cm 2 / Vs or more.
- a third target that can be suitably used in the film formation method of the present invention is a target made of a metal oxide, and the metal oxide contains indium element (In), tin element (Sn), and zinc element ( Zn) and the contents of indium element, tin element and zinc element in the target satisfy the following atomic ratio.
- the metal oxide of the third target preferably satisfies the following atomic ratio. 0.2 ⁇ [In] / ([In] + [Sn] + [Zn]) ⁇ 0.9 0 ⁇ [Sn] / ([In] + [Sn] + [Zn]) ⁇ 0.35 More preferably, the metal oxide of the third target satisfies the following atomic ratio. 0.3 ⁇ [In] / ([In] + [Sn] + [Zn]) ⁇ 0.9 0 ⁇ [Sn] / ([In] + [Sn] + [Zn]) ⁇ 0.2
- the resistance of the target becomes high resistance. There is a possibility that AC sputtering cannot be performed.
- [In] / ([In] + [Ga] + [Zn]) is 0.9 or more, the obtained thin film is easily crystallized. May be non-uniform.
- tin element becomes a carrier scattering source, when [Sn] / ([In] + [Sn] + [Zn]) is 0.5 or more, the carrier mobility becomes low, and the resulting thin film May be 5 cm 2 / Vs or less.
- the carrier concentration and carrier mobility can be controlled, and high field effect mobility can be obtained.
- the composition ratio of the third target is, for example, 0.2 ⁇ [In] / ([In] + [Sn] + [Zn]) ⁇ 0.9 and 0 ⁇ [Sn] / ([In] + [Sn] + [Zn]) ⁇ 0.35, the field effect mobility can be 5 to 10 cm 2 / Vs, and 0.3 ⁇ [In] / ([In] + [Sn] + [Zn]) ⁇ When 0.9 and 0 ⁇ [Sn] / ([In] + [Sn] + [Zn]) ⁇ 0.2, the field-effect mobility can be 10 cm 2 / Vs or more.
- Non-Patent Document 3 in order to control the carrier concentration, the target contains a Ga element, and the atomic number ratio of the Ga element target to all metal elements is 0.33.
- Ga element content exceeds 0.33 in terms of the atomic ratio with respect to the total metal elements of the target, Ga serves as a scattering source, and the mobility of the TFT element in which the thin film obtained is a semiconductor layer decreases. There was a risk of it.
- the content of Ga element is less than 0.33 in terms of the atomic ratio with respect to the total metal elements of the target, the amount of Ga serving as a scattering source becomes small, and there is an advantage that high mobility can be expected. There is a problem that it is difficult to control the thickness to 10 18 cm ⁇ 3 or less.
- the film forming method of the present invention when the film is formed using the second target having a Ga element content of less than 0.5 in terms of the number ratio of atoms relative to the indium element, or the third target not containing the Ga element. Also, a suitable TFT element can be obtained. In particular, when the third target is used, chemical resistance can be improved, so that the source / drain electrodes can be formed by wet etching without forming an etching stopper layer, and more preferably. An operating TFT element can be manufactured, and the manufacturing cost can be reduced.
- the metal oxide of the first target is preferably an oxide consisting essentially of or only of indium element and zinc element.
- the metal oxide of the second target is preferably indium element and gallium element.
- the third target metal oxide is preferably an oxide that is substantially or only composed of an indium element, a tin element, and a zinc element.
- the first to third targets are, for example, Mg, Ca, Sr, Ba, Ti, Zr, Hf, Al, Ge, Cu, Co, Fe, Ni, Mo, and rare earth elements as long as the effects of the present invention are not impaired.
- One or more elements selected from lanthanoid elements can be included.
- the OH group taken into the thin film enters oxygen defects as O, so that the carrier concentration can be lowered.
- the annealing treatment condition is preferably an annealing treatment at 150 to 400 ° C. for 5 to 120 minutes.
- the annealing temperature is less than 150 ° C., the OH groups incorporated in the film do not sufficiently form oxygen bonds, so it is difficult to obtain the effect of reducing the carrier concentration.
- the annealing temperature exceeds 400 ° C., crystallization proceeds. There is a risk that. The same applies to the processing time.
- the annealing treatment is not particularly limited as long as it is in the temperature range of 150 ° C. to 400 ° C., but is preferably performed in an atmosphere containing at least oxygen. By performing in an atmosphere containing oxygen, it is possible to suppress variation in characteristics when the annealed thin film is used as a TFT.
- An oxide semiconductor obtained by annealing a thin film obtained by the film formation method of the present invention (hereinafter sometimes simply referred to as the oxide semiconductor of the present invention) can be suitably used as a semiconductor thin film of a thin film transistor.
- the field-effect transistor including an oxide semiconductor of the present invention has high field-effect mobility and on-off ratio, shows normally-off, and has a clear pinch-off.
- the field-effect transistor including an oxide semiconductor of the present invention can form an oxide semiconductor at a low temperature, the field-effect transistor can be formed over a substrate having a limit of heat resistance such as alkali-free glass.
- the oxide semiconductor of the present invention is usually used in an n-type region, but it can be used in combination with various P-type semiconductors such as P-type Si-based semiconductors, P-type oxide semiconductors, P-type organic semiconductors, and the like. It can be used for various semiconductor devices.
- the TFT can also be applied to various integrated circuits such as logic circuits, memory circuits, and differential amplifier circuits. In addition to field effect transistors, it can be applied to electrostatic induction transistors, Schottky barrier transistors, Schottky diodes, and resistance elements.
- the configuration of the transistor a known configuration such as a bottom gate, a top gate, a bottom contact, and a top contact can be used without limitation.
- the bottom gate configuration is advantageous because high performance can be obtained as compared with amorphous silicon or ZnO TFTs.
- the bottom gate configuration is preferable because it is easy to reduce the number of masks at the time of manufacturing, and it is easy to reduce the manufacturing cost for uses such as a large display.
- a channel etch type bottom gate thin film transistor is particularly preferable.
- a channel-etched bottom gate thin film transistor has a small number of photomasks at the time of a photolithography process, and can produce a display panel at a low cost.
- a thin film transistor having a channel etch type bottom gate structure and a top contact structure is particularly preferable because it has excellent characteristics such as mobility and is easily industrialized.
- the field effect transistor including an oxide semiconductor of the present invention can be suitably operated even when the film thickness of a semiconductor film, which has conventionally been difficult to obtain good characteristics, is 50 nm or more, further 60 nm or more, 70 nm or more. .
- the field-effect transistor including the oxide semiconductor of the present invention has preferable mobility, on / off ratio, and S value. Note that the upper limit of the thickness of the semiconductor film is, for example, 100 nm.
- the S value of the field effect transistor containing an oxide semiconductor of the present invention is preferably 1 V / decade or less, more preferably 0.7 V / decade or less, and particularly preferably 0.5 V / decade or less. If the S value exceeds 1 V / decade, the transistor may not exhibit good switching characteristics such as an increase in driving voltage.
- the threshold voltage of the field effect transistor including the oxide semiconductor of the present invention is usually ⁇ 5.0 to 5.0 V, preferably ⁇ 1.0 to 2.0 V, more preferably ⁇ 1.0 to 1.0 V. More preferably, it is 0 to 1.0V. If it is greater than 5V, the drive voltage may increase and the power consumption may increase, and if it is less than -5V, the power consumption may increase.
- the channel length of the field effect transistor including the oxide semiconductor of the present invention is not particularly limited as long as it is in a range usually used, but is usually 10 to 70 ⁇ m, preferably 20 to 50 ⁇ m.
- the channel width of the field effect transistor containing an oxide semiconductor of the present invention is usually 10 to 100 ⁇ m, preferably 20 to 70 ⁇ m.
- the semiconductor film used for the TFT channel layer needs high mobility. Since the field effect transistor including an oxide semiconductor of the present invention has high mobility, it can be expected to be preferably used in a region of 1 to 10 ⁇ m, more preferably 2 to 8 ⁇ m. In terms of channel width, the field effect transistor including the oxide semiconductor of the present invention can be expected to be preferably used in a region of 1 to 10 ⁇ m, and further in a region of 2 to 8 ⁇ m.
- FIG. 2 is a schematic cross-sectional view showing an embodiment of a thin film transistor including the oxide semiconductor of the present invention.
- the thin film transistor 1 which is a field effect transistor is a bottom gate type, and a gate electrode 30 is formed on a glass substrate 60 and a gate insulating film 50 is formed thereon.
- An oxide semiconductor film 40 is formed on the gate insulating film 50, and the drain electrode 10 and the source electrode 20 are further formed on the oxide semiconductor film 40.
- the material for forming the drain electrode 10, the source electrode 20, and the gate electrode 30, and any commonly used material can be selected.
- a transparent electrode such as ITO, IZO, ZnO, or SnO 2
- a metal electrode such as Al, Ag, Cu, Cr, Ni, Mo, Au, Ti, or Ta, or a metal electrode made of an alloy containing these may be used. it can.
- Each electrode of the drain electrode 10, the source electrode 20, and the gate electrode 30 may have a multilayer structure in which two or more different conductive layers are stacked.
- the first conductive layer 31, 21, 11 and the second conductive layer 32, 22, 12 are respectively configured.
- a good conductor such as Al or Cu may be sandwiched with a metal having excellent adhesion such as Ti or Mo.
- the material for forming the gate insulating film 50 is not particularly limited, and a commonly used material can be arbitrarily selected.
- Examples of the material of the gate insulating film 50 include SiO 2 , SiNx, Al 2 O 3 , Ta 2 O 5 , TiO 2 , MgO, ZrO 2 , CeO 2 , K 2 O, Li 2 O, Na 2 O, and Rb 2.
- Compounds such as O, Sc 2 O 3 , Y 2 O 3 , HfO 3 , CaHfO 3 , PbTi 3 , BaTa 2 O 6 , SrTiO 3 , and AlN can be used.
- the number of oxygen in the oxide does not necessarily match the stoichiometric ratio (for example, it may be SiO 2 or SiO x).
- the gate insulating film 50 may have a structure in which two or more different insulating films are stacked.
- the gate insulating film 50 may be crystalline, polycrystalline, or amorphous, but is preferably polycrystalline or amorphous that is easy to manufacture industrially.
- the oxide semiconductor film 40 is an oxide semiconductor obtained by the film formation method of the present invention.
- the carrier density obtained by hole measurement is usually less than 10 18 cm ⁇ 3 , preferably less than 5 ⁇ 10 17 cm ⁇ 3 , more preferably less than 1 ⁇ 10 17 cm ⁇ 3. It is.
- the carrier density is 10 18 cm ⁇ 3 or more, the leakage current may increase.
- the lower limit of the carrier density is preferably 10 15 cm ⁇ 3 or more, for example, although it depends on the use of the element including the oxide semiconductor film 40.
- the specific resistance of the oxide semiconductor film 40 is usually 10 ⁇ 1 to 10 8 ⁇ cm, preferably 10 1 to 10 7 ⁇ cm, more preferably 10 2 to 10 6 ⁇ cm, as determined by the four probe method. It is. When the specific resistance is less than 10 ⁇ 1 ⁇ cm, electricity easily flows and there is a possibility that the semiconductor thin film does not function. On the other hand, when the specific resistance exceeds 10 8 ⁇ cm, there is a possibility that the semiconductor does not function unless a strong electric field is applied.
- the thickness of the oxide semiconductor film 40 is appropriately selected in accordance with the specific resistance of the oxide semiconductor 40 itself, and is preferably thick from the viewpoint of uniformity. From the viewpoint of (time), a thinner film thickness is preferable.
- the thickness of the oxide semiconductor film 40 is usually 20 to 500 nm, preferably 50 to 150 nm, more preferably 60 to 140 nm, particularly preferably 70 to 130 nm, and particularly preferably 70 to 110 nm.
- the thickness of the oxide semiconductor is less than 20 nm, the characteristics of the manufactured TFT may be non-uniform due to non-uniformity of the thickness when the oxide semiconductor is formed over a large area.
- the film thickness exceeds 500 nm the film formation time becomes long and there is a possibility that it cannot be adopted industrially.
- the field effect mobility of the thin film transistor 1 is usually 1 cm 2 / Vs or more, preferably 5 cm 2 / Vs or more, more preferably 10 cm 2 / Vs or more, further preferably 18 cm 2 / Vs or more, particularly preferably 30 cm 2 / Vs. Above, most preferably 50 cm 2 / Vs or more. When the field effect mobility is less than 1 cm 2 / Vs, the switching speed may be slow.
- the upper limit of the field effect mobility is, for example, 500 cm 2 / Vs.
- the on-off ratio of the thin film transistor 1 is usually 10 3 or more, preferably 10 4 or more, more preferably 10 5 or more, still more preferably 10 6 or more, and particularly preferably 10 7 or more.
- the thin film transistor 1 is preferably normally off with a positive threshold voltage (Vth) from the viewpoint of low power consumption. If the threshold voltage (Vth) is negative and normally on, power consumption may increase.
- the manufacturing method of the field effect transistor containing the oxide semiconductor of this invention can be manufactured, for example with the following method.
- a metal film is formed on an insulating substrate to form a gate electrode.
- Mo, Al, Cr and alloys containing these as main components are preferably used.
- a laminated film of these metal films may be used.
- a gate insulating film is formed on the gate electrode and the insulating substrate by plasma CVD.
- a semiconductor layer to be a channel is formed by a sputtering method.
- a semiconductor layer in a region to be a TFT is formed in an island shape through a photolithography process and an etching process.
- a second metal film for forming a source electrode and a drain electrode is formed.
- a material such as Al, Cr, Mo, or an alloy containing these can be used in the same manner as the gate electrode. It is also possible to configure with a laminated film.
- a transistor is obtained by obtaining a pattern of a source electrode and a drain electrode having desired shapes from the formed second metal film by a photolithography process and an etching process.
- Examples 1-30 A 2-inch target having the target composition shown in Tables 1 to 3 is mounted on the magnetron sputtering apparatus, a silicon wafer with a thermal oxide film having a thickness of 100 nm is used as the substrate A1, and a slide glass (# 1737 manufactured by Corning) as the substrate B1. Each was fitted. After transporting the substrate into the chamber and setting it to a predetermined ultimate pressure, Ar gas and H 2 O gas having a partial pressure ratio shown in Tables 1 to 3 were introduced, and the film thickness was 50 nm under the sputtering conditions shown in Tables 1 to 3. Were formed on the substrate A1 and the substrate B1, respectively. The obtained thin film was annealed in an oven under the annealing conditions shown in Tables 1 to 3 to obtain an oxide semiconductor formed by stacking on the substrate A1 and the substrate B1.
- the substrate B1 including the oxide semiconductor after the heat treatment was cut into 1 cm 2 and Au electrodes were attached to the four corners.
- An Au electrode and a copper wire were bonded with a silver paste to form a Hall effect measuring element B1, and the carrier concentration was evaluated.
- the results are shown in Tables 1 to 3.
- the carrier concentration was measured by performing Hall effect measurement using a ReiTest 8300 type (manufactured by Toyo Technica Co., Ltd.) at room temperature.
- An Au electrode was formed so that the TFT element A1 was manufactured.
- Comparative Examples 1-12 and Reference Examples 1-2 Using targets having the target compositions shown in Tables 4 and 5, Ar gas and H 2 O gas (Comparative Examples 5 to 6 and Reference Examples 1 and 2) or Ar gas and O 2 having the partial pressure ratios shown in Tables 4 and 5 A gas (Comparative Examples 1 to 4 and 7 to 12) was introduced, and an oxide film was formed and annealed under the conditions shown in Tables 4 and 5 in the same manner as in Examples 1 to 30.
- a semiconductor was manufactured, and a Hall effect measuring element B1 was manufactured and the carrier concentration was evaluated in the same manner as in Examples 1 to 30, and a TFT element A1 was manufactured and the transfer characteristics were evaluated. The results are shown in Tables 4 and 5.
- Example 31 A field effect transistor having a bottom gate structure and a top contact structure was fabricated.
- the obtained semiconductor layer was subjected to photolithography to form a semiconductor region (so-called island), and heat-treated at 300 ° C. for 1 hour in the atmosphere.
- a laminated metal film of Ti / Au / Ti was formed by DC sputtering, and patterning was performed by lift-off to form a source electrode and a drain electrode, respectively.
- heat treatment was performed at 300 ° C. for 1 hour in the atmosphere.
- SiOx and SiNx were formed in this order by plasma CVD to form a first protective layer and a second protective layer, respectively. Contact holes were formed and connected to external wiring.
- the obtained field effect transistor was evaluated for its characteristics.
- the field effect mobility was 21 cm 2 / Vs
- the on / off ratio was 10 8 or more
- the threshold voltage was 0.3 V
- the S value was 0.2 V / decade.
- the evaluation was performed using a semiconductor parameter analyzer (Keutley 4200) in an atmosphere of dry nitrogen at atmospheric pressure, room temperature, and in a light-shielded environment.
- Example 32 By using Mo for the source electrode and the drain electrode, and wet etching the Mo electrode on the channel layer using a phosphoric acid-based wet etching solution, a field-effect transistor having a channel-etched bottom gate configuration and a top-contact configuration is obtained.
- a field effect transistor was prepared and evaluated in the same manner as in Example 31 except that it was manufactured. As a result, the obtained field effect transistor has a field effect mobility of 19 cm 2 / Vs, an on / off ratio of 10 8 or more, a threshold voltage of 0.3 V, and an S value of 0.2 V / decade. Met.
- Example 33 RF sputtering was performed on a glass substrate at room temperature to deposit 200 nm of molybdenum metal, followed by patterning by dry etching to produce a gate electrode.
- the gate electrode was forward tapered after etching.
- SiNx and SiO 2 were formed in this order by a plasma enhanced chemical vapor deposition apparatus (PECVD), and the laminated film was used as a gate insulating film.
- PECVD plasma enhanced chemical vapor deposition apparatus
- the same sputtering target as in Example 31 was mounted on a DC magnetron sputtering film forming apparatus and sputtered under the same conditions as in Example 31 to form a semiconductor layer (film thickness of 80 nm) on the gate insulating film. Then, it heat-processed at 300 degreeC for 1 hour.
- the obtained field effect transistor was evaluated in the same manner as in Example 31. As a result, the field effect mobility was 18 cm 2 / Vs, the on / off ratio was 10 8 or more, the threshold voltage was 0.3 V, and the S value was 0.2 V / decade.
- Example 34 Sputtering was performed using the film forming apparatus of FIG. 1 under the conditions shown in Table 6 without heating a glass substrate having a width of 1100 mm, a length of 1250 mm, and a thickness of 0.7 mm.
- Sn: Zn (atomic ratio) 36: 15: 49 is used, and six targets 100a to 100f having a width of 200 mm, a length of 1700 mm, and a thickness of 10 mm are used. Parallel to the width direction, the distance between the targets was 2 mm.
- the width of the magnetic field forming means 200a to 200f was set to 200 nm, which is the same as that of the targets 100a to 100f.
- Ar and H 2 O which are sputtering gases, were introduced from the gas supply system into the system at a flow rate ratio of 99: 1.
- the film forming atmosphere at this time was 0.5 Pa.
- the film was formed under the above conditions for 8 seconds, and the thickness of the obtained ITZO was measured to be 15 nm.
- the film formation rate was as high as 112.5 nm / min, which was suitable for mass production.
- the carrier concentration was 2.5 ⁇ 10 16 cm ⁇ 3 , and it was confirmed that the semiconductor was sufficiently semiconductorized.
- Examples 35 to 39 A semiconductor thin film was obtained in the same manner as in Example 34 except that the target composition and sputtering conditions were changed as shown in Table 6. Further, after heat treatment in the same manner as in Example 34, hole measurement was performed, and it was confirmed that all semiconductors were formed.
- Comparative Example 14 A semiconductor thin film was obtained in the same manner as in Example 34 except that the sputtering conditions were changed as shown in Table 6. ITZO was formed by introducing argon and oxygen without using water as the introduced gas. As a result of the hole measurement, the carrier concentration was 2.5 ⁇ 10 17 cm ⁇ 3 and the semiconductor was made, but the film formation rate was slow at 36 nm / min. This film formation rate is considered to leave a problem in mass production.
- Comparative Example 15 In Comparative Example 14, the output power was increased to 20 W / cm 2 and high speed film formation was performed. As a result, the deposition rate increased to 90 nm / min. However, the carrier concentration was 7.5 ⁇ 10 18 cm ⁇ 3 and it was not made into a semiconductor.
- Comparative Example 16 A semiconductor thin film was obtained in the same manner as in Comparative Example 14 except that the sputtering conditions were changed as shown in Table 6. The carrier concentration was 5.5 ⁇ 10 19 cm ⁇ 3 and it was not made into a semiconductor.
- Examples 40-46 A 2-inch target having the target composition shown in Table 7 was mounted on the magnetron sputtering apparatus, a silicon wafer with a thermal oxide film having a thickness of 100 nm was used as the substrate A1, and a slide glass (# 1737 manufactured by Corning) was used as the substrate B1. Installed. After transporting the substrate into the chamber and setting it to a predetermined ultimate pressure, Ar gas and H 2 O gas having a partial pressure ratio shown in Table 7 were introduced, and an amorphous film having a film thickness of 50 nm under the sputtering conditions shown in Table 7 A film was formed on each of the substrate A1 and the substrate B1. The obtained thin film was annealed in an oven under the annealing conditions shown in Table 7 to obtain an oxide semiconductor laminated on the substrate A1 and the substrate B1.
- the substrate B1 including the oxide semiconductor after the heat treatment was cut into 1 cm 2 and Au electrodes were attached to the four corners.
- An Au electrode and a copper wire were bonded with a silver paste to form a Hall effect measuring element B1, and the carrier concentration was evaluated.
- the results are shown in Table 7.
- the carrier concentration was measured by performing Hall effect measurement using a ReiTest 8300 type (manufactured by Toyo Technica Co., Ltd.) at room temperature.
- An Au electrode was formed so that the TFT element A1 was manufactured.
- Examples 47-51 Using a target having the target composition shown in Table 8, Ar gas and H 2 O gas having a partial pressure ratio shown in Table 8 were introduced, and an amorphous film was formed and annealed under the conditions shown in Table 8. Others manufactured oxide semiconductors in the same manner as in Examples 40 to 46, manufactured Hall effect measuring elements B1 in the same manner as in Examples 40 to 46, evaluated carrier concentrations, and manufactured TFT elements A1. The transfer characteristics were evaluated. The results are shown in Table 8.
- the oxide semiconductor obtained by the oxide semiconductor manufacturing method of the present invention can be widely used as a semiconductor thin film of a field effect transistor such as a thin film transistor.
Abstract
Description
そこで、アモルファスシリコン系半導体薄膜のように大面積化が可能で、結晶シリコンに次いで移動度が高い材料として金属酸化物からなる透明半導体薄膜、特に、酸化インジウム、酸化亜鉛、酸化ガリウムからなる酸化物半導体薄膜が注目されている。
しかし、パワー密度を高くした場合、成膜速度が速くなり、酸素供給速度が相対的に遅くなるため、膜中のキャリア濃度が概ね1018cm-3以上となってしまい、TFTとしたときに良好な特性が得られなくなる問題があった。
しかしながら、これらはいずれも4インチサイズ以下のターゲットで適用される技術であり、実生産を想定した高速成膜に関しては改良の余地があった。
しかし、水蒸気分圧を導入して成膜した薄膜トランジスタは、電界移動度が3cm2/Vs程度と酸素導入時よりも特性が低くなり、大面積且つ高精細な表示装置に用いるには特性が不十分である。
そのため、これまで酸化物半導体を用いた薄膜トランジスタは、通常、チャンネル層は50nm以下の薄い膜厚で作製されており(非特許文献3)、チャンネル層の厚膜が厚く(例えば50nm以上、さらには60nm以上、70nm以上)、移動度、閾値電圧等の特性の良好な薄膜トランジスタが求められていた。
また、本発明の他の目的は、チャンネル層(半導体層)の膜厚が厚くても、移動度等のトランジスタ特性の良好な薄膜トランジスタを提供することである。
また上記成膜方法を用いることにより、製造時間が延長されることなく安定した半導体膜の製造方法を見出した。
1.希ガス原子及び水分子を含み、前記水分子の含有量が前記希ガス原子に対して分圧比で0.1~10%である気体の雰囲気下において、金属酸化物からなるターゲットをスパッタリングし、基板上に薄膜を成膜する成膜方法。
2.前記気体の圧力が、0.1~5.0Paである1に記載の成膜方法。
3.前記スパッタリングが、直流スパッタである1又は2に記載の成膜方法。
4.前記スパッタリングが、交流スパッタである1又は2に記載の成膜方法。
5.直流パワー密度が1~5W/cm2である3に記載の成膜方法。
6.真空チャンバー内に所定の間隔を置いて並設された3枚以上のターゲットに対向する位置に、基板を順次搬送し、
前記各ターゲットに交流電源から負電位及び正電位を交互に印加して前記ターゲット上にプラズマを発生させて前記基板表面上に薄膜を成膜する成膜方法であって、
前記成膜は、前記交流電源からの出力の少なくとも1つを、分岐して接続した2枚以上のターゲットの間で、電位を印加するターゲットの切替を行いながら行う、4に記載の成膜方法。
7.交流パワー密度が5~20W/cm2である4又は6に記載の成膜方法。
8.前記交流電源の周波数が10kHz~1MHzである4、6及び7のいずれかに記載の成膜方法。
9.基板の成膜面に対して垂直方向の成膜速度が1~100nm/minである1~8のいずれかに記載の成膜方法。
10.前記ターゲット及び基板間の距離が、基板の成膜面に対して垂直方向に1~15cmである1~9のいずれかに記載の成膜方法。
11.前記雰囲気の磁場強度が300~1000ガウスである1~10のいずれかに記載の成膜方法。
12.前記金属酸化物が、ガリウム元素(Ga)、亜鉛元素(Zn)及びスズ元素(Sn)からなら群から選択される1以上の元素、及びインジウム元素(In)を含有し、
ターゲット中のインジウム元素の含有量が、下記原子比を満たす1~11のいずれかに記載の成膜方法。
0.2≦[In]/全金属原子≦0.8
(式中、[In]はターゲット中のインジウム元素の原子数である。
全金属原子とは、ターゲットに含まれる全ての金属原子の原子数である。)
13.前記金属酸化物が、インジウム元素(In)、ガリウム元素(Ga)及び亜鉛元素(Zn)を含有し、
ターゲット中のインジウム元素、ガリウム元素及び亜鉛元素の含有量が、下記原子比を満たす1~11のいずれかに記載の成膜方法。
0<[In]/[Ga]<0.5
0.2<[In]/([In]+[Ga]+[Zn])<0.9
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Ga]はターゲット中のガリウム元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。)
14.前記金属酸化物が、インジウム元素(In)、スズ元素(Sn)及び亜鉛元素(Zn)を含有し、
ターゲット中のインジウム元素、スズ元素及び亜鉛元素の含有量が、下記原子比を満たす1~11のいずれかに記載の成膜方法。
0.2<[In]/([In]+[Sn]+[Zn])<0.9
0<[Sn]/([In]+[Sn]+[Zn])<0.5
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Sn]はターゲット中のスズ元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。)
15.1~14のいずれかに記載の成膜方法により得られる薄膜を150~400℃で5~120分間アニール処理する酸化物半導体薄膜の製造方法。
16.前記アニール処理を、少なくも酸素を含有する雰囲気下で行なう15に記載の酸化物半導体薄膜の製造方法。
17.15又は16に記載の薄膜の製造方法により得られる酸化物半導体薄膜を備えてなる電界効果型薄膜トランジスタ素子。
18.前記酸化物半導体薄膜がチャネル層である17に記載の電界効果型薄膜トランジスタ素子。
19.移動度10cm2/Vs以上であり、閾値電圧が-5~5Vである17又は18に記載の電界効果型薄膜トランジスタ素子。
また、本発明によれば、チャンネル層(半導体層)の膜厚が厚くても、移動度等のトランジスタ特性の良好な薄膜トランジスタを提供できる。
尚、水分子の希ガス原子に対する分圧比とは、[H2O]/([H2O]+[希ガス原子])で表され、[H2O]は気体雰囲気中の水分子の分圧であり、[希ガス原子]は気体雰囲気中の希ガス原子の分圧である。
に好ましくは1.0~5%であり、特に好ましくは、1.0~3.0%である。
スパッタ時の水の分圧は5×10-3~5×10-1Paが好ましい。5×10-3Pa未満の場合、膜中に取り込まれるOH基の量が少なくなるため、薄膜の酸化度が不足し、キャリア濃度が増加しやすくなる。5×10-1Paを超えると、膜中に多量のOH基が取り込まれるため、酸化が促進され、キャリア濃度と移動度が低くなる。そのためTFT素子としたときに電界効果移動度が所望の値よりも低くなってしまうおそれがある。
最適な水分圧は、放電のパワー密度やT-S距離等の種々のスパッタリングの条件により変化する。例えば放電のパワー密度が2.5W/cm2の場合は、水分圧は好ましくは3×10-3Pa~1.5×10-2Paであり、放電のパワー密度が5.0W/cm2の場合は、水分圧は好ましくは1×10-2Pa~1×10-1Paであり、放電のパワー密度が7.4W/cm2の場合は、水分圧は好ましくは2.0×10-2Pa~3.5×10-2Paの範囲である。水分圧をこれら範囲にすることで、得られる薄膜のキャリア濃度を1017cm-3台後半とすることができ、TFT素子とした時に10cm2/Vs以上の高い電界効果移動度を得ることができる。
尚、希ガス原子は、特に制限されないが、好ましくはアルゴン原子である。また、希ガス原子及び水以外に、TFT素子に影響を及ぼさない範囲で酸素及び窒素を含んでもよい。
尚、スパッタ圧力とは、アルゴン、水、酸素等を導入した後のスパッタ開始時の系内の全圧をいう。
成膜速度が1nm/min未満の場合、成膜速度が遅いため生産性が悪くなるおそれがある。一方、成膜速度が250nm/min超の場合、成膜速度が速くなりすぎて、膜厚の制御性が悪くなるとともに、OH基が膜中に均一に取り込まれず特性の面内均一性が損なわれるおそれがある。また、成膜速度が速すぎると膜中に十分にOH基が取り込まれないため、スパッタ成膜時に過剰な水分子の導入が必要となるおそれがある。
この距離が1cm未満の場合、基板に到達するターゲット構成元素の粒子の運動エネルギーが大きくなり、良好な膜特性を得ることができないおそれがあるうえ、膜厚及び電気特性の面内分布が生じてしまうおそれがある。一方、ターゲットと基板との間隔が15cmを越える場合、基板に到達するターゲット構成元素の粒子の運動エネルギーが小さくなりすぎて、緻密な膜を得ることができず、良好な膜特性を得ることができないおそれがある。
磁場強度が300ガウス未満の場合、プラズマ密度が低くなるため高抵抗のスパッタリングターゲットの場合スパッタリングできなくなるおそれがある。一方、1000ガウス超の場合、膜厚及び膜中の電気特性の制御性が悪くなるおそれがある。
ここでDCスパッタリングとは、直流電源を印加して行うスパッタ方法(直流スパッタ)をいい、高周波スパッタ(RFスパッタリング)とは、交流電源(交流スパッタ)を印加して行うスパッタリングをいう。また、パルススパッタリングとは、パルス電圧を印加して行うスパッタリングをいう。
そのため、RFスパッタリングより得られる膜は、TFT素子としたときの電界効果移動度も高くなることが期待される。しかし、一般的にRFスパッタリングは、DCスパッタリングよりも成膜が遅いため、工業的にはDCスパッタリングが採用されている。
パワー密度が1W/cm2未満の場合、成膜速度が遅くなって生産性が悪くなるおそれがあるうえ、また放電も安定しないおそれがある。一方、スパッタパワー密度が10W/cm2超の場合、成膜速度が速くなりすぎて、膜厚の制御性及び特性の均一性が悪くなるおそれがある。
真空チャンバー内に所定の間隔を置いて並設された3枚以上のターゲットに対向する位置に、基板を順次搬送し、上記各ターゲットに交流電源から負電位及び正電位を交互に印加して、ターゲット上にプラズマを発生させて基板表面上に成膜する。
このとき、交流電源からの出力の少なくとも1つを、分岐して接続した2枚以上のターゲットの間で、電位を印加するターゲットの切替を行いながら成膜を行う。即ち、上記交流電源からの出力の少なくとも1つを分岐して2枚以上のターゲットに接続し、隣り合うターゲットに異なる電位を印加しながら成膜を行う。
スパッタ源は、複数のスパッタ部を有し、板状のターゲット100a~100fをそれぞれ有し、各ターゲット100a~100fのスパッタされる面をスパッタ面とすると、各ターゲットはスパッタ面が同じ平面上に位置するように配置される。
各ターゲット100a~100fは長手方向を有する細長の直方体に形成され、各ターゲットは同一形状であり、スパッタ面の長手方向の縁部分(側面)が互いに所定間隔を空けて平行に配置される。従って、隣接するターゲット100a~100fの側面は平行になる。
各交流電源300a~300cの2つの端子は正負の異なる極性の電圧を出力するようになっており、ターゲット100a~100fは、電極に密着して取り付けられているので、隣接する2つのターゲット100a~100fには互いに異なる極性の交流電圧が交流電源300a~300cから印加される。従って、互いに隣接するターゲット100a~100fのうち、一方が正電位に置かれる時には他方が負電位に置かれた状態になる。
0.2≦[In]/全金属原子≦0.8
(式中、[In]はターゲット中のインジウム元素の原子数である。
全金属原子とは、ターゲットに含まれる全ての金属原子の原子数である。)
[In]/全金属原子(原子比)が0.2未満の場合、キャリア濃度が半導体領域よりも低くなってしまうおそれがある。一方、[In]/全金属原子(原子比)が0.8超の場合、スパッタリングした薄膜が結晶化しやすくなり、大面積に成膜した場合に、面内の電気特性が不均一になるおそれがある。
0<[In]/[Ga]<0.5
0.2<[In]/([In]+[Ga]+[Zn])<0.9
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Ga]はターゲット中のガリウム元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。)
0<[In]/[Ga]<0.45
0.3<[In]/([In]+[Ga]+[Zn])<0.9
第2のターゲットの金属酸化物は、より好ましくは下記原子比を満たす。
0<[In]/[Ga]<0.35
0.4<[In]/([In]+[Ga]+[Zn])<0.9
第2のターゲットの組成比が、例えば0<[In]/[Ga]<0.45且つ0.3<[In]/([In]+[Ga]+[Zn])<0.9では電界効果移動度を5~10cm2/Vsとすることができ、0<[In]/[Ga]<0.35且つ0.4<[In]/([In]+[Ga]+[Zn])<0.9では電界効果移動度を10cm2/Vs以上とすることができるため望ましい。
0.2<[In]/([In]+[Sn]+[Zn])<0.9
0<[Sn]/([In]+[Sn]+[Zn])<0.5
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Sn]はターゲット中のスズ元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。)
0.2<[In]/([In]+[Sn]+[Zn])<0.9
0<[Sn]/([In]+[Sn]+[Zn])<0.35
第3のターゲットの金属酸化物は、より好ましくは下記原子比を満たす。
0.3<[In]/([In]+[Sn]+[Zn])<0.9
0<[Sn]/([In]+[Sn]+[Zn])<0.2
第3のターゲットの組成比が、例えば0.2<[In]/([In]+[Sn]+[Zn])<0.9且つ0<[Sn]/([In]+[Sn]+[Zn])<0.35では、電界効果移動度を5~10cm2/Vsとすることができ、0.3<[In]/([In]+[Sn]+[Zn])<0.9且つ0<[Sn]/([In]+[Sn]+[Zn])<0.2では、電界効果移動度を10cm2/Vs以上とすることができる。
しかし、Ga元素の含有量が、ターゲットの全金属元素に対する原子数比で0.33を超える場合、Gaが散乱源となり、得られる薄膜が半導体層であるTFT素子は、その移動度が低下してしまうおそれがあった。一方で、Ga元素の含有量をターゲットの全金属元素に対する原子数比で0.33未満にすると、散乱源となるGaが少量となり、高い移動度が期待できるという利点を有する一方で、キャリア濃度を1018cm-3以下に制御することが困難となる問題があった。
第1~第3のターゲットは、本発明の効果を損なわないない範囲で例えばMg、Ca、Sr、Ba、Ti、Zr、Hf、Al、Ge、Cu、Co、Fe、Ni、Mo及び希土類元素、ランタノイド元素から選ばれる1種類以上の元素を含むことができる。
アニール温度が150℃未満の場合、膜中に取り込まれたOH基が十分に酸素結合を作らないため、キャリア濃度を低下させる効果を得ることが難しく、400℃超の場合、結晶化が進行してしまうおそれがある。処理時間についても同様である。
本発明の酸化物半導体を含む電界効果型トランジスタは、電界効果移動度及びon-off比が高く、ノーマリーオフを示すとともに、ピンチオフが明瞭なトランジスタである。また、本発明の酸化物半導体を含む電界効果型トランジスタは、酸化物半導体を低温で成膜できるので、無アルカリガラス等の耐熱温度に限界のある基板上に構成することが可能である。
尚、半導体膜の膜厚の上限は例えば100nmである。
本発明の酸化物半導体を含む電界効果型トランジスタのチャネル幅は、通常10~100μmであり、好ましくは20~70μmである。
本発明の酸化物半導体を含む電界効果型トランジスタは高い移動度を有するので、1~10μm領域、さらには2~8μmの領域においても好適に使用することが期待できる。またチャネル幅について、本発明の酸化物半導体を含む電界効果型トランジスタは、1~10μmの領域、さらには2~8μmの領域においても好適に使用することが期待できる。
電界効果型トランジスタである薄膜トランジスタ1はボトムゲート型であり、ガラス基板60上に、ゲート電極30が形成され、その上にゲート絶縁膜50が形成されている。ゲート絶縁膜50上には、酸化物半導体膜40が形成され、さらにその上にドレイン電極10とソース電極20とが離間して形成されている。
例えば、ITO,IZO,ZnO,SnO2等の透明電極や、Al,Ag,Cu,Cr,Ni,Mo,Au,Ti,Ta等の金属電極、又はこれらを含む合金の金属電極を用いることができる。
ゲート絶縁膜50の材料としては、例えばSiO2,SiNx,Al2O3,Ta2O5,TiO2,MgO,ZrO2,CeO2,K2O,Li2O,Na2O,Rb2O,Sc2O3,Y2O3,HfO3,CaHfO3,PbTi3,BaTa2O6,SrTiO3,AlN等の化合物を用いることができる。これらのなかでも、好ましくはSiO2,SiNx,Al2O3,Y2O3,HfO3,CaHfO3であり、より好ましくはSiO2,SiNx,Y2O3,HfO3,CaHfO3である。
尚、上記の酸化物の酸素数は、必ずしも化学量論比と一致していなくともよい(例えば、SiO2でもSiOxでもよい)。
酸化物半導体膜40は、通常はホール測定で求めたキャリア密度が1018cm-3未満であり、好ましくは5×1017cm-3未満であり、より好ましくは1×1017cm-3未満である。キャリア密度が1018cm-3以上の場合、漏れ電流が大きくなるおそれがある。
尚、キャリア密度の下限としては、酸化物半導体膜40を備える素子の用途にもよるが、例えば1015cm-3以上とするのが好ましい。
比抵抗が10-1Ωcm未満の場合、電気が容易に流れ半導体薄膜として機能しないおそれがある。一方、比抵抗が108Ωcm超の場合、強い電界をかけないと半導体として機能しないおそれがある。
酸化物半導体膜40の膜厚は、通常は、20~500nm、好ましくは50~150nm、より好ましくは60~140nm、特に好ましくは70~130nm、特に好ましくは70~110nmである。
酸化物半導体の膜厚が20nm未満の場合、大面積に成膜した際の膜厚の不均一性により、作製したTFTの特性が不均一になるおそれがある。一方、膜厚が500nm超の場合、成膜時間が長くなり工業的に採用できないおそれがある。
電界効果移動度が1cm2/Vs未満の場合、スイッチング速度が遅くなるおそれがある。また、電界効果移動度の上限は例えば500cm2/Vsである。
また、薄膜トランジスタ1は、低消費電力の観点からは閾値電圧(Vth)がプラスでノーマリーオフとなることが好ましい。閾値電圧(Vth)がマイナスでノーマリーオンとなると、消費電力が大きくなるおそれがある。
まず絶縁性基板上に金属膜を成膜し、ゲート電極を形成する。金属膜としてはMo,Al、Cr及びこれらを主成分とする合金が好適に用いられる。これらの金属膜の積層膜を用いてもよい。
ゲート電極及び絶縁性基板上に、プラズマCVD法により、ゲート絶縁膜を成膜する。次にスパッタリング法によりチャネルとなる半導体層を成膜する。次に、フォトリソグラフィー工程及びエッチング工程を経て、TFTとなる領域の半導体層を島状に形成する。続いて、ソース電極、ドレイン電極を形成するための第2金属膜を成膜する。この第2金属膜には、ゲート電極と同様に、Al、CrやMo、これらを含む合金等の材料を用いることができる。積層膜により構成することも可能である。
成膜した第2金属膜を、フォトリソグラフィー工程、エッチング工程により所望の形状のソース電極、ドレイン電極のパターンを得ることでトランジスタが得られる。
マグネトロンスパッタリング装置に、表1~3に示すターゲット組成を有する2インチのターゲットを装着し、基板A1として厚み100nmの熱酸化膜付シリコンウェハーを、及び基板B1としてスライドガラス(コーニング社製♯1737)をそれぞれ装着した。
基板をチャンバー内へ搬送後、所定の到達圧力とした後、表1~3に示す分圧比であるArガス及びH2Oガスを導入し、表1~3に示すスパッタ条件にて膜厚50nmの非晶質膜を基板A1及び基板B1上にそれぞれ成膜した。
得られた薄膜を表1~3に示すアニール条件でオーブン中でアニール処理を行い、基板A1及び基板B1上に積層してなる酸化物半導体を得た。
尚、キャリア濃度の測定は、室温にてResiTest8300型(東陽テクニカ社製)を用いてホール効果測定を行うことにより求めた。
得られたTFT素子A1をケースレー4200SCSにセットし、ドレイン電圧Vds=10V及びゲート電圧Vgs=-20~20Vの条件で伝達特性を評価した。結果を表1~3に示す。
表4及び5に示すターゲット組成を有するターゲットを用い、表4及び5に示す分圧比であるArガス及びH2Oガス(比較例5~6及び参考例1~2)又はArガス及びO2ガス(比較例1~4、7~12)を導入し、表4及び5に示す条件で非晶質膜の成膜及びアニール処理を行なった他は実施例1~30と同様にして酸化物半導体を製造し、実施例1~30と同様にしてホール効果測定用素子B1を製造してキャリア濃度を評価し、及びTFT素子A1を製造して伝達特性を評価した。結果を表4及び5に示す。
ボトムゲート構造トップコンタクト構成の電界効果トランジスタを作製した。
原子比In:Sn:Zn=36:15:49であるITZOスパッタリングターゲットを、DCマグネトロンスパッタリング成膜装置に装着してスパッタリングを行い、熱酸化膜(100nm)付シリコン基板上に半導体層(膜厚80nm)を成膜した。
スパッタ条件は、到達圧力2×10-4Pa、スパッタ圧力0.65Pa、分圧比[H2O]/([H2O]+[Ar])=3%、分圧比[O2]/([O2]+[Ar])=0%、パワー密度5.0W/cm2、T-S距離5cm、成膜速度95nm/min.とした。
次に、プラズマCVDにてSiOx及びSiNxの順に成膜し、第1の保護層、第2の保護層をそれぞれ形成した。コンタクトホールを形成し、外部配線と接続した。その後、大気下、300℃で1時間熱処理して、W=20μm及びL=20μmであり、Si基板をゲート電極としたボトムゲート構成かつトップコンタクト構成の電界効果型トランジスタを製造した。
その結果、電界効果移動度が21cm2/Vs、オンオフ比が108以上、閾値電圧が0.3V、S値が0.2V/decadeであった。
上記評価は、半導体パラメーターアナライザー(ケースレー4200)を用い、大気圧の乾燥窒素雰囲気下、室温、遮光環境下で評価した。
半導体層成膜時の水蒸気分圧及び酸素分圧をそれぞれ分圧比[H2O]/([H2O]+[Ar])=0%、分圧比[O2]/([O2]+[Ar])=10%とした他は実施例31と同様にして電界効果型トランジスタを製造し、評価した。
その結果、得られた電界効果型トランジスタは、閾値電圧-20V以下のノーマリーオン状態であった。酸素分圧制御では、チャンネル層が80nmの薄膜トランジスタの作製が困難であることが確認された。
ソース電極及びドレイン電極にMoを用い、リン酸系ウェットエッチング液を用い、チャンネル層上のMo電極をウェトエッチィングすることによって、チャンネルエッチ型のボトムゲート構成かつトップコンタクト構成の電界効果型トランジスタを製造した以外は、実施例31と同様にして電界効果型トランジスタを作製し評価した。
その結果、得られた電界効果型トランジスタは、電界効果移動度が19cm2/Vsであり、オンオフ比が108以上であり、閾値電圧が0.3Vであり、S値が0.2V/decadeであった。
ガラス基板上に、室温でRFスパッタリングして、モリブデン金属を200nm積層した後、ドライエッチングでパターニングして、ゲート電極を作製した。ゲート電極は、エッチング後に順テーパとなっていた。ゲート電極を積層した基板に、プラズマ化学気相成長装置(PECVD)にて、SiNx、SiO2の順に成膜し、積層膜をゲート絶縁膜とした。
実施例31と同じスパッタリングターゲットを、DCマグネトロンスパッタリング成膜装置に装着し、実施例31と同一の条件でスパッタリングして、ゲート絶縁膜上に半導体層(膜厚80nm)を成膜した。その後、300℃で1時間熱処理した。
その結果、電界効果移動度18cm2/Vs、オンオフ比が108以上、閾値電圧が0.3V、S値が0.2V/decadeであった。
図1の成膜装置を用い、幅1100mm、長さ1250mm、厚さ0.7mmのガラス基板を加熱せずに表6の条件にてスパッタリングを行った。
以上の条件で8秒成膜し、得られたITZOの膜厚を測定すると15nmであった。成膜速度は112.5nm/分と高速であり、量産に適した結果となった。
また、このようにして得られたITZO付きガラス基板電気炉に入れ、空気中400℃15分の条件で熱処理後、1cm2のサイズに切出し、4探針法によるホール測定を行った。その結果、キャリア濃度が2.5×1016cm-3となり、十分半導体化していることが確認できた。
ターゲット組成とスパッタ条件を表6のように変更した他は実施例34と同様にして半導体薄膜を得た。また、実施例34と同様にして熱処理の後、ホール測定を行い、全て半導体化していることを確認した。
スパッタ条件を表6のように変更した他は実施例34と同様にして半導体薄膜を得た。導入ガスに水を使用せず、アルゴンと酸素を導入してITZOを成膜した。ホール測定の結果、キャリア濃度は2.5×1017cm-3であり、半導体化したが、成膜レートが36nm/分と遅かった。この成膜レートでは量産に課題を残すと考えられる。
比較例14において出力パワーを20W/cm2に増加させ、高速成膜を行った。これにより成膜レートは90nm/分と上昇した。しかし、キャリア濃度が7.5×1018cm-3であり、半導体化しなかった。
スパッタ条件を表6のように変更した他は比較例14と同様にして半導体薄膜を得た。キャリア濃度が5.5×1019cm-3であり、半導体化しなかった。
マグネトロンスパッタリング装置に、表7に示すターゲット組成を有する2インチのターゲットを装着し、基板A1として厚み100nmの熱酸化膜付シリコンウェハーを、及び基板B1としてスライドガラス(コーニング社製♯1737)をそれぞれ装着した。
基板をチャンバー内へ搬送後、所定の到達圧力とした後、表7に示す分圧比であるArガス及びH2Oガスを導入し、表7に示すスパッタ条件にて膜厚50nmの非晶質膜を基板A1及び基板B1上にそれぞれ成膜した。
得られた薄膜を表7に示すアニール条件でオーブン中でアニール処理を行い、基板A1及び基板B1上に積層してなる酸化物半導体を得た。
尚、キャリア濃度の測定は、室温にてResiTest8300型(東陽テクニカ社製)を用いてホール効果測定を行うことにより求めた。
得られたTFT素子A1をケースレー4200SCSにセットし、ドレイン電圧Vds=10V及びゲート電圧Vgs=-20~20Vの条件で伝達特性を評価した。結果を表7に示す。
表8に示すターゲット組成を有するターゲットを用い、表8に示す分圧比であるArガス及びH2Oガスを導入し、表8に示す条件で非晶質膜の成膜及びアニール処理を行なった他は実施例40~46と同様にして酸化物半導体を製造し、実施例40~46と同様にしてホール効果測定用素子B1を製造してキャリア濃度を評価し、及びTFT素子A1を製造して伝達特性を評価した。結果を表8に示す。
この明細書に記載の文献の内容を全てここに援用する。
Claims (19)
- 希ガス原子及び水分子を含み、前記水分子の含有量が前記希ガス原子に対して分圧比で0.1~10%である気体の雰囲気下において、金属酸化物からなるターゲットをスパッタリングし、基板上に薄膜を成膜する成膜方法。
- 前記気体の圧力が、0.1~5.0Paである請求項1に記載の成膜方法。
- 前記スパッタリングが、直流スパッタである請求項1又は2に記載の成膜方法。
- 前記スパッタリングが、交流スパッタである請求項1又は2に記載の成膜方法。
- 直流パワー密度が1~5W/cm2である請求項3に記載の成膜方法。
- 真空チャンバー内に所定の間隔を置いて並設された3枚以上のターゲットに対向する位置に、基板を順次搬送し、
前記各ターゲットに交流電源から負電位及び正電位を交互に印加して前記ターゲット上にプラズマを発生させて前記基板表面上に薄膜を成膜する成膜方法であって、
前記成膜は、前記交流電源からの出力の少なくとも1つを、分岐して接続した2枚以上のターゲットの間で、電位を印加するターゲットの切替を行いながら行う、請求項4に記載の成膜方法。 - 交流パワー密度が5~20W/cm2である請求項4又は6に記載の成膜方法。
- 前記交流電源の周波数が10kHz~1MHzである請求項4、6及び7のいずれかに記載の成膜方法。
- 基板の成膜面に対して垂直方向の成膜速度が1~100nm/minである請求項1~8のいずれかに記載の成膜方法。
- 前記ターゲット及び基板間の距離が、基板の成膜面に対して垂直方向に1~15cmである請求項1~9のいずれかに記載の成膜方法。
- 前記雰囲気の磁場強度が300~1000ガウスである請求項1~10のいずれかに記載の成膜方法。
- 前記金属酸化物が、ガリウム元素(Ga)、亜鉛元素(Zn)及びスズ元素(Sn)からなら群から選択される1以上の元素、及びインジウム元素(In)を含有し、
ターゲット中のインジウム元素の含有量が、下記原子比を満たす請求項1~11のいずれかに記載の成膜方法。
0.2≦[In]/全金属原子≦0.8
(式中、[In]はターゲット中のインジウム元素の原子数である。
全金属原子とは、ターゲットに含まれる全ての金属原子の原子数である。) - 前記金属酸化物が、インジウム元素(In)、ガリウム元素(Ga)及び亜鉛元素(Zn)を含有し、
ターゲット中のインジウム元素、ガリウム元素及び亜鉛元素の含有量が、下記原子比を満たす請求項1~11のいずれかに記載の成膜方法。
0<[In]/[Ga]<0.5
0.2<[In]/([In]+[Ga]+[Zn])<0.9
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Ga]はターゲット中のガリウム元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。) - 前記金属酸化物が、インジウム元素(In)、スズ元素(Sn)及び亜鉛元素(Zn)を含有し、
ターゲット中のインジウム元素、スズ元素及び亜鉛元素の含有量が、下記原子比を満たす請求項1~11のいずれかに記載の成膜方法。
0.2<[In]/([In]+[Sn]+[Zn])<0.9
0<[Sn]/([In]+[Sn]+[Zn])<0.5
(式中、[In]はターゲット中のインジウム元素の原子数であり、[Sn]はターゲット中のスズ元素の原子数であり、[Zn]はターゲット中の亜鉛元素の原子数である。) - 請求項1~14のいずれかに記載の成膜方法により得られる薄膜を150~400℃で5~120分間アニール処理する酸化物半導体薄膜の製造方法。
- 前記アニール処理を、少なくも酸素を含有する雰囲気下で行なう請求項15に記載の酸化物半導体薄膜の製造方法。
- 請求項15又は16に記載の薄膜の製造方法により得られる酸化物半導体薄膜を備えてなる電界効果型薄膜トランジスタ素子。
- 前記酸化物半導体薄膜がチャネル層である請求項17に記載の電界効果型薄膜トランジスタ素子。
- 移動度10cm2/Vs以上であり、閾値電圧が-5~5Vである請求項17又は18に記載の電界効果型薄膜トランジスタ素子。
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