WO2011125935A1 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
- Publication number
- WO2011125935A1 WO2011125935A1 PCT/JP2011/058420 JP2011058420W WO2011125935A1 WO 2011125935 A1 WO2011125935 A1 WO 2011125935A1 JP 2011058420 W JP2011058420 W JP 2011058420W WO 2011125935 A1 WO2011125935 A1 WO 2011125935A1
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- electrode
- layer
- hole
- semiconductor substrate
- photosensitive resin
- Prior art date
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/481—Internal lead connections, e.g. via connections, feedthrough structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76898—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics formed through a semiconductor substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0231—Manufacturing methods of the redistribution layers
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0236—Shape of the insulating layers therebetween
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/0237—Disposition of the redistribution layers
- H01L2224/02372—Disposition of the redistribution layers connecting to a via connection in the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/023—Redistribution layers [RDL] for bonding areas
- H01L2224/024—Material of the insulating layers therebetween
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/0401—Bonding areas specifically adapted for bump connectors, e.g. under bump metallisation [UBM]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05541—Structure
- H01L2224/05548—Bonding area integrally formed with a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/0556—Disposition
- H01L2224/0557—Disposition the external layer being disposed on a via connection of the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/05611—Tin [Sn] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05601—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
- H01L2224/05616—Lead [Pb] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05617—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 400°C and less than 950°C
- H01L2224/05624—Aluminium [Al] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05639—Silver [Ag] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05644—Gold [Au] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05647—Copper [Cu] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05655—Nickel [Ni] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05638—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/05657—Cobalt [Co] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05666—Titanium [Ti] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
- H01L2224/05599—Material
- H01L2224/056—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
- H01L2224/05663—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of greater than 1550°C
- H01L2224/05671—Chromium [Cr] as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/0601—Structure
- H01L2224/0603—Bonding areas having different sizes, e.g. different heights or widths
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
- H01L2224/061—Disposition
- H01L2224/0618—Disposition being disposed on at least two different sides of the body, e.g. dual array
- H01L2224/06181—On opposite sides of the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13022—Disposition the bump connector being at least partially embedded in the surface
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
- H01L2224/13001—Core members of the bump connector
- H01L2224/1302—Disposition
- H01L2224/13024—Disposition the bump connector being disposed on a redistribution layer on the semiconductor or solid-state body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/02—Bonding areas ; Manufacturing methods related thereto
- H01L24/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L24/06—Structure, shape, material or disposition of the bonding areas prior to the connecting process of a plurality of bonding areas
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
- H01L24/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01004—Beryllium [Be]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01005—Boron [B]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01006—Carbon [C]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01013—Aluminum [Al]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01024—Chromium [Cr]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01029—Copper [Cu]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01033—Arsenic [As]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01047—Silver [Ag]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/0105—Tin [Sn]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01082—Lead [Pb]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/014—Solder alloys
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/102—Material of the semiconductor or solid state bodies
- H01L2924/1025—Semiconducting materials
- H01L2924/1026—Compound semiconductors
- H01L2924/1032—III-V
- H01L2924/10329—Gallium arsenide [GaAs]
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/14—Integrated circuits
- H01L2924/143—Digital devices
- H01L2924/1434—Memory
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/156—Material
- H01L2924/15786—Material with a principal constituent of the material being a non metallic, non metalloid inorganic material
- H01L2924/15788—Glasses, e.g. amorphous oxides, nitrides or fluorides
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Definitions
- the present invention relates to a semiconductor device provided with a through electrode, and in particular, a semiconductor that prevents the occurrence of cracks and the like in the protective layer filling the inside of the through hole in which the through electrode is formed, and improves the durability of the protective layer.
- the present invention relates to an apparatus and a manufacturing method thereof. This application claims priority based on Japanese Patent Application No. 2010-087257 for which it applied on April 5, 2010, and uses the content here.
- the through electrode is formed by covering a through hole formed perpendicular to the semiconductor substrate with a conductive metal.
- the technology for forming the through electrode can significantly reduce the wiring distance as compared with the conventional method for realizing the connection by wire bonding, and thus contributes to speeding up, power saving, and downsizing of the semiconductor device.
- the through electrode having these excellent features is very advantageous in that it is possible to realize a high-density mounting or a high information processing speed that is currently progressing rapidly.
- FIG. 8 shows an example of a semiconductor device having a conventional through electrode.
- the semiconductor device 101 includes, as main components, a semiconductor substrate 102 having an insulating portion 103 formed on a first surface 102a (one surface or one surface), and a first surface 102a of the semiconductor substrate 102.
- the circuit element 104 is formed.
- a through hole 106 is formed in the semiconductor substrate 102 so that the electrode pad 105 is exposed on the second surface 102b side of the semiconductor substrate.
- An insulating layer 107 is formed on both surfaces of the semiconductor substrate 102 and inside the through hole 106, and the rewiring layer 108 and the through hole are formed on the side surface of the through hole 106 and on the second surface 102 b of the semiconductor substrate on the insulating layer 107.
- An electrode 109 is formed. The through electrode 109 is electrically connected to the electrode pad 105.
- the circuit element 104 is electrically connected to the electrode pad 105 through the wiring portion 119. Furthermore, the electrode pad 105 is electrically connected to the redistribution layer 108 through the through electrode 109, whereby the electrical connection between the circuit element 104 and the member disposed on the second surface 102 b of the semiconductor substrate 102. Connection is possible.
- the rewiring layer 108 and the through electrode 109 are mainly composed of Cu. Further, the rewiring layer 108 and the through electrode 109 are covered and protected by a protective layer 110 (overcoat layer).
- a protective layer 110 an inexpensive negative photosensitive resin is often used. This negative photosensitive resin is embedded in the through hole 106 and simultaneously covers the second surface 102b of the semiconductor substrate 102 including the rewiring layer 108.
- the negative photosensitive resin used in this structure is a dry film-like or varnish-like resin.
- the negative photosensitive resin is filled in the through hole 106 by a method such as film lamination or spin coating.
- a scribe line for dicing into an opening of a Cu pad on which the solder bump 15 is placed or a chip size is formed by photolithography, and the semiconductor substrate is completed.
- the conventional structure has a defect that a void 151 is generated when the photosensitive resin coating is applied.
- the photosensitive resin does not easily enter the through hole having a large aspect ratio, and it is difficult to completely fill the inside of the through hole with the resin.
- the void 151 is likely to occur at a position close to the intersection between the bottom surface 109a and the side surface 109b of the through electrode 109 that covers the inside of the through hole.
- the exposure light hardly reaches the inside of the through hole 106. Therefore, the photochemical reaction of the photosensitive resin does not sufficiently proceed inside the through hole, and a protective layer having poor mechanical strength is formed due to the remaining unreacted photosensitive component, and a crack-like void 152 is formed. There was a problem that would occur.
- the presence of such voids 151 or voids 152 in the protective layer 110 makes it easy for cracks to expand starting from the voids or voids, and also facilitates breakage of the through electrodes 109, resulting in the reliability of the semiconductor device 101. There is a problem that the performance is lowered.
- the present invention has been made in view of such circumstances, and an object of the present invention is to provide a semiconductor device that prevents a defect that a crack or the like is generated in a protective layer filling the inside of a through hole constituting a through electrode. There is.
- a semiconductor device includes a semiconductor substrate including a first surface, a second surface opposite to the first surface, an electrode pad provided on the first surface, and the second surface.
- a through hole penetrating the semiconductor substrate from the surface toward the first surface and exposing the electrode pad; an exposed portion where the electrode pad is exposed; and a side surface of the through hole; a bottom surface and a side surface; And a through electrode electrically connected to the electrode pad, and a protective layer filled in the through hole, covering the through electrode, and formed of a plurality of layers.
- the layer closest to the first surface among the plurality of layers of the protective layer covers at least an intersection located between the bottom surface and the side surface of the through electrode, and is positive photosensitive.
- Made of resin That is, the layer closest to the first surface is formed using a positive photosensitive resin.
- the method for manufacturing a semiconductor device includes the following steps (A) to (G).
- a semiconductor substrate having a first surface and a second surface opposite to the first surface is prepared, and an electrode pad is formed on the first surface.
- a through hole penetrating the semiconductor substrate is formed from the second surface toward the first surface to expose the electrode pad.
- a through electrode having a bottom surface and a side surface is formed by covering the exposed portion where the electrode pad is exposed and the side surface of the through hole.
- the through electrode is covered with a positive photosensitive resin.
- the positive photosensitive resin is removed so that the positive photosensitive resin remains at least at the intersection between the bottom surface and the side surface of the through electrode.
- step (D), the step (E), and the step (F) are repeated a plurality of times.
- the protective layer that fills the through hole and covers the through electrode is formed by a plurality of protective layers.
- the protective layer composed of a plurality of layers covers at least the intersection located between the bottom surface and the side surface of the through electrode, and is formed using a positive photosensitive resin.
- the bottom portion of the through electrode that is difficult for light to reach is coated with a positive photosensitive resin, and light is applied to the surface coated with the positive photosensitive resin. Irradiation is performed to remove the resin so that the positive photosensitive resin remains on the bottom surface of the through electrode. Accordingly, the protective layer can be reliably filled in the through hole, and the positive photosensitive resin can be filled in the corner of the bottom surface of the through electrode that is difficult for exposure light to reach. For this reason, the problem resulting from the photosensitive resin inside the through hole not being exposed can be eliminated.
- the steps of filling the positive photosensitive resin, irradiating light, and removing the resin are repeated a plurality of times.
- a small amount of resin is filled into the through hole, and then the resin is filled into the through hole so as to overlap the previously filled resin. That is, the resin is filled into the through hole little by little. For this reason, the resin is more reliably filled into the through-hole, and filling failure is less likely to occur.
- FIG. 1 is a cross-sectional view showing a first embodiment of a semiconductor device according to the present invention. It is a figure explaining the process of the manufacturing method of the semiconductor device which concerns on this invention. It is a figure explaining the process of the manufacturing method of the semiconductor device which concerns on this invention. It is a figure explaining the process of the manufacturing method of the semiconductor device which concerns on this invention. It is a figure explaining the process of the manufacturing method of the semiconductor device which concerns on this invention. It is a figure explaining the process of the manufacturing method of the semiconductor device which concerns on this invention. It is a figure explaining the process of the manufacturing method of the semiconductor device which concerns on this invention. It is sectional drawing which shows 2nd Embodiment of the semiconductor device which concerns on this invention. It is sectional drawing which shows 3rd Embodiment of the semiconductor device which concerns on this invention.
- FIG. 1 is a cross-sectional view showing an embodiment of the present invention.
- reference numeral 1 denotes a semiconductor device
- reference numeral 2 denotes a semiconductor substrate
- reference numeral 3 denotes an insulating portion
- reference numeral 4 denotes a circuit element
- reference numeral 5 denotes an electrode pad
- reference numeral 6 denotes a through hole
- Reference numeral 7 indicates an insulating layer
- reference numeral 8 indicates a rewiring layer
- reference numeral 9 indicates a through electrode
- reference numeral 20 indicates a support substrate
- reference numeral 21 indicates a bonding resin.
- the semiconductor device 1 is supported by a semiconductor substrate 2 provided with a rewiring layer 8, a through electrode 9, a circuit element 4, and the like via a bonding resin 21.
- the structure is supported by the substrate 20.
- the semiconductor substrate 2 is a semiconductor substrate such as silicon or GaAs, for example.
- the thickness of the semiconductor substrate 2 is, for example, about several hundred ⁇ m.
- the first surface 2 a of the semiconductor substrate 2 functions as the insulating portion 3.
- the semiconductor substrate 2 may be a semiconductor wafer such as a silicon wafer, or may be a semiconductor chip having a predetermined dimension (chip dimension) divided by cutting (dicing) the semiconductor wafer.
- the semiconductor substrate 2 is a semiconductor chip, first, various circuit elements and the like are formed on the semiconductor wafer, and then the semiconductor wafer is cut to obtain a plurality of semiconductor chips having predetermined dimensions (chip dimensions). be able to.
- the circuit element 4 is, for example, a semiconductor functional element such as a memory, an IC, an imaging element, and a MEMS element.
- the support substrate 20 As a material for the support substrate 20, it is desirable to select a material (member) whose thermal expansion coefficient of the support substrate 20 is close to the thermal expansion coefficient of the semiconductor substrate 2 at the temperature at which the semiconductor substrate 2 and the support substrate 20 are bonded. . Specifically, a glass substrate is preferable, but if the circuit element 2 does not require optical characteristics, the material of the support substrate 20 does not need to be a transparent material. Further, the support substrate 20 is not always necessary, and the support substrate 20 may be omitted when the strength required for the semiconductor substrate 2 is sufficiently obtained.
- the material of the bonding resin 21 a material having adhesiveness and electrical insulation is used. For example, it is desirable to use polyimide resin, epoxy resin, benzocyclobutane (BCB) resin, or the like.
- An electrode pad 5 is provided on the first surface 2 a of the semiconductor substrate 2.
- a material having excellent conductivity such as Al or Cu, an aluminum-silicon (Al-Si) alloy, an aluminum-silicon-copper (Al-Si-Cu) alloy is preferably used.
- the electrode pad 5 is electrically connected to the circuit element 4 provided on the first surface 2 a of the semiconductor substrate 2 through the wiring portion 19.
- the wiring portion 19 is disposed on the first surface 2 a of the semiconductor substrate 2 and constitutes a circuit that electrically connects the electrode pad 5 and the circuit element 4.
- the material of the wiring portion 19 may be the same material as that of the electrode pad 5 and is made of conductive material such as Al or Cu, an aluminum-silicon (Al-Si) alloy, an aluminum-silicon-copper (Al-Si-Cu) alloy, or the like. A material having excellent properties is preferably used.
- a through hole 6 penetrating from the second surface 2b toward the first surface 2a is formed in a portion where the electrode pad 5 is provided. Therefore, when viewed from the second surface 2 b side, a part of the electrode pad 5 is exposed through the through hole 6.
- the diameter of the through hole 6 is, for example, about several tens of ⁇ m. Further, the number of through holes 6 provided on the semiconductor substrate 2 is not particularly limited.
- An insulating layer 7 is provided on the second surface 2 b of the semiconductor substrate 2 and the side surfaces of the through holes 5.
- the semiconductor substrate 2 has insulating properties on the second surface 2 b of the substrate and the side surfaces of the through holes 6.
- the insulating layer 7 is made of, for example, SiO 2 , SiN, or a resin film.
- a through electrode 9 is formed inside the through hole 6 to cover the side surface of the through hole 6 and the exposed portion where the electrode pad 5 is exposed.
- a rewiring layer 8 is formed on the second surface 2 b of the semiconductor substrate 2. One end of the rewiring layer 8 is electrically connected to the through electrode 9.
- the through electrode 9 is electrically connected to the electrode pad 5.
- the material of the through electrode 9 and the rewiring layer 8 is preferably a material having excellent conductivity. Further, as the material of the through electrode 9, it is more preferable to use a material that is excellent in adhesion between the electrode pad 5 and the through electrode 9 and that does not easily diffuse into the electrode pad 5.
- the material of the rewiring layer 8 and the through electrode 9 includes conductors (such as various metals or alloys) such as Cu, Al, Ni, Ag, Pb, Sn, Au, Co, Cr, Ti, TiW, or the like. It is preferable to use a material in which is combined.
- the through electrode 9 is disposed in a part of the through hole 6 so as to extend between the first surface 2 a and the second surface 2 b of the semiconductor substrate 2 may be employed.
- the protective layer 10 includes a first layer 11 made of a positive photosensitive resin and a second layer 12 made of a negative photosensitive resin.
- the first layer 11 is disposed at least inside the through hole 6, and is the layer closest to the first surface 2 a of the semiconductor substrate 2 in the protective layer 10.
- the positive photosensitive resin is a photosensitive resin in which an exposed portion generated by exposing the resin is removed by a chemical solution.
- the negative photosensitive resin is a photosensitive resin in which the resin excluding the exposed portion is removed by a chemical solution.
- the first layer 11 is disposed in the inside of the through hole 6 at a position near the first surface 2 a of the semiconductor substrate 2, that is, a position near the bottom of the through hole 6 (bottom side).
- the bottom surface 9a of the through electrode 9 is covered.
- the thickness of the first layer 11 is not particularly limited, but at least the intersecting portion where the bottom surface 9a and the side surface 9b of the through electrode 9 intersect each other is covered with the first layer 11 made of a positive photosensitive resin. ing.
- various resin materials such as a polyimide resin, a silicone resin, and an epoxy resin can be applied.
- the second layer 12 covers the inside of the through hole 6 and the second surface 2 b of the semiconductor substrate 2 so as to cover the first layer 11.
- the second layer 12 is patterned so that at least the connection portion of the rewiring layer 8 is exposed, and a hemispherical solder bump 15 is formed on this connection portion.
- the resin constituting the second layer 12 any type of photosensitive resin is applicable regardless of whether it is a positive type or a negative type.
- various resin materials such as polyimide resin, silicone resin, and epoxy resin can be used.
- the protective layer filling the through hole 6 is formed by a plurality of protective layers.
- the semiconductor device 1 according to this embodiment has a configuration in which at least the intersection between the bottom surface and the side surface of the through electrode 9 is covered with the first layer 11 made of a positive photosensitive resin. Regardless of the magnitude of the photosensitive reaction in the positive photosensitive resin, a resin layer having a stable strength can be obtained after the desired thermosetting treatment.
- the first layer 11 made of a positive photosensitive resin is disposed at least at the intersection between the bottom surface and the side surface of the through electrode 9 in the through hole where light does not easily reach when exposing the photosensitive resin.
- the conventional semiconductor device it is possible to suppress the occurrence of cracks or the like of the protective layer 10 that is easily generated at the intersection between the bottom surface and the side surface of the through electrode 9.
- a negative photosensitive resin is employed as the material of the second layer 12, but the material is not limited to a negative type, and a positive photosensitive resin may be employed. Further, any resin can be used as long as the resin can be patterned so as to protect the second surface 2b of the semiconductor substrate 2 and expose a part of the rewiring layer 8.
- FIGS. 2A to 2E are views for sequentially explaining the steps of the method of manufacturing a semiconductor device according to the present invention, using cross-sectional views. 2A to 2E, the support substrate and the bonding resin are omitted.
- step A a process of preparing the semiconductor substrate 2 on which the rewiring layer 8 and the through electrode 9 have been formed will be described with reference to FIG. 2A.
- step A the semiconductor substrate 2 provided with the circuit element 4 is prepared, and the electrode pad 5 and the wiring part 19 are formed on the first surface 2a of the semiconductor substrate 2 (step A).
- step B A through hole 6 reaching the electrode pad 5 from the second surface 2b of the semiconductor substrate 2 is formed (step B).
- the through hole 6 is formed from the second surface 2b of the semiconductor substrate 2 so that the electrode pad 5 is exposed.
- the diameter and the cross-sectional shape of the through-hole 6 are not particularly limited, but are appropriately set according to the thickness of the semiconductor substrate 2 or the use (desired use) of the semiconductor substrate 2 and can be appropriately determined according to the desired wiring. .
- the thickness of the semiconductor substrate 2 is 100 ⁇ m
- the hole diameter of the through hole 6 is 80 ⁇ m.
- a through hole 6 formation method for example, a DRIE (Deep-Reactive Ion Etching) method, a wet etching method, a machining method using a micro drill, a photoexcited electrolytic polishing method, or the like can be used.
- a DRIE Deep-Reactive Ion Etching
- step C After forming the insulating layer 7 on the side surface of the through hole 6 and the second surface 2b of the semiconductor substrate 2, the exposed portion of the electrode pad 5, the through electrode 9 covering the side surface of the through hole 6, and the semiconductor substrate 2 A rewiring layer 8 covering the second surface 2b is formed (step C).
- the electrode pad 5, the rewiring layer 8 of the insulating layer 7 and the through electrode 9 are electrically connected.
- the insulating layer 7 is formed, for example, by depositing SiO 2 by plasma CVD or the like.
- the formation method of the rewiring layer 8 and the through electrode 9 is not particularly limited, and examples of the formation method include a sputtering method, a vapor deposition method, a plating method, and a combination of these two or more methods.
- a photolithography technique is preferably used as a patterning method for the rewiring layer 8 and the through electrode 9.
- the through electrode 9 is formed so as to cover the entire surface of the through hole 6 .
- the through electrode on the electrode pad 5 and the second surface 2b of the semiconductor substrate 2 is described.
- the present invention is not limited to the structure described above.
- the through electrode 9 may be formed linearly on the side surface of the through hole 6.
- the semiconductor substrate 2 on which the rewiring layer 8 and the through electrode 9 are formed as shown in FIG. 2A can be prepared.
- the positive photosensitive resin 11a is applied to the second surface 2b of the semiconductor substrate 2 to cover the rewiring layer 8 and the through electrode 9, and the through hole 6 is filled with the positive photosensitive resin 11a.
- the positive photosensitive resin 11a is preferably a low-viscosity liquid resin so that the resin can easily enter the through hole 6.
- a positive photosensitive resin having a viscosity of 50 to 300 cP can be applied.
- a method for applying the positive photosensitive resin 11a a method in which the resin can enter the through hole 6 is preferable. For example, a spin coat coating method, a spray coating method or the like is preferable.
- the semiconductor substrate 2 is returned to an atmospheric pressure environment to fill the through hole 6 with a differential pressure.
- the exposure light 60 is irradiated onto the second surface 2b of the semiconductor substrate 2 (step E).
- the exposure light 60 light including the photosensitive wavelength of the photosensitive resin is used.
- the optimum photosensitive wavelength for exposure varies depending on the resin material, it is generally preferable to use light in the ultraviolet region called g, h, i line.
- the positive photosensitive resin is developed so that the positive photosensitive resin 11a remains at least at the intersection between the bottom surface 9a and the side surface 9b of the through electrode 9 (steps). F).
- the resin is developed so as to reach about half the depth of the through-hole 6, and the positive photosensitive resin 11a applied on the second surface 2b of the semiconductor substrate 2 disappears,
- the positive photosensitive resin 11a disposed at a position close to the bottom surface 9a of the through electrode 9 remains.
- the developer used in the development step can be determined according to the type of photosensitive resin.
- heat treatment is performed in this state to volatilize excess photosensitive group components, solvent components, and the like of the positive photosensitive resin, thereby causing a thermosetting reaction.
- the negative photosensitive resin 12a is coated on the second surface 2b of the semiconductor substrate 2, and the negative photosensitive resin 12a is filled into the through-hole 6 (step G). As shown in FIG. 2D, the negative photosensitive resin 12a is applied on the second surface 2b.
- a coating method of the negative photosensitive resin 12a a spin coat coating method, a film laminating method, a spray coating method, or the like can be employed. Further, after applying the negative photosensitive resin 12a under a vacuum pressure, the semiconductor substrate 2 is returned to an atmospheric pressure environment to fill the inside of the through hole 6 with a differential pressure. it can.
- the negative photosensitive resin 12a is patterned using photolithography technology. Specifically, as shown in FIG. 2D, the negative photosensitive resin 12a is irradiated with exposure light 60 through a photomask 70, and the mask pattern is transferred to the negative photosensitive resin 12a. Next, as shown in FIG. 2E, the negative photosensitive resin 12a is developed to remove unnecessary photosensitive resin. Cure and descum are applied to the remaining photosensitive resin 12. Finally, the solder bump 15 is formed, and the semiconductor device 1 as shown in FIG. 1 can be obtained.
- the semiconductor substrate 1 of the first embodiment can be manufactured by the method as described above. By manufacturing in this way, the positive photosensitive resin 11a is filled at the bottom of the through hole 6 where light does not easily reach, so that the bottom of the through hole 6 is reliably covered with the positive photosensitive resin 11a.
- the positive photosensitive resin 11a is formed by a single coating process, but the present invention is not limited to the above-described method.
- the coating process of the positive photosensitive resin 11a can be repeated a plurality of times. That is, a manufacturing method in which the negative photosensitive resin 12a is applied after performing the steps D to F a plurality of times may be used.
- a manufacturing method in which the negative photosensitive resin 12a is applied after performing the steps D to F a plurality of times may be used.
- a small amount of resin is filled into the through holes, and then the resin that has been previously filled The resin is filled into the through hole so as to overlap with the inside. That is, the resin is filled into the through hole 6 little by little. For this reason, the resin is more reliably filled into the through-hole, and filling failure is less likely to occur.
- the material of the second layer 12 is not limited to the negative photosensitive resin, and a positive photosensitive resin may be used. Further, any resin can be used as long as the resin can be patterned so as to protect the second surface 2b of the semiconductor substrate 2 and expose a part of the rewiring layer 8.
- 3 to 7 are cross-sectional views showing an example of an embodiment of the semiconductor device of the present invention.
- the same members as those in the first embodiment are denoted by the same reference numerals, and the description thereof will be omitted or simplified.
- the differences between the first embodiment and the third to sixth embodiments will be mainly described. State.
- the protective layer 10b includes a first layer 11b made of a positive photosensitive resin, a second layer 13b, and a space between the first layer 11b and the second layer 13b. And a third layer 12b disposed in the first layer.
- the third layer 12b can be formed by forming a film by a suitable film formation method after the formation of the first layer 11b.
- the third layer 12b is formed of a material having adhesiveness to both the first layer 11b and the second layer 13b.
- the third layer 12b is not limited to the resin layer but may be a metal layer.
- the third layer 12b is interposed between the first layer 11b and the second layer 13b. Adhesiveness with the 2nd layer 13b can be improved.
- the first layer 11 c constituting the protective layer 10 c is not formed at a position near the center of the bottom surface 9 a of the through electrode 9, and the bottom surface 9 a and the side surface 9 b of the through electrode are not formed. It is formed so as to cover only the intersection between them. In this configuration, only the intersection between the bottom surface and the side surface of the through electrode 9 that is most difficult to fill is filled with a small amount of the first layer 11 c and then the second layer 12 c is filled into the through hole 6. . By this method, the through hole 6 can be reliably filled without generating a void.
- the shape of the first layer 11 d constituting the protective layer 10 d is symmetric in a cross section that includes the center point of the through hole 6 and is perpendicular to the semiconductor substrate 2. It need not be in shape. That is, the first layer 11d remaining by exposure may be formed in an asymmetric shape.
- the 1st layer 11e which comprises the protective layer 10e may have a convex shape that the center part rises upwards.
- the protective layer 10f can be formed by using a plurality of layers in accordance with the function of the protective layer.
- the protective layer 10f includes a first layer 11f, a second layer 12f, a third layer 13f, and a fourth layer 14f.
- the protective layer 10f is comprised with the some resin layer, it becomes possible to form the protective layer 10f which has a function according to the objective which each layer implement
- the material of the first layer 11f and the third layer 13f a material that can easily fill the through hole is applied, and as the material of the second layer 12f and the fourth layer 14f, rewiring is performed.
- a material that functions as a protective film for protecting the film or a material excellent in pattern processability can be applied.
- the present invention can be widely applied to a semiconductor device provided with a through electrode and a manufacturing method thereof.
- SYMBOLS 1 ... Semiconductor device, 2 ... Semiconductor substrate, 3 ... Insulating part, 4 ... Circuit element, 5 ... Electrode pad, 6 ... Through-hole, 7 ... Insulating layer, 8 ... Redistribution layer, 9 ... Through electrode, 10 ... Protective layer 11 ... first layer, 12 ... second layer, 19 ... wiring section.
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2010087257A JP5568357B2 (ja) | 2010-04-05 | 2010-04-05 | 半導体装置及びその製造方法 |
JP2010-087257 | 2010-04-05 |
Publications (1)
Publication Number | Publication Date |
---|---|
WO2011125935A1 true WO2011125935A1 (ja) | 2011-10-13 |
Family
ID=44762873
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/JP2011/058420 WO2011125935A1 (ja) | 2010-04-05 | 2011-04-01 | 半導体装置及びその製造方法 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP5568357B2 (enrdf_load_stackoverflow) |
TW (1) | TW201201342A (enrdf_load_stackoverflow) |
WO (1) | WO2011125935A1 (enrdf_load_stackoverflow) |
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2584598A1 (en) * | 2011-10-20 | 2013-04-24 | austriamicrosystems AG | Method of producing a semiconductor device comprising a through-substrate via and a capping layer and corresponding semiconductor device |
WO2015093313A1 (ja) * | 2013-12-16 | 2015-06-25 | ソニー株式会社 | 半導体素子、半導体素子の製造方法、および電子機器 |
EP3316283A1 (en) * | 2016-10-27 | 2018-05-02 | NXP USA, Inc. | Through substrate via (tsv) and method therefor |
US11329092B2 (en) | 2017-10-02 | 2022-05-10 | Sony Semiconductor Solutions Corporation | Semiconductor device, manufacturing method of semiconductor device, and electronic equipment |
Families Citing this family (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014013810A (ja) * | 2012-07-04 | 2014-01-23 | Seiko Epson Corp | 基板、基板の製造方法、半導体装置、及び電子機器 |
JP6263859B2 (ja) * | 2013-04-18 | 2018-01-24 | 大日本印刷株式会社 | 貫通電極基板の製造方法、貫通電極基板、および半導体装置 |
US9613843B2 (en) * | 2014-10-13 | 2017-04-04 | General Electric Company | Power overlay structure having wirebonds and method of manufacturing same |
WO2017059781A1 (zh) * | 2015-10-10 | 2017-04-13 | 苏州晶方半导体科技股份有限公司 | 影像传感芯片的封装方法以及封装结构 |
KR102082714B1 (ko) * | 2015-10-10 | 2020-02-28 | 차이나 와퍼 레벨 씨에스피 씨오., 엘티디. | 이미지 센싱 칩을 위한 패키징 방법 및 패키지 구조 |
JP7340965B2 (ja) * | 2019-06-13 | 2023-09-08 | キヤノン株式会社 | 半導体装置およびその製造方法 |
JP7354885B2 (ja) * | 2020-03-12 | 2023-10-03 | 富士通株式会社 | 半導体装置及び半導体装置の製造方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002270714A (ja) * | 2001-03-12 | 2002-09-20 | Sumitomo Metal Electronics Devices Inc | プラスチックパッケージの製造方法 |
JP2009277883A (ja) * | 2008-05-14 | 2009-11-26 | Sharp Corp | 電子素子ウェハモジュールおよびその製造方法、電子素子モジュール、電子情報機器 |
JP2010040862A (ja) * | 2008-08-06 | 2010-02-18 | Fujikura Ltd | 半導体装置 |
-
2010
- 2010-04-05 JP JP2010087257A patent/JP5568357B2/ja not_active Expired - Fee Related
-
2011
- 2011-04-01 TW TW100111590A patent/TW201201342A/zh unknown
- 2011-04-01 WO PCT/JP2011/058420 patent/WO2011125935A1/ja active Application Filing
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002270714A (ja) * | 2001-03-12 | 2002-09-20 | Sumitomo Metal Electronics Devices Inc | プラスチックパッケージの製造方法 |
JP2009277883A (ja) * | 2008-05-14 | 2009-11-26 | Sharp Corp | 電子素子ウェハモジュールおよびその製造方法、電子素子モジュール、電子情報機器 |
JP2010040862A (ja) * | 2008-08-06 | 2010-02-18 | Fujikura Ltd | 半導体装置 |
Cited By (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
EP2584598A1 (en) * | 2011-10-20 | 2013-04-24 | austriamicrosystems AG | Method of producing a semiconductor device comprising a through-substrate via and a capping layer and corresponding semiconductor device |
WO2015093313A1 (ja) * | 2013-12-16 | 2015-06-25 | ソニー株式会社 | 半導体素子、半導体素子の製造方法、および電子機器 |
JPWO2015093313A1 (ja) * | 2013-12-16 | 2017-03-16 | ソニー株式会社 | 半導体素子、半導体素子の製造方法、および電子機器 |
US9978797B2 (en) | 2013-12-16 | 2018-05-22 | Sony Corporation | Semiconductor element, manufacturing method of semiconductor element, and electronic apparatus |
US10950648B2 (en) | 2013-12-16 | 2021-03-16 | Sony Corporation | Semiconductor element, manufacturing method of semiconductor element, and electronic apparatus |
US11610929B2 (en) | 2013-12-16 | 2023-03-21 | Sony Corporation | Semiconductor element, manufacturing method of semiconductor element, and electronic apparatus |
EP3316283A1 (en) * | 2016-10-27 | 2018-05-02 | NXP USA, Inc. | Through substrate via (tsv) and method therefor |
US20180122698A1 (en) * | 2016-10-27 | 2018-05-03 | Freescale Semiconductor, Inc. | Through substrate via (tsv) and method therefor |
US10157792B2 (en) | 2016-10-27 | 2018-12-18 | Nxp Usa, Inc. | Through substrate via (TSV) and method therefor |
US10546779B2 (en) * | 2016-10-27 | 2020-01-28 | Nxp Usa, Inc. | Through substrate via (TSV) and method therefor |
US11329092B2 (en) | 2017-10-02 | 2022-05-10 | Sony Semiconductor Solutions Corporation | Semiconductor device, manufacturing method of semiconductor device, and electronic equipment |
Also Published As
Publication number | Publication date |
---|---|
JP5568357B2 (ja) | 2014-08-06 |
JP2011222596A (ja) | 2011-11-04 |
TW201201342A (en) | 2012-01-01 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
JP5568357B2 (ja) | 半導体装置及びその製造方法 | |
JP6110889B2 (ja) | チップパッケージおよびその製造方法 | |
US6667551B2 (en) | Semiconductor device and manufacturing thereof, including a through-hole with a wider intermediate cavity | |
CN101635266B (zh) | 晶粒与晶片间三维互连的接合结构与方法 | |
JP4874005B2 (ja) | 半導体装置、その製造方法及びその実装方法 | |
TWI761852B (zh) | 貫通電極基板及其製造方法、以及安裝基板 | |
TWI492354B (zh) | 半導體裝置及其製造方法 | |
CN104218022B (zh) | 晶片封装体及其制造方法 | |
JP6041731B2 (ja) | インターポーザ、及び電子部品パッケージ | |
CN107146795A (zh) | 晶片封装体及其制造方法 | |
TW202133258A (zh) | 半導體元件以及其製造方法 | |
JP2008305897A (ja) | 半導体装置およびその製造方法 | |
JP4601686B2 (ja) | 半導体装置および半導体装置の製造方法 | |
JP5026025B2 (ja) | 半導体装置 | |
US9502344B2 (en) | Wafer level packaging of electronic device | |
WO2022191180A1 (ja) | 多層配線基板 | |
JP2008135553A (ja) | 基板積層方法及び基板が積層された半導体装置 | |
JP5355363B2 (ja) | 半導体装置内蔵基板及びその製造方法 | |
JP7679686B2 (ja) | 多層配線基板 | |
CN114171467A (zh) | 一种半导体封装结构 | |
JP7721953B2 (ja) | 多層配線基板 | |
JP7435635B2 (ja) | 貫通電極基板 | |
JP6435893B2 (ja) | 貫通電極基板の製造方法 | |
JP7679684B2 (ja) | 多層配線基板、複合配線基板、パッケージ化デバイス、及び多層配線基板の製造方法 | |
JP7679682B2 (ja) | 多層配線基板、複合配線基板、パッケージ化デバイス、及び多層配線基板の製造方法 |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
121 | Ep: the epo has been informed by wipo that ep was designated in this application |
Ref document number: 11765835 Country of ref document: EP Kind code of ref document: A1 |
|
NENP | Non-entry into the national phase |
Ref country code: DE |
|
122 | Ep: pct application non-entry in european phase |
Ref document number: 11765835 Country of ref document: EP Kind code of ref document: A1 |