WO2017059781A1 - 影像传感芯片的封装方法以及封装结构 - Google Patents

影像传感芯片的封装方法以及封装结构 Download PDF

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Publication number
WO2017059781A1
WO2017059781A1 PCT/CN2016/100817 CN2016100817W WO2017059781A1 WO 2017059781 A1 WO2017059781 A1 WO 2017059781A1 CN 2016100817 W CN2016100817 W CN 2016100817W WO 2017059781 A1 WO2017059781 A1 WO 2017059781A1
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Prior art keywords
wafer
opening
image sensing
photosensitive ink
substrate
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PCT/CN2016/100817
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English (en)
French (fr)
Inventor
王之奇
王卓伟
谢国梁
Original Assignee
苏州晶方半导体科技股份有限公司
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
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Priority claimed from CN201520780135.4U external-priority patent/CN205050828U/zh
Priority claimed from CN201510650103.7A external-priority patent/CN105244339B/zh
Application filed by 苏州晶方半导体科技股份有限公司 filed Critical 苏州晶方半导体科技股份有限公司
Priority to US15/765,802 priority Critical patent/US10283483B2/en
Priority to KR1020187011133A priority patent/KR102055412B1/ko
Priority to JP2018517536A priority patent/JP6629440B2/ja
Publication of WO2017059781A1 publication Critical patent/WO2017059781A1/zh

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    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
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    • H01L2924/16235—Connecting to a semiconductor or solid-state bodies, i.e. cap-to-chip

Definitions

  • the present invention relates to the field of semiconductor technology, and in particular, to a method of packaging a wafer level semiconductor chip.
  • Wafer Level Chip Size Packaging Today's mainstream semiconductor chip packaging technology is Wafer Level Chip Size Packaging (WLCSP), which is a technology that packages and tests the entire wafer and then cuts it to obtain a single finished chip.
  • the size of a single finished chip packaged by this package technology is similar to that of a single die size, which is in line with the market demand for lighter, smaller, shorter, thinner and lower cost of microelectronic products.
  • Wafer-level chip-scale packaging technology is a hotspot and future development trend in the current packaging field.
  • a package structure of a wafer level image sensing chip is disclosed.
  • the wafer 1 is aligned with the protective substrate 2 , and the supporting unit 3 is located between the wafer 1 and the protective substrate 2 to form a gap therebetween.
  • the gap avoids the direct contact between the protective substrate 2 and the wafer 1.
  • the wafer 1 includes a plurality of grid-shaped image sensing chips 10, and the image sensing chip 10 includes an image sensing region 11 and pads 12, and a plurality of supports
  • the unit 3 is arranged in a grid on the protective substrate 2 and corresponds to the image sensor chip 10.
  • the support unit 3 surrounds the image sensing area 11, and the wafer 1 has the first A surface and a second surface opposite the first surface, the image sensing region 11 and the pad 12 are located on a first surface side of the wafer.
  • an opening 22 extending toward the first surface is disposed on the second surface side of the wafer 1.
  • the opening 22 corresponds to the pad 12 and the bottom of the opening 22 exposes the pad.
  • an insulating layer 23 is disposed on the sidewall of the opening 22
  • a rewiring layer 24 is disposed on the insulating layer 23 and the bottom of the opening 22.
  • the rewiring layer 24 is electrically connected to the pad 12, and the solder ball 25 and the rewiring layer 24 electrical connection, electrically connected to other circuits through the solder ball 25 to achieve electrical connection between the pad 12 and other circuits.
  • the second surface of the wafer 1 is provided with a cutting groove 21 extending toward the first surface.
  • the solder resist ink 26 Before the solder balls 25 are arranged on the second surface of the wafer 1, the solder resist ink 26 needs to be applied, and the solder resist ink 26 is also filled in the cutting grooves 21 and the openings 22 to achieve the effect of protection and insulation.
  • solder resist ink 26 fills the opening 22, in the subsequent reflow soldering and reliability test, the thermal expansion and contraction of the solder resist ink 26 forms a force acting on the rewiring layer 24, under the pull of such force.
  • the rewiring layer 24 is easily separated from the pad 12, resulting in a defective chip, which becomes a technical problem to be solved by those skilled in the art.
  • the problem solved by the invention is that the wafer level image sensor chip packaging method and the image sensor chip package structure provided by the invention eliminate the detachment of the rewiring layer from the solder pad, solve the chip defect, and improve the image sensor chip package structure. Trustworthiness.
  • the present invention provides a method for packaging an image sensing chip, comprising: providing a wafer having a first surface and a second surface opposite to the first surface, the wafer An image sensing chip having a plurality of grids, the image sensing chip having an image sensing area and a pad, the image sensing area and the pad being located on a first surface side of the wafer;
  • the second surface of the circle forms an opening extending toward the first surface, the opening exposing the pad;
  • the second of the wafer Forming a V-shaped cutting groove extending toward the first surface; coating a photosensitive ink on the second surface of the wafer, filling the V-shaped cutting groove with the photosensitive ink, and covering the opening with the photosensitive ink, and A cavity is formed between the opening and the photosensitive ink.
  • the V-shaped cutting groove and the opening are simultaneously formed on the second surface of the wafer by an etching process.
  • the V-shaped cutting groove is formed by cutting from a second surface of the wafer with a cutter.
  • the method further comprises: providing a protection substrate, wherein the protection substrate is provided with a grid-arranged supporting unit, and each supporting unit corresponds to one image transmission a chip; the first surface of the wafer is aligned with the protective substrate, the support unit is located between the wafer and the protective substrate; and the second surface of the wafer is ground Thinning.
  • cutting is performed along the V-shaped cutting groove by a cutter which is cut into at least a part of the supporting unit.
  • the cutting width of the cutter is smaller than the width of the opening of the V-shaped groove near the second surface of the wafer.
  • the V-shaped cutting groove is cut from a second surface of the wafer by a cutter and the cutter is cut into at least a part of the supporting unit.
  • the method before applying the photosensitive ink, further comprises: forming an insulating layer on the sidewall of the opening and the second surface of the wafer; forming a rewiring layer on the insulating layer and at the bottom of the opening And electrically connecting the rewiring layer to the solder pad; after coating the photosensitive ink on the second surface of the wafer, further comprising: forming a plurality of through holes on the photosensitive ink, the through holes being exposed The rewiring layer; forming a solder ball in the through hole, the solder ball being electrically connected to the rewiring layer.
  • the photosensitive ink has a viscosity of not less than 12 Kcps.
  • the invention also provides an image sensing chip package structure, comprising: a substrate having a first side and a second surface opposite the first surface; an image sensing region on the first surface; and a pad; an opening on the second surface and extending toward the first surface, the opening being exposed And the photosensitive pad covering the side of the substrate; the photosensitive ink covers the opening, and forms a cavity between the opening and the photosensitive ink; the side of the substrate has an inclined side a wall, one end of the inclined side wall intersecting the second surface.
  • the side of the substrate further has a vertical side wall, one end of the vertical side wall is in contact with the inclined side wall, and the other end is in contact with the first side of the substrate.
  • the other end of the inclined side wall interfaces with the first side of the substrate.
  • the angle of the inclined side wall to the second side of the substrate ranges from 40° to 85°.
  • the photosensitive ink has a viscosity of not less than 12 Kcps.
  • the package structure further includes: a protection substrate pressed against the first facing position of the substrate; a support unit located between the protection substrate and the substrate, the support unit surrounding the image sensing a photosensitive ink covering at least a portion of the side of the support unit; an insulating layer on the sidewall of the opening and the second side of the substrate; a rewiring layer on the insulating layer and at the bottom of the opening,
  • the rewiring layer is electrically connected to the pad;
  • the photosensitive ink covers the rewiring layer, and a through hole is disposed on the photosensitive ink, the through hole exposing the rewiring layer; a solder ball in the via hole, the solder ball being electrically connected to the rewiring layer.
  • the invention has the beneficial effects that the rewiring layer and the bonding pad are effectively avoided between the opening and the photosensitive ink, the packaging yield of the image sensing chip is improved, and the reliability of the image sensing chip packaging structure is improved. .
  • FIG. 1 is a schematic diagram of a package structure of a wafer level image sensing chip in the prior art
  • Figure 2 is a schematic structural view of a wafer level image sensing chip
  • FIG. 3 is a cross-sectional view showing a package structure of a wafer level image sensor chip
  • FIG. 4 to FIG. 11 are schematic diagrams showing a method of packaging a wafer level image sensing chip according to the present invention.
  • FIG. 12 is a schematic diagram of a package structure of a single image sensing chip according to an embodiment of the invention.
  • FIG. 13 is a schematic diagram of a package structure of a single image sensing chip according to another embodiment of the present invention.
  • the solder resist ink fills the opening, so that the solder resist ink is completely in contact with the rewiring layer, and in the subsequent reflow soldering and reliability test, the force formed by the shrinkage expansion of the solder resist ink pulls the rewiring layer, which is easy to make The rewiring layer is detached from the pad.
  • the present invention can effectively prevent the rewiring layer from being detached from the bonding pad by forming a cavity between the opening and the solder resist ink so that the solder resist ink does not come into contact with the wiring layer at the bottom of the opening.
  • FIG. 2 is a schematic structural diagram of a wafer level image sensing chip.
  • the wafer 100 has a plurality of image sensing chips 110 arranged in a grid, and a gap is reserved between the image sensing chips 110 for subsequent packaging. After the process and testing, the image sensor chip is separated along the gap.
  • Each of the image sensing chips 110 has an image sensing area 111 and a plurality of pads 112.
  • the pads 112 are located on the side of the image sensing area 111 and are located on the same surface side of the wafer 100 as the image sensing area 111.
  • FIG. 3 is a cross-sectional view showing a package structure of a wafer level image sensor chip according to an embodiment of the invention.
  • One of the protective substrate 200 is provided with a plurality of supporting units 210 arranged in a grid. After the wafer 100 is aligned with the protective substrate 200, the supporting unit 210 is located between the wafer 100 and the protective substrate 200. A gap is formed between the two, and the supporting unit 210 is in one-to-one correspondence with the image sensing chip 110, and the supporting unit 210 surrounds the image sensing area 111.
  • the wafer 100 has a first surface 101 and a second surface 102 opposite to the first surface 101.
  • the image sensing region 111 and the pad 112 are located on the first surface 101 side, and the second surface 102 of the wafer has a first orientation.
  • the surface 101 extends a V-shaped cutting groove 103 and an opening 113. Each opening 113 corresponds to the position of each pad 112, and the bottom of the opening 113 exposes the pad 112.
  • the soldering pad 112 is connected to other lines by using the rewiring layer 115 and the solder balls 116.
  • the sidewall of the opening 113 and the second surface 102 of the wafer 100 have an insulating layer 114 on the insulating layer 114 and the opening 113.
  • the bottom of the wafer is electrically connected to the pad 112, and the solder ball 116 is electrically connected to the rewiring layer 115 through the solder ball. 116 electrically connecting other circuits to form an electrical connection between the pad 112 and other circuits.
  • the V-shaped cutting groove 103 is filled with the photosensitive ink 117, and the photosensitive ink 117 covers the opening 113 and forms a cavity 119 between the opening 113 and the photosensitive ink 117.
  • the photosensitive ink 117 has a through hole, and the through hole exposes the rewiring layer. 115, the solder ball 116 is located in the through hole and electrically connected to the rewiring layer 115.
  • the specific packaging process is as follows.
  • a wafer 100 is provided, and a schematic diagram of the structure of the wafer 100 is shown in FIG. 1;
  • a protective substrate 200 is provided, and a plurality of supporting units 210 are arranged on one side of the protective substrate 200.
  • the material of the supporting unit 210 is photosensitive ink, which is formed on the protective substrate 200 by exposure and development. One side.
  • the wafer 100 is aligned with the protective substrate 200, and the wafer 100 is bonded to the protective substrate 200 by using an adhesive.
  • the support unit 210 is located between the wafer 100 and the protective substrate 200, and the three are surrounded by A plurality of sealed spaces arranged in a grid are formed. Each sealed space corresponds to one image sensing chip 110, The support unit 210 surrounds the image sensing area 111 of the image sensor chip 110.
  • the second surface 102 of the wafer 100 is ground and thinned.
  • the thickness of the wafer 100 before thinning is D
  • the thickness of the wafer 100 after thinning is d.
  • the V-shaped cutting groove 103 and the opening 113 extending toward the first surface 101 of the wafer 100 are simultaneously etched on the second surface 102 of the wafer 100 by an etching process.
  • a pad 112 is exposed at the bottom of the opening 113.
  • the V-shaped cutting groove 103 has the same depth as the opening 113.
  • only the opening 113 may be etched without etching the V-shaped cutting groove 103.
  • the cutting is performed along the V-shaped cutting groove 103 by using a cutter until the first surface 101 of the wafer 100 is cut, that is, cut.
  • the knife cuts into a portion of the support unit 210. Since the material of the wafer 100 is brittle, the toughness and the ductility are poor, and the cutter uses a knife having a relatively high hardness, such as a metal knife. And the cutting width h of the cutter is smaller than the width H of the opening of the V-shaped cutting groove 103 close to the second surface 102, and thus, the V-shaped cutting groove 103 retains the partially inclined side wall 1031.
  • the inclined side wall 1031 has a drainage effect on the photosensitive ink 117 coated in the subsequent process, so that the photosensitive ink 117 is more easily filled with the V-shaped slit 103.
  • the V-shaped cutting groove 103' can be cut from the second surface 102 of the wafer 100 along the gap by using a cutter, and the cutter cuts through the wafer 100.
  • the first surface 101 that is, the cutter cuts into a part of the support unit 210.
  • the V-shaped groove 103' having the inclined side wall 1031' is formed directly by the cutter cutting, and the inclined side wall 1031' has a drainage effect on the photosensitive ink 117 coated in the subsequent process, so that the photosensitive ink 117 is more easily filled with the V-cut. Slot 103'.
  • an insulating layer 114 is formed on the second surface 102 of the wafer 100, the sidewalls and the bottom of the opening 113, and the inner wall of the V-shaped cutting groove 103.
  • the insulating layer 114 is organic.
  • the insulating material having insulation and a certain flexibility, is formed by a spraying or spin coating process, and then the soldering pad 112 is exposed by laser or exposure development.
  • an insulating layer 114' may be deposited on the second surface 102 of the wafer 100, the sidewalls and bottom of the opening 113, and the inner wall of the V-shaped cutting groove 103.
  • the material of the insulating layer 114' is an inorganic material, usually silicon dioxide. Since the impact resistance of the silicon dioxide is not as good as that of the organic insulating material 114, it is also necessary to form a buffer layer 1140 on the second surface of the wafer 101 by an exposure developing process to facilitate subsequent soldering of the ball, and then etching the bottom of the opening 113 by an etching process.
  • the insulating layer exposes the pad 112.
  • a rewiring layer 115 is formed on the insulating layer 114 (or the insulating layer 114'), and the rewiring layer 115 is electrically connected to the pad 112.
  • the key to the invention is that the V-shaped cutting groove 103 is filled with the photosensitive ink, and a cavity 119 is formed between the opening 113 and the photosensitive ink so that the photosensitive ink does not contact the bottom of the opening 113, and the photosensitive ink is prevented from filling the opening 113.
  • the present invention needs to easily fill the cutting groove by reducing the viscosity of the photosensitive ink, and it is necessary to increase the viscosity of the photosensitive ink so that the photosensitive ink is not easily filled into the lower half of the opening, which is a conflict point to be solved by the present invention.
  • the invention can design the cutting groove with the inclined side wall to facilitate the drainage of the higher viscosity photosensitive ink to the lower half of the cutting groove, so that the photosensitive ink can fill the cutting groove and cannot fill the opening and the opening and the photosensitive A cavity is formed between the inks. A good solution to the conflict point.
  • the photosensitive ink 117 is coated on the second surface 102 of the wafer 100, the photosensitive ink 117 is filled with the V-shaped cut 103, the opening 113 is covered, and a cavity 119 is formed between the opening 113 and the photosensitive ink 117.
  • the photosensitive ink of a viscosity of not less than 12 Kcps is preferably used in the present invention.
  • the photosensitive ink 117 is coated on the second surface 102 of the wafer 100 by a spin coating process, and the photosensitive ink 117 can be filled with the V-cut 103 and the opening 113 according to the viscosity of the photosensitive ink and adjusting the spin coating rate. And a cavity 119 is formed between the opening 113 and the photosensitive ink 117.
  • the photosensitive ink 117 forms a solder resist layer, which facilitates the subsequent solder ball process, acts as a solder mask, and protects the chip.
  • a through hole is formed at a position corresponding to the rewiring layer 115 of the photosensitive ink 117.
  • the photosensitive ink 117 is coated from the entire surface 102 of the wafer 100, and then formed by re-solidification and exposure development.
  • the via hole exposes the rewiring layer 115.
  • the photosensitive ink may also be applied to the second surface 102 of the wafer 100 by screen printing and form a through hole exposing the rewiring layer 115.
  • a solder ball 116 is formed in the via hole to electrically connect the solder ball 116 to the rewiring layer 115 by using a solder ball process.
  • the wafer 100 and the protective substrate 200 are cut along the V-shaped dicing groove 103 from the second surface 102 of the wafer 100 toward the first surface 101 of the wafer 100 to obtain a single image sensing chip package structure.
  • the single image sensor chip package structure includes a substrate 310 cut from the wafer 100, and has a first surface 301 and a second surface 302 opposite to the first surface 301.
  • the image sensing region 111 The solder pad 112 is located on the first surface 301, the opening 113 and the solder ball 116 are located on the second surface 302, and the side surface of the substrate 310 is covered by the photosensitive ink 117.
  • the side surface of the substrate 310 includes a slanted sidewall 311 and a vertical sidewall 312.
  • One end of the slanted sidewall 311 is in contact with the second surface 302, and the other end is intersected with the vertical sidewall 312.
  • the vertical sidewall 312 The other end of the hand is interfaced with the first face 301.
  • the substrate 310' has a sloped sidewall 311' having one end that interfaces with the second surface 302 and the other end that interfaces with the first surface 301.
  • the angle of the inclined side wall 311 (or the inclined side wall 311') to the second side 302 of the substrate 310 ranges from 40° to 85°.
  • the side surface of the substrate 310 and a part of the side wall of the support unit 210 are covered by the photosensitive ink 117.
  • the buffer layer 1140 may not be disposed at a position corresponding to the solder ball 116 between the re-wiring layer 115 and the insulating layer 114.
  • a buffer layer 1140 is disposed at a position corresponding to the solder ball 116 between the re-wiring layer 115 and the insulating layer 114', and the buffer layer 1140 is a photoresist material, which may be formed by an exposure developing process.

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Abstract

提供一种影像传感芯片的封装方法以及封装结构，包括：提供晶圆（100），具有第一表面（101）以及与所述第一表面（101）相背的第二表面（102），所述晶圆（100）具有多颗网格排布的影像传感芯片（110），具有影像传感区（111）以及焊垫（112），所述影像传感区（111）以及焊垫（112）位于所述晶圆（100）的第一表面（101）侧；于所述晶圆（100）的第二表面（102）形成朝向第一表面（101）延伸的开孔（113），所述开孔（113）暴露出所述焊垫（112）；于所述晶圆（100）的第二表面（102）形成朝向第一表面（101）延伸的V型切割槽（103）；在所述晶圆（100）第二表面（102）涂布感光油墨（117），使感光油墨（117）充满所述V型切割槽（103），且所述感光油墨（117）覆盖所述开孔（113），并在所述开孔（113）与所述感光油墨（117）之间形成空腔（119），通过在开孔（113）与感光油墨（117）之间形成空腔（119），有效避免再布线层（115）与焊垫（112）脱离的情况，提升了影像传感芯片的封装良率，提高了影像传感芯片封装结构的信赖性。

Description

影像传感芯片的封装方法以及封装结构
本申请要求于2015年10月10日提交中国专利局，申请号201510650103.7，发明名称为“影像传感芯片的封装方法以及封装结构”的中国专利申请的优先权，以及申请号201520780135.4，发明名称为“影像传感芯片封装结构”的中国专利申请的优先权，其全部内容通过引用结合在本申请中。
技术领域
本发明涉及半导体技术领域，尤其涉及晶圆级半导体芯片的封装方法。
背景技术
现今主流的半导体芯片封装技术是晶圆级芯片尺寸封装技术(Wafer Level Chip Size Packaging，WLCSP)，是对整片晶圆进行封装并测试后再切割得到单个成品芯片的技术。利用此种封装技术封装后的单个成品芯片尺寸与单个晶粒尺寸差不多，顺应了市场对微电子产品日益轻、小、短、薄化和低价化要求。晶圆级芯片尺寸封装技术是当前封装领域的热点和未来发展的趋势。
请参考图1，公开一种晶圆级影像传感芯片的封装结构，晶圆1与保护基板2对位压合，支撑单元3位于晶圆1与保护基板2之间使两者之间形成间隙，避免保护基板2与晶圆1直接接触，晶圆1包括多颗网格状排布的影像传感芯片10，影像传感芯片10包括影像传感区11以及焊垫12，多个支撑单元3网格状排布于保护基板2上且与影像传感芯片10对应，当保护基板2与晶圆1对位压合后，支撑单元3包围影像传感区11，晶圆1具有第一表面以及与所述第一表面相背的第二表面，影像传感区11以及焊垫12位于晶圆的第一表面侧。
为了实现焊垫12与其他电路电连接，在晶圆1的第二表面侧设置有朝向第一表面延伸的开孔22，开孔22与焊垫12对应且开孔22的底部暴露出焊垫12，在开孔22的侧壁设置有绝缘层23，绝缘层23上以及开孔22的底部设置有再布线层24，再布线层24与焊垫12电连接，焊球25与再布线层24电连接，通过焊球25电连接其他电路实现焊垫12与其他电路之间形成电连接。
为了便于将封装完成的影像传感芯片切割下来，于晶圆1的第二表面设置有朝向第一表面延伸的切割槽21。
在向晶圆1的第二表面排布焊球25之前，需要涂布防焊油墨26，通常在切割槽21以及开孔22中也填充了防焊油墨26以达到保护、绝缘的效果。
然而，由于防焊油墨26填满开孔22，在后续的回流焊以及信赖性测试中，防焊油墨26的热胀冷缩形成作用于再布线层24的力，在这种力的拉扯下，再布线层24容易与焊垫12脱离，导致芯片不良，成为本领域技术人员噬待解决的技术问题。
发明内容
本发明解决的问题是通过本发明提供的晶圆级影像传感芯片封装方法以及影像传感芯片封装结构，消除再布线层与焊垫脱离的情况，解决芯片不良，提高影像传感芯片封装结构的信赖性。
为解决上述问题，本发明提供一种影像传感芯片的封装方法，包括：提供晶圆，所述晶圆具有第一表面以及与所述第一表面相背的第二表面，所述晶圆具有多颗网格排布的影像传感芯片，影像传感芯片具有影像传感区以及焊垫，所述影像传感区以及焊垫位于所述晶圆的第一表面侧；于所述晶圆的第二表面形成朝向第一表面延伸的开孔，所述开孔暴露出所述焊垫；于所述晶圆的第二 表面形成朝向第一表面延伸的V型切割槽；在所述晶圆的第二表面涂布感光油墨，使感光油墨充满所述V型切割槽,且所述感光油墨覆盖所述开孔，并在所述开孔与所述感光油墨之间形成空腔。
优选的，采用刻蚀工艺同时在晶圆的第二表面形成所述V型切割槽以及所述开孔。
优选的，利用切刀从所述晶圆的第二表面切割形成所述V型切割槽。
优选的，在所述晶圆第二表面形成V型切割槽以及开孔之前还包括：提供保护基板，所述保护基板上设置有网格排布的支撑单元，每一支撑单元对应一个影像传感芯片；将所述晶圆的第一表面与所述保护基板对位压合，所述支撑单元位于所述晶圆与所述保护基板之间；对所述晶圆的第二表面进行研磨减薄。
优选的，在形成V型切割槽之后且在涂布感光油墨之前，利用切刀沿所述V型切割槽切割，所述切刀至少切入部分所述支撑单元中。
优选的，所述切刀的切割宽度小于所述V型槽靠近所述晶圆第二表面的开口的宽度。
优选的，利用切刀从所述晶圆的第二表面切割形成所述V型切割槽且所述切刀至少切入部分所述支撑单元中。
优选的，在涂布感光油墨之前还包括：于所述开孔的侧壁以及所述晶圆的第二表面形成绝缘层；于所述绝缘层上以及所述开孔的底部形成再布线层，使所述再布线层与所述焊垫电连接；在所述晶圆的第二表面涂布感光油墨之后还包括：在所述感光油墨上形成多个通孔，所述通孔暴露出所述再布线层；在所述通孔中形成焊球，所述焊球与所述再布线层电连接。
优选的，所述感光油墨的粘度不小于12Kcps。
本发明还提供一种影像传感芯片封装结构，包括：基底，具有第一面以及 与所述第一面相背的第二面；位于所述第一面的影像传感区以及焊垫；位于所述第二面并向所述第一面延伸的开孔，所述开孔暴露出所述焊垫；包覆所述基底侧面的感光油墨；所述感光油墨覆盖所述开孔，并在所述开孔与所述感光油墨之间形成空腔；所述基底侧面具有倾斜侧壁，所述倾斜侧壁的一端与所述第二面交接。
优选的，所述基底侧面还具有竖直侧壁，所述竖直侧壁的一端与所述倾斜侧壁交接，另一端与所述基底的第一面交接。
优选的，所述倾斜侧壁的另一端与所述基底的第一面交接。
优选的，所述倾斜侧壁到所述基底第二面的角度的范围是40°至85°。
优选的，所述感光油墨的粘度不小于12Kcps。
优选的，所述封装结构还包括：与所述基底第一面对位压合的保护基板；位于所述保护基板与所述基底之间的支撑单元，所述支撑单元包围所述影像传感区；所述感光油墨包覆至少部分所述支撑单元的侧面；位于所述开孔侧壁以及所述基底第二面的绝缘层；位于所述绝缘层上以及开孔底部的再布线层，所述再布线层与所述焊垫电连接；所述感光油墨覆盖所述再布线层，且在所述感光油墨上设置有通孔，所述通孔暴露出所述再布线层；设置在通孔中的焊球，所述焊球与所述再布线层电连接。
本发明的有益效果是在开孔与感光油墨之间，有效避免了再布线层与焊垫脱离的情况，提升了影像传感芯片的封装良率，提高了影像传感芯片封装结构的信赖性。
附图说明
图1为现有技术中晶圆级影像传感芯片的封装结构示意图；
图2晶圆级影像传感芯片的结构示意图；
图3为晶圆级影像传感芯片封装结构的剖面示意图；
图4至图11为本发明晶圆级影像传感芯片封装方法的示意图；
图12为本发明一实施例单颗影像传感芯片封装结构示意图；
图13为本发明另一实施例单颗影像传感芯片封装结构示意图。
具体实施方式
以下将结合附图对本发明的具体实施方式进行详细描述。但这些实施方式并不限制本发明，本领域的普通技术人员根据这些实施方式所做出的结构、方法、或功能上的变换均包含在本发明的保护范围内。
现有技术中防焊油墨填充开孔，使得防焊油墨与再布线层完全接触，导致在后续的回流焊以及信赖性测试中，防焊油墨的收缩膨胀形成的力拉扯再布线层，容易使再布线层与焊垫脱离。
为解决上述问题，本发明通过在开孔与防焊油墨之间形成空腔，使防焊油墨不与开孔底部的布线层接触，能够有效防止再布线层与焊垫脱离。
请参考图2，为晶圆级影像传感芯片的结构示意图，晶圆100具有多颗网格排布的影像传感芯片110，在影像传感芯片110之间预留有空隙，后续完成封装工艺以及测试之后，沿空隙分离影像传感芯片。
每一影像传感芯片110具有影像传感区111以及多个焊垫112，焊垫112位于影像传感区111的侧边且与影像传感区111位于晶元100的同一表面侧。
请参考图3，为本发明一实施例晶圆级影像传感芯片封装结构的剖面示意图。保护基板200的其中一面设置有网格排布的多个支撑单元210，当晶圆100与保护基板200对位压合后，支撑单元210位于晶圆100与保护基板200之间 使两者之间形成间隙，且支撑单元210与影像传感芯片110一一对应，支撑单元210包围影像传感区111。
晶圆100具有第一表面101以及与第一表面101相背的第二表面102，影像传感区111以及焊垫112位于第一表面101侧，在晶圆的第二表面102具有朝向第一表面101延伸的V型切割槽103以及开孔113，每一开孔113与每一焊垫112的位置对应，且开孔113的底部暴露出焊垫112。
利用再布线层115以及焊球116方便焊垫112与其他线路连接，具体的，开孔113的侧壁以及晶圆100的第二表面102具有绝缘层114，在绝缘层114上以及开孔113的底部形成再布线层115，再布线层115与焊垫112电连接，且在晶圆100的第二表面102上设置有焊球116，焊球116与再布线层115电连接，通过焊球116电连接其他电路实现焊垫112与其他电路之间形成电连接。
V型切割槽103内充满感光油墨117，且感光油墨117覆盖开孔113且在开孔113与感光油墨117之间形成空腔119，感光油墨117上具有通孔，通孔暴露出再布线层115，焊球116位于通孔内并与再布线层115电连接。
对应的，为了使V型切割槽103中充满感光油墨117且在开孔113与感光油墨117之间形成空腔119，具体的封装工艺如下。
提供晶圆100，晶圆100的结构示意图请参考图1；
提供保护基板200，在保护基板200的其中一面有网格排布的多个支撑单元210，于本实施例中，支撑单元210的材质为感光油墨，通过曝光显影的方式形成于保护基板200的其中一面。
请参考图4，将晶圆100与保护基板200对位压合，利用粘合胶将晶圆100与保护基板200粘合，支撑单元210位于晶圆100与保护基板200之间，三者包围形成多个网格排布的密封空间。每一密封空间对应一个影像传感芯片110， 支撑单元210包围影像传感芯片110的影像传感区111。
请参考图5，对晶圆100的第二表面102进行研磨减薄。减薄前晶圆100的厚度为D，减薄后晶圆100的厚度为d。
请参考图6，利用刻蚀工艺在晶圆100的第二表面102同时刻蚀出朝向晶圆100第一表面101延伸的V型切割槽103以及开孔113。开孔113底部暴露出焊垫112。于本实施例中，V型切割槽103与开孔113的深度相同。当然，于此步骤中也可以仅仅刻蚀出开孔113而不刻蚀出V型切割槽103。
请参考图7(a)，从晶圆100的第二表面102朝向第一表面101的方向，利用切刀沿V型切割槽103切割，直至切透晶圆100的第一表面101，即切刀切入支撑单元210一部分。由于晶圆100的材质较脆，韧性、延展性较差，切刀采用硬度较大的刀，如金属刀。且切刀的切割宽度h小于V型切割槽103靠近第二表面102的开口的宽度H，如此，V型切割槽103保留了部分倾斜侧壁1031。倾斜侧壁1031对后续工艺中涂布的感光油墨117具有引流作用，使得感光油墨117更容易充满V型切槽103。
请参考图7(b),于本发明的另一实施例中，可以直接采用切刀从晶圆100的第二表面102沿空隙切割出V型切割槽103’，切刀切透晶圆100的第一表面101，即切刀切入支撑单元210一部分。如此，直接通过切刀切割形成具有倾斜侧壁1031’的V型槽103’，倾斜侧壁1031’对后续工艺中涂布的感光油墨117具有引流作用，使得感光油墨117更容易充满V型切槽103’。
请参考图8(a)，在晶圆100的第二表面102、开孔113的侧壁和底部以及V型切割槽103的内壁形成绝缘层114，于本实施例中，绝缘层114为有机绝缘材料，具有绝缘以及一定的柔性，采用喷涂或者旋涂工艺形成绝缘层114，然后通过镭射或者曝光显影的方式暴露出焊垫112。
请参考图8(b)，于本发明的另一实施例中，可以在晶圆100的第二表面102、开孔113的侧壁和底部以及V型切割槽103的内壁沉积绝缘层114’，绝缘层114’的材质为无机材料，通常为二氧化硅。由于二氧化硅抗冲击能力不如有机绝缘材料114，还需要通过曝光显影工艺在晶圆101的第二表面形成缓冲层1140以方便后续上焊球，然后采用刻蚀工艺刻蚀掉开孔113底部的绝缘层露出焊垫112。
请参考图9，在绝缘层114(或者绝缘层114’)上形成再布线层115，再布线层115与焊垫112电连接。
本发明关键要在V型切割槽103充满感光油墨，而在开孔113与感光油墨之间形成空腔119使感光油墨不接触开孔113底部，避免感光油墨充满开孔113。
本发明需要通过降低感光油墨的粘度容易使感光油墨充满切割槽，需要通过提高感光油墨的粘度使感光油墨不容易填充至开孔的下半部分，这是本发明所要解决的冲突点。
本发明通过将切割槽设计成具有倾斜侧壁的切割槽方便将粘度较高的感光油墨引流至切割槽的下半部分，使感光油墨能够充满切割槽而不能充满开孔并在开孔与感光油墨之间形成空腔。很好的解决了冲突点。
请参考图10，在晶圆100的第二表面102涂布感光油墨117，使感光油墨117充满V型切割103、覆盖开孔113并在开孔113与感光油墨117之间形成空腔119。
本发明优选的采用粘度不小于12Kcps的感光油墨。
于本实施例中采用旋涂工艺在晶圆100的第二表面102涂布感光油墨117，可以根据感光油墨的粘度并调整旋涂速率可以使感光油墨117充满V型切割103、覆盖开孔113，并在开孔113与感光油墨117之间形成空腔119。
感光油墨117形成阻焊层，方便后续上焊球工艺，起阻焊、保护芯片的作用。
为了方便后续上焊球，需要在感光油墨117对应再布线层115的位置形成通孔，具体的，通过从晶圆100第二表面102整面涂布感光油墨117，再固化、曝光显影工艺形成通孔，通孔暴露出再布线层115。当然，也可以通过丝网印刷的方式将感光油墨涂布至晶圆100的第二表面102且形成暴露再布线层115的通孔。
请参考图11，采用上焊球工艺，在通孔中形成焊球116使焊球116与再布线层115电连接。
最后，沿V型切割槽103从晶圆100的第二表面102朝向晶圆100的第一表面101切割晶圆100以及保护基板200，得到单颗的影像传感芯片封装结构。
请参考图12，单颗影像传感芯片封装结构包括从晶圆100上切割得到的基底310，其具有第一面301以及与第一面301相背的第二面302，影像传感区111以及焊垫112位于第一面301，开口113以及焊球116位于第二面302，基底310的侧面被感光油墨117包覆。
于本实施例中，基底310的侧面包括倾斜侧壁311以及竖直侧壁312，倾斜侧壁311的一端与第二面302交接，另一端与竖直侧壁312交接，竖直侧壁312的另一端与第一面301交接。
于另一实施例中，请参考图13，基底310’具有倾斜侧壁311’，其一端与第二面302交接，另一端与第一面301交接。
优选的，倾斜侧壁311(或者倾斜侧壁311’)到基底310第二面302的角度的范围是40°至85°。
基底310的侧面以及支撑单元210的部分侧壁被感光油墨117包覆。
当绝缘层114为有机绝缘材料时，再布线层115与绝缘层114之间对应焊球116的位置可以不设置缓冲层1140。
当绝缘层114’为无机材料时，再布线层115与绝缘层114’之间对应焊球116的位置设置有缓冲层1140，缓冲层1140为光阻材料，可以采用曝光显影工艺形成。
应当理解，虽然本说明书按照实施方式加以描述，但并非每个实施方式仅包含一个独立的技术方案，说明书的这种叙述方式仅仅是为清楚起见，本领域技术人员应当将说明书作为一个整体，各实施方式中的技术方案也可以经适当组合，形成本领域技术人员可以理解的其他实施方式。
上文所列出的一系列的详细说明仅仅是针对本发明的可行性实施方式的具体说明，它们并非用以限制本发明的保护范围，凡未脱离本发明技艺精神所作的等效实施方式或变更均应包含在本发明的保护范围之内。

Claims (15)

  1. 一种影像传感芯片的封装方法，包括：
    提供晶圆，所述晶圆具有第一表面以及与所述第一表面相背的第二表面，所述晶圆具有多颗网格排布的影像传感芯片，影像传感芯片具有影像传感区以及焊垫，所述影像传感区以及焊垫位于所述晶圆的第一表面侧；
    于所述晶圆的第二表面形成朝向第一表面延伸的开孔，所述开孔暴露出所述焊垫；
    其特征在于，所述封装方法还包括：
    于所述晶圆的第二表面形成朝向第一表面延伸的V型切割槽；以及
    在所述晶圆的第二表面涂布感光油墨，使感光油墨充满所述V型切割槽,且所述感光油墨覆盖所述开孔并在所述开孔与感光油墨之间形成空腔。
  2. 根据权利要求1所述的影像传感芯片封装方法，其特征在于，采用刻蚀工艺同时在晶圆的第二表面形成所述V型切割槽以及所述开孔。
  3. 根据权利要求1所述的影像传感芯片封装方法，其特征在于，利用切刀从所述晶圆的第二表面切割形成所述V型切割槽。
  4. 根据权利要求1所述的影像传感芯片封装方法，其特征在于，在所述晶圆第二表面形成V型切割槽以及开孔之前还包括：
    提供保护基板，所述保护基板上设置有网格排布的支撑单元，每一支撑单元对应一个影像传感芯片；
    将所述晶圆的第一表面与所述保护基板对位压合，所述支撑单元位于所述晶圆与所述保护基板之间；以及
    对所述晶圆的第二表面进行研磨减薄。
  5. 根据权利要求4所述的影像传感芯片封装方法，其特征在于，在形成V型切割槽之后且在涂布感光油墨之前，利用切刀沿所述V型切割槽切割，所述切刀至少切入部分所述支撑单元中。
  6. 根据权利要求5所述的影像传感芯片封装方法，其特征在于，所述切刀的切割宽度小于所述V型槽靠近所述晶圆第二表面的开口的宽度。
  7. 根据权利要求4所述的影像传感芯片封装方法，其特征在于，利用切刀从所述晶圆的第二表面切割形成所述V型切割槽且所述切刀至少切入部分所述支撑单元中。
  8. 根据权利要求1所述的影像传感芯片封装方法，其特征在于，
    在涂布感光油墨之前还包括：
    于所述开孔的侧壁以及所述晶圆的第二表面形成绝缘层；以及
    于所述绝缘层上以及所述开孔的底部形成再布线层，使所述再布线层与所述焊垫电连接；
    在所述晶圆的第二表面涂布感光油墨之后还包括：
    在所述感光油墨上形成多个通孔，所述通孔暴露出所述再布线层；以及
    在所述通孔中形成焊球，所述焊球与所述再布线层电连接。
  9. 根据权利要求1所述的影像传感芯片封装方法，其特征在于，所述感光油墨的粘度不小于12Kcps。
  10. 一种影像传感芯片封装结构，包括：
    基底，具有第一面以及与所述第一面相背的第二面；
    位于所述第一面的影像传感区以及焊垫；
    位于所述第二面并向所述第一面延伸的开孔，所述开孔暴露出所述焊垫；以及
    包覆所述基底侧面的感光油墨；
    其特征在于：
    所述感光油墨覆盖所述开孔，并在所述开孔与感光油墨之间形成空腔；
    所述基底侧面具有倾斜侧壁，所述倾斜侧壁的一端与所述第二面交接。
  11. 根据权利要求10所述的影像传感芯片封装结构，其特征在于，所述基底侧面还具有竖直侧壁，所述竖直侧壁的一端与所述倾斜侧壁交接，另一端与所述基底的第一面交接。
  12. 根据权利要求10所述的影像传感芯片封装结构，其特征在于，所述倾斜侧壁的另一端与所述基底的第一面交接。
  13. 根据权利要求10所述的影像传感芯片封装结构，其特征在于，所述倾斜侧壁到所述基底第二面的角度的范围是40°至85°。
  14. 根据权利要求10所述的影像传感芯片封装结构，其特征在于，所述感光油墨的粘度不小于12Kcps。
  15. 根据权利要求10所述的影像传感芯片封装结构，其特征在于，所述封装结构还包括：
    与所述基底第一面对位压合的保护基板；
    位于所述保护基板与所述基底之间的支撑单元，所述支撑单元包围所述影像传感区，所述感光油墨包覆至少部分所述支撑单元的侧面；
    位于所述开孔侧壁以及所述基底第二面的绝缘层；
    位于所述绝缘层上以及开孔底部的再布线层，所述再布线层与所述焊垫电连接，所述感光油墨覆盖所述再布线层，且在所述感光油墨上设置有通孔，所述通孔暴露出所述再布线层；以及
    设置在通孔中的焊球，所述焊球与所述再布线层电连接。
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