TWI645478B - 半導體晶片的封裝方法以及封裝結構 - Google Patents

半導體晶片的封裝方法以及封裝結構 Download PDF

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Publication number
TWI645478B
TWI645478B TW106116913A TW106116913A TWI645478B TW I645478 B TWI645478 B TW I645478B TW 106116913 A TW106116913 A TW 106116913A TW 106116913 A TW106116913 A TW 106116913A TW I645478 B TWI645478 B TW I645478B
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Taiwan
Prior art keywords
wafer
metal wiring
hole
solder resist
wiring layer
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TW106116913A
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English (en)
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TW201810453A (zh
Inventor
王之奇
謝國梁
胡漢青
王文斌
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蘇州晶方半導體科技股份有限公司
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Priority claimed from CN201610351529.7A external-priority patent/CN106409771B/zh
Priority claimed from CN201620484861.6U external-priority patent/CN206116374U/zh
Application filed by 蘇州晶方半導體科技股份有限公司 filed Critical 蘇州晶方半導體科技股份有限公司
Publication of TW201810453A publication Critical patent/TW201810453A/zh
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Abstract

本申請實施例提供一種半導體晶片的封裝方法以及封裝結構，所述封裝方法包括：提供晶圓，所述晶圓具有多個半導體晶片，每一半導體晶片具有位於第一表面側的功能區以及焊墊；提供保護基板，所述保護基板上設置多個支撐單元，所述支撐單元上形成有開孔；使所述焊墊對準所述開孔、保護基板上設置的支撐單元面對所述晶圓的第一表面，將所述晶圓與所述保護基板壓合。本申請能有效防止支撐單元在後續的信賴性測試中產生的應力作用於焊墊，避免了焊墊損壞或者分層的情況。

Description

半導體晶片的封裝方法以及封裝結構
本申請涉及半導體技術領域，尤其涉及晶圓級半導體晶片的封裝技術。
現今主流的半導體晶片封裝技術是晶圓級晶片尺寸封裝技術(Wafer Level Chip Size Packaging，WLCSP)，是對整片晶圓進行封裝並測試後再切割得到單個成品晶片的技術。利用此種封裝技術封裝後的單個成品晶片尺寸與單個晶粒尺寸差不多，順應了市場對微電子產品日益輕、小、短、薄化和低價化要求。晶圓級晶片尺寸封裝技術是當前封裝領域的熱點和未來發展的趨勢。
晶圓包括多顆半導體晶片，半導體晶片的其中一面上具有功能區以及位於功能區週邊並與功能區電連接的焊墊。為了對功能區進行保護，在晶圓上壓合保護基板，保護基板上設置有支撐單元。支撐單元與晶圓上對應焊墊的位置接觸，由於支撐單元的熱膨脹係數與晶圓的熱膨脹係數不同，在信賴性測試中支撐單元形成作用於焊墊的應力，容易使焊墊損壞，特別是如果焊墊是多層結構，該應力容易導致焊墊分層。
本申請提供一種晶圓級半導體晶片封裝方法以及半導體晶片封裝結構，解決焊墊損壞的問題，提高半導體晶片封裝結構的品質以及信賴性。
為解決上述問題，本申請提供一種半導體晶片的封裝方法，包括：提供晶圓，所述晶圓具有彼此相對的第一表面以及第二表面，所述晶圓具有多個半導體晶片，每一半導體晶片具有位於所述第一表面側的功能區以及焊墊；提供保護基板，所述保護基板的一個表面上設置多個支撐單元，所述支撐單元上形成有開孔；使所述焊墊對準所述開孔、保護基板上設置的 支撐單元面對所述晶圓的第一表面，將所述晶圓與所述保護基板壓合。
優選地，所述多個半導體晶片呈網格排布，一個支撐單元對應一個半導體晶片，和/或所述功能區位於所述支撐單元包圍形成的密封腔內。優選地，在將所述晶圓與所述保護基板壓合之前，所述方法還包含如下步驟：在所述支撐單元上形成所述開孔，使所述晶圓的第一表面上對應焊墊的位置不接觸所述支撐單元。
優選地，所述支撐單元的材質為感光膠，透過曝光顯影工藝同步形成所述支撐單元以及所述支撐單元上的開孔。
優選地，所述多個支撐單元呈網格狀排布，在形成網格狀排布的多個支撐單元之後，採用雷射打孔工藝形成所述開孔。
優選地，在將所述晶圓與所述保護基板壓合之後，包含如下步驟：於所述晶圓的第二表面上形成與所述焊墊一一對應的多個通孔，通孔底部暴露所述焊墊；於所述通孔的底部以及側壁形成金屬佈線層，所述金屬佈線層延伸至所述晶圓的第二表面，所述金屬佈線層與所述焊墊電連接；形成覆蓋所述晶圓的第二表面的阻焊層，所述阻焊層填充所述通孔且所述阻焊層對應通孔的位置形成凹槽；在所述阻焊層上設置開口，所述開口底部暴露所述金屬佈線層；於所述開口中形成焊接凸起，所述焊接凸起與所述金屬佈線層電連接。
優選地，採用噴塗工藝形成所述阻焊層，所述阻焊層均勻覆蓋所述通孔的側壁以及底部。
優選地，採用旋塗工藝於所述晶圓的第二表面以及所述通孔中形成阻焊層；採用蝕刻工藝或者雷射打孔工藝在所述阻焊層上對應通孔的位置形成所述凹槽。
優選地，所述凹槽的深度與所述通孔的深度之間的差值為0-20微米，所述阻焊層的材質為感光膠。
優選地，在將所述晶圓與所述保護基板壓合之後，還包含如下步驟：於所述晶圓的第二表面上形成與所述焊墊一一對應的多個通孔，通孔底部暴露所述焊墊；於所述通孔的底部以及側壁形成金屬佈線層，所述金屬佈 線層延伸至所述晶圓的第二表面，所述金屬佈線層與所述焊墊電連接；形成覆蓋所述晶圓的第二表面的阻焊層，所述阻焊層覆蓋所述通孔並在所述通孔中形成空腔；在所述阻焊層上設置開口，所述開口底部暴露所述金屬佈線層；於所述開口中形成焊接凸起，所述焊接凸起與所述金屬佈線層電連接。
優選地，採用旋塗工藝形成所述阻焊層，所述阻焊層的黏度大於12Kcps。
優選地，所述半導體晶片為影像傳感晶片，所述功能區具有光敏感器件。
本申請還提供一種半導體晶片封裝結構，包括：基底，具有彼此相對的第一表面以及第二表面；功能區以及焊墊，兩者均位於所述基底第一表面側；保護基板，位於所述基底第一表面；支撐單元，位於所述保護基板與所述基底之間，所述功能區位於所述支撐單元包圍形成的密封腔內；所述支撐單元上設置有開孔，使所述晶圓的第一表面上對應焊墊的位置不接觸所述支撐單元。
優選地，所述支撐單元的材質為感光膠。
優選地，所述封裝結構還包括：位於所述基底的第二表面且與所述焊墊一一對應的通孔，所述通孔底部暴露所述焊墊；位於所述通孔的底部以及側壁的金屬佈線層，所述金屬佈線層延伸至所述基底的第二表面，所述金屬佈線層與所述焊墊電連接；覆蓋所述基底的第二表面的阻焊層，所述阻焊層填充所述通孔且所述阻焊層對應通孔的位置形成凹槽；位於所述阻焊層上的開口，所述開口底部暴露所述金屬佈線層；位於所述開口中的焊接凸起，所述焊接凸起與所述金屬佈線層電連接。
優選地，所述阻焊層覆蓋所述通孔的側壁以及底部。
優選地，所述凹槽的深度與所述通孔的深度之間的差值為0-20微米，所述阻焊層的材質為感光膠。
優選地，所述封裝結構還包括：位於所述基底的第二表面且與所述焊墊一一對應的通孔，所述通孔底部暴露所述焊墊；位於所述通孔的底部以及側壁的金屬佈線層，所述金屬佈線層延伸至所述基底的第二表面，所述金屬佈線層與所述焊墊電連接；覆蓋所述基底的第二表面的阻焊層，所述 阻焊層覆蓋所述通孔並在所述通孔中形成空腔；位於所述阻焊層上的開口，所述開口底部暴露所述金屬佈線層；位於所述開口中的焊接凸起，所述焊接凸起與所述金屬佈線層電連接。
優選地，所述阻焊層的黏度大於12Kcps。
優選地，所述半導體晶片為影像傳感晶片，所述功能區具有光敏感器件。
本申請的有益效果是透過在支撐單元上形成開孔，使晶圓上對應焊墊的位置不接觸支撐單元，有效防止支撐單元在後續的信賴性測試中產生的應力作用於焊墊，避免了焊墊損壞或者分層的情況，提升了半導體晶片的封裝良率，提高了半導體晶片封裝結構的信賴性。
1‧‧‧晶圓
2‧‧‧保護基板
3‧‧‧支撐單元
10‧‧‧半導體晶片
11‧‧‧功能區
12‧‧‧焊墊
13‧‧‧密封腔
21‧‧‧切割槽
22‧‧‧通孔
23‧‧‧絕緣層
24‧‧‧金屬佈線層
25‧‧‧焊接凸起
100‧‧‧晶圓
101‧‧‧第一表面
102‧‧‧第二表面
103‧‧‧切割槽
110‧‧‧半導體晶片
111‧‧‧功能區
112‧‧‧焊墊
113‧‧‧通孔
114、114’‧‧‧絕緣層
115‧‧‧金屬佈線層
116‧‧‧焊接凸起
117、117’、117”‧‧‧阻焊層
118‧‧‧凹槽
119‧‧‧空腔
120‧‧‧開口
200‧‧‧保護基板
210‧‧‧支撐單元
211‧‧‧開孔
220‧‧‧密封腔
301‧‧‧第一表面
302‧‧‧第二表面
1140‧‧‧緩衝層
d‧‧‧減薄後晶圓的厚度
D‧‧‧減薄前晶圓的厚度
圖1為晶圓級半導體晶片的封裝結構示意圖；圖2晶圓級半導體晶片的結構示意圖；圖3為本申請實施例中晶圓級半導體晶片封裝結構的剖面示意圖；圖4至圖11為申請實施例晶圓級半導體晶片封裝方法的示意圖；圖12為本申請實施例單個半導體晶片封裝結構示意圖。
以下將結合附圖對本發明的具體實施方式進行詳細描述。但這些實施方式並不限制本發明，本領域的通常技術人員根據這些實施方式所做出的結構、方法、或功能上的變換均包含在本發明的保護範圍內。
半導體晶片上通常積體化有敏感器件，在對其進行封裝時，需要對其上的敏感器件進行保護。請參考圖1，公開一種晶圓級半導體晶片的封裝結構，晶圓(Wafer)1包括多顆網格狀排布的半導體晶片10，半導體晶片10的其中一面上具有功能區11以及位於功能區11週邊並與功能區11電連接的焊墊12。由於功能區積體化有敏感器件，為了對功能區11進行保護，在晶圓1上壓合保護基板2，保護基板2上設置有多個網格狀排布的支撐單元3，支撐單元3與半導體晶片10一一對應，當晶圓1與保護基板2對位壓合後，支撐單元3位於晶圓1與保護基板2之間使晶圓1與保護基板2之間形成間隙，避免保護基板2與晶圓1直接接觸，功能區11位於支撐單元3包圍形成的密封腔 13內。
由於焊墊12與功能區11位於晶圓1的第一表面，為了實現焊墊12與外部電路電連接，在晶圓1與保護基板2對位壓合之後，透過TSV或者TSL工藝在晶圓1的第二表面形成與焊墊12電連接的焊接凸起25，透過焊接凸起25電連接其他電路實現在焊墊12與其他電路之間形成電連接。
為了實現焊墊12與其他電路電連接，在晶圓1的第二表面側設置有朝向第一表面延伸的通孔22，通孔22與焊墊12對應且通孔22的底部暴露出焊墊12，在通孔22的側壁以及晶圓1的第二表面上設置有絕緣層23，絕緣層23上以及通孔22的底部設置有金屬佈線層24，金屬佈線層24與焊墊12電連接，在晶圓的第二表面上設置焊接凸起25，焊接凸起25與金屬佈線層24電連接。為了便於將封裝完成的傳感晶片(該傳感晶片的一個例子是影像傳感晶片)切割下來，於晶圓1的第二表面設置有朝向第一表面延伸的切割槽21。
由於支撐單元3與晶圓1的熱膨脹係數不同，在後續的信賴性測試中支撐單元3會產生作用於焊墊12的應力而造成焊墊12損壞，特別是當焊墊12為多層結構的時候，支撐單元3作用於焊墊12的應力會導致焊墊12分層。
為解決焊墊損壞和/或分層的問題，本發明實施例透過在支撐單元上形成開孔，使晶圓上對應焊墊的位置不接觸支撐單元，有效防止支撐單元在後續的信賴性測試中產生的應力作用於焊墊，避免了焊墊損壞或者分層的情況，提升了半導體晶片的封裝良率，提高了半導體晶片封裝結構的信賴性。
請參考圖2，為晶圓級半導體晶片的結構示意圖，晶圓100具有多顆網格排布的半導體晶片110，在半導體晶片110之間預留有空隙，後續完成封裝工藝以及測試之後，沿空隙分離半導體晶片。
每一半導體晶片110具有功能區111以及多個焊墊112，焊墊112位於功能區111的側邊且與功能區111位於晶圓100的同一表面側。
請參考圖3，為本發明實施例晶圓級半導體晶片封裝結構的剖面示意圖。保護基板200的其中一面設置有網格排布的多個支撐單元210，當晶圓100與保護基板200對位壓合後，支撐單元210位於晶圓100與保護基板200之間使兩者之間形成間隙，且支撐單元210與半導體晶片110一一對應，功能區111位於支撐單元210包圍形成的密封腔220內。
晶圓100具有彼此相對的第一表面101以及第二表面102，功能區111以及焊墊112位於第一表面101側，在晶圓的第二表面102具有朝向第一表面101延伸的切割槽103以及通孔113，每一通孔113與每一焊墊112的位置對應，且通孔113的底部暴露出焊墊112。
利用金屬佈線層115以及焊接凸起116實現焊墊112與外部線路連通，具體的，通孔113的側壁以及晶圓100的第二表面102具有絕緣層114，在通孔113的底部以及側壁形成與焊墊112電連接的金屬佈線層115，金屬佈線層115延伸至晶圓100的第二表面102，金屬佈線層115位於絕緣層114上方，阻焊層117位於金屬佈線層115的上方，阻焊層117覆蓋於晶圓100的第二表面102並填充切割槽103以及通孔113，阻焊層117上設置有開口，開口底部暴露出金屬佈線層115，焊接凸起116位於開口內並與金屬佈線層115電連接，透過焊接凸起116電連接外部電路實現焊墊112與外部電路的連通。
支撐單元210上形成開孔211，使晶圓100上對應焊墊112的位置不接觸支撐單元210，有效防止支撐單元210在後續的信賴性測試中產生的應力作用於焊墊112，避免了焊墊112損壞或者分層的情況，提升了半導體晶片的封裝良率，提高了半導體晶片封裝結構的信賴性。
形成如圖3所示的半導體晶片封裝結構的具體的封裝工藝如下。
提供晶圓100，晶圓100的結構示意圖請參考圖2；提供保護基板200，在保護基板200的其中一面形成網格排布的多個支撐單元210，在實施例中，支撐單元210的材質為感光膠。透過整面塗布感光膠然後採用曝光顯影工藝將支撐單元210以及開孔211同步形成於保護基板200的其中一面。
或者，透過絲網印刷工藝將網格排布的支撐單元210以及開孔211同步形成於保護基板200的其中一面。
或者，透過曝光顯影工藝先形成支撐單元210，再利用雷射打孔工藝在支撐單元210上對應焊墊112的位置形成開孔211。
或者，透過絲網印刷工藝先形成支撐單元210，再利用雷射打孔工藝在支撐單元210上對應焊墊112的位置形成開孔211。
請參考圖4，將晶圓100與保護基板200對位壓合，利用黏合膠將晶圓100與保護基板200黏合，支撐單元210位於晶圓100與保護基板200之間，每一 支撐單元210對應一個半導體晶片110，半導體晶片110的功能區111位於支撐單元210包圍形成的密封腔220內。
請參考圖5，對晶圓100的第二表面102進行研磨減薄。減薄前晶圓100的厚度為D(請參考圖4)，減薄後晶圓100的厚度為d。
請參考圖6，利用切割工藝在晶圓100的第二表面102上切割出切割槽103，切割槽103部分切入支撐單元210中但並不切穿支撐單元210。利用蝕刻工藝在晶圓100的第二表面102蝕刻出通孔113，通孔113底部暴露出焊墊112。
於本發明的另一實施例中，也可以先蝕刻出通孔113然後切割出切割槽103。
請參考圖7(a)，在晶圓100的第二表面102、通孔113的側壁和底部以及切割槽103的側壁和底部形成絕緣層114，於本實施例中，絕緣層114為有機絕緣材料，具有絕緣以及一定的柔性，採用噴塗或者旋塗工藝形成絕緣層114，然後透過雷射或者曝光顯影的方式暴露出焊墊112。
請參考圖7(b)，也可以在晶圓100的第二表面102、通孔113的側壁和底部以及切割槽103的側壁和底部沉積絕緣層114’，絕緣層114’的材質為無機材料，通常為二氧化矽。優選地，由於二氧化矽抗衝擊能力不如有機絕緣材料，可以透過曝光顯影工藝在晶圓101的第二表面形成緩衝層1140以方便後續形成焊接凸起。然後，採用蝕刻工藝蝕刻掉通孔113底部的絕緣層露出焊墊112。
請參考圖8，在絕緣層114(或者絕緣層114’)上形成金屬佈線層115，金屬佈線層115位於通孔113的側壁以及底部並延伸至晶圓100的第二表面102，金屬佈線層115與焊墊112電連接。優選地，金屬佈線層115的厚度範圍是1-5微米。
請參考圖9(a)，採用旋塗工藝在切割槽103、通孔113以及晶圓的第二表面102形成阻焊層117，方便後續上焊球工藝，起阻焊、保護晶片的作用。
請參考圖9(b)，在本發明的另一實施例中，採用噴塗工藝在切割槽103的側壁和底部、通孔113的側壁和底部以及晶圓100的第二表面102形成厚度均勻的阻焊層117’，因阻焊層117’厚度均勻，因此，在阻焊層117’對應通孔113的位置形成了凹槽118，從而降低了通孔113內的阻焊層117’材料的填充 量，降低了阻焊層117’在後續的回流焊以及信賴性測試中作用於金屬佈線層115上的應力，避免金屬佈線層115與焊墊112分層脫離的情況。
優選地，阻焊層117’的厚度範圍是5-20微米。
當然，也可以在圖9(a)的噴塗工藝之後，採用蝕刻工藝或者雷射打孔工藝在阻焊層117對應通孔113的位置形成凹槽。
凹槽(例如凹槽118)的深度與通孔113的深度之間的差值為0-20微米。
請參考圖9(c)，在本發明的又一實施例中，為了避免金屬佈線層115與焊墊112分層脫離的情況，採用旋塗工藝在晶圓100的第二表面102上形成的阻焊層117”，阻焊層117”覆蓋通孔113並在通孔113中形成空腔119，如此，減少阻焊層117”與通孔113的接觸面積，消除了阻焊層117”在後續的回流焊以及信賴性測試中作用於金屬佈線層115上的應力，從而避免金屬佈線層115與焊墊112分層脫離的情況。
優選地，阻焊層117”的黏度大於12Kcps。
優選地，為了在通孔113中形成空腔119，需要提升旋塗的速率，且為了使阻焊層117”充滿切割槽103，將切割槽103的側壁設置成斜面以利於阻焊層117”填充。
本實施例中，阻焊層117、117’和/或117”的材質可以為感光膠。
請參考圖10，透過曝光顯影工藝在晶圓100的第二表面上形成開口120，開口120的底部暴露金屬佈線層115。
請參考圖11，採用上焊球工藝，在開口120中形成焊接凸起116使焊接凸起116與金屬佈線層115電連接。
最後，沿切割槽103從晶圓100的第二表面102朝向晶圓100的第一表面101切割晶圓100以及保護基板200，得到單顆的半導體晶片封裝結構。
請參考圖12，單顆半導體晶片封裝結構包括從晶圓100上切割得到的基底310，其具有彼此相對的第一表面301以及第二表面302，功能區111以及焊墊112位於第一表面301，通孔113以及焊接凸起116位於第二表面302，基底310的側壁被阻焊層117包覆。
支撐單元210上形成開孔211，使基底310上對應焊墊112的位置不接觸支撐單元210，有效防止支撐單元210在後續的信賴性測試中產生的應力作用於焊墊112，避免了焊墊112損壞或者分層的情況，提升了半導體晶片的 封裝良率，提高了半導體晶片封裝結構的信賴性。
本實施例中的半導體晶片可以為影像傳感晶片，功能區具有光敏感器件。當然，本發明實施例中的半導體晶片不限於影像傳感晶片。
本發明實施例的有益效果是透過在支撐單元上形成開孔，使晶圓上對應焊墊的位置不接觸支撐單元，有效防止支撐單元在後續的信賴性測試中產生的應力作用於焊墊，避免了焊墊損壞或者分層的情況，提升了半導體晶片的封裝良率，提高了半導體晶片封裝結構的信賴性。
應當理解，雖然本說明書按照實施方式加以描述，但並非每個實施方式僅包含一個獨立的技術方案，說明書的這種敘述方式僅僅是為清楚起見，本領域技術人員應當將說明書作為一個整體，各實施方式中的技術方案也可以經適當組合，形成本領域技術人員可以理解的其他實施方式。
上文所列出的一系列的詳細說明僅僅是針對本發明的可行性實施方式的具體說明，它們並非用以限制本發明的保護範圍，凡未脫離本發明技藝精神所作的均等實施方式或變更均應包含在本發明的保護範圍之內。
本申請要求於2016年5月25日提交中國專利局，申請號為201610351529.7，發明名稱為“半導體晶片的封裝方法以及封裝結構”以及2016年5月25日提交中國專利局，申請號為201620484861.6，發明名稱為“半導體晶片封裝結構”的中國專利申請的優先權，其全部內容透過引用結合在本申請中。

Claims (20)

  1. 一種半導體晶片的封裝方法，包括：提供晶圓，所述晶圓具有彼此相對的第一表面以及第二表面，所述晶圓具有多個半導體晶片，每一半導體晶片具有位於所述第一表面側的功能區以及焊墊；提供保護基板，所述保護基板的一個表面上設置多個支撐單元，所述支撐單元上形成有開孔；使所述焊墊對準所述開孔、保護基板上設置的支撐單元面對所述晶圓的第一表面，將所述晶圓與所述保護基板壓合。
  2. 如請求項1所述的半導體晶片封裝方法，其中，所述多個半導體晶片呈網格排布，一個支撐單元對應一個半導體晶片，和/或所述功能區位於所述支撐單元包圍形成的密封腔內。
  3. 如請求項1所述的半導體晶片封裝方法，其中，在將所述晶圓與所述保護基板壓合之前，所述方法還包含如下步驟：在所述支撐單元上形成所述開孔，使所述晶圓的第一表面上對應焊墊的位置不接觸所述支撐單元。
  4. 如請求項1所述的半導體晶片封裝方法，其中，所述支撐單元的材質為感光膠，透過曝光顯影工藝同步形成所述支撐單元以及所述支撐單元上的開孔。
  5. 如請求項1所述的半導體晶片封裝方法，其中，所述多個支撐單元呈網格狀排布，在形成網格狀排布的多個支撐單元之後，採用雷射打孔工藝形成所述開孔。
  6. 如請求項1所述的半導體晶片封裝方法，其中，在將所述晶圓與所述保護基板壓合之後，還包含如下步驟：於所述晶圓的第二表面上形成與所述焊墊一一對應的多個通孔，通孔底部暴露所述焊墊；於所述通孔的底部以及側壁形成金屬佈線層，所述金屬佈線層延伸至所述晶圓的第二表面，所述金屬佈線層與所述焊墊電連接；形成覆蓋所述晶圓的第二表面的阻焊層，所述阻焊層填充所述通孔且所述阻焊層對應通孔的位置形成凹槽；在所述阻焊層上設置開口，所述開口底部暴露所述金屬佈線層；於所述開口中形成焊接凸起，所述焊接凸起與所述金屬佈線層電連接。
  7. 如請求項6所述的半導體晶片封裝方法，其中，採用噴塗工藝形成所述阻焊層，所述阻焊層均勻覆蓋所述通孔的側壁以及底部。
  8. 如請求項6所述的半導體晶片封裝方法，其中，採用旋塗工藝於所述晶圓的第二表面以及所述通孔中形成阻焊層；採用蝕刻工藝或者雷射打孔工藝在所述阻焊層上對應通孔的位置形成所述凹槽。
  9. 如請求項6所述的半導體晶片封裝方法，其中，所述凹槽的深度與所述通孔的深度之間的差值為0-20微米，所述阻焊層的材質為感光膠。
  10. 如請求項1所述的半導體晶片封裝方法，其中，在將所述晶圓與所述保護基板壓合之後，還包含如下步驟：於所述晶圓的第二表面上形成與所述焊墊一一對應的多個通孔，通孔底部暴露所述焊墊；於所述通孔的底部以及側壁形成金屬佈線層，所述金屬佈線層延伸至所述晶圓的第二表面，所述金屬佈線層與所述焊墊電連接；形成覆蓋所述晶圓的第二表面的阻焊層，所述阻焊層覆蓋所述通孔並在所述通孔中形成空腔；在所述阻焊層上設置開口，所述開口底部暴露所述金屬佈線層；於所述開口中形成焊接凸起，所述焊接凸起與所述金屬佈線層電連接。
  11. 如請求項10所述的半導體晶片封裝方法，其中，採用旋塗工藝形成所述阻焊層，所述阻焊層的黏度大於12Kcps。
  12. 如請求項1所述的半導體晶片封裝方法，其中，所述半導體晶片為影像傳感晶片，所述功能區具有光敏感器件。
  13. 一種半導體晶片封裝結構，包括：基底，具有彼此相對的第一表面以及第二表面；功能區以及焊墊，兩者均位於所述基底第一表面側；保護基板，位於所述基底第一表面；支撐單元，位於所述保護基板與所述基底之間，所述功能區位於所述支撐單元包圍形成的密封腔內；其中，所述支撐單元上設置有開孔，所述開孔對準所述焊墊，使所述晶圓的第一表面上對應焊墊的位置不接觸所述支撐單元。
  14. 如請求項13所述的半導體晶片封裝結構，其中，所述支撐單元的材質為感光膠。
  15. 如請求項13所述的半導體晶片封裝結構，其中，所述封裝結構還包括：位於所述基底的第二表面且與所述焊墊一一對應的通孔，所述通孔底部暴露所述焊墊；位於所述通孔的底部以及側壁的金屬佈線層，所述金屬佈線層延伸至所述基底的第二表面，所述金屬佈線層與所述焊墊電連接；覆蓋所述基底的第二表面的阻焊層，所述阻焊層填充所述通孔且所述阻焊層對應通孔的位置形成凹槽；位於所述阻焊層上的開口，所述開口底部暴露所述金屬佈線層；位於所述開口中的焊接凸起，所述焊接凸起與所述金屬佈線層電連接。
  16. 如請求項15所述的半導體晶片封裝結構，其中，所述阻焊層覆蓋所述通孔的側壁以及底部。
  17. 如請求項15所述的半導體晶片封裝結構，其中，所述凹槽的深度與所述通孔的深度之間的差值為0-20微米，所述阻焊層的材質為感光膠。
  18. 如請求項13所述的半導體晶片封裝結構，其中，所述封裝結構還包括：位於所述基底的第二表面且與所述焊墊一一對應的通孔，所述通孔底部暴露所述焊墊；位於所述通孔的底部以及側壁的金屬佈線層，所述金屬佈線層延伸至所述基底的第二表面，所述金屬佈線層與所述焊墊電連接；覆蓋所述基底的第二表面的阻焊層，所述阻焊層覆蓋所述通孔並在所述通孔中形成空腔；位於所述阻焊層上的開口，所述開口底部暴露所述金屬佈線層；位於所述開口中的焊接凸起，所述焊接凸起與所述金屬佈線層電連接。
  19. 如請求項18所述的半導體晶片封裝結構，其中，所述阻焊層的黏度大於12Kcps。
  20. 如請求項13所述的半導體晶片封裝結構，其中，所述半導體晶片為影像傳感晶片，所述功能區具有光敏感器件。
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