WO2011093155A1 - 昇降圧dc-dcコンバータおよびスイッチング制御回路 - Google Patents
昇降圧dc-dcコンバータおよびスイッチング制御回路 Download PDFInfo
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- WO2011093155A1 WO2011093155A1 PCT/JP2011/050627 JP2011050627W WO2011093155A1 WO 2011093155 A1 WO2011093155 A1 WO 2011093155A1 JP 2011050627 W JP2011050627 W JP 2011050627W WO 2011093155 A1 WO2011093155 A1 WO 2011093155A1
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- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M3/00—Conversion of dc power input into dc power output
- H02M3/02—Conversion of dc power input into dc power output without intermediate conversion into ac
- H02M3/04—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters
- H02M3/10—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode
- H02M3/145—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal
- H02M3/155—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only
- H02M3/156—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators
- H02M3/158—Conversion of dc power input into dc power output without intermediate conversion into ac by static converters using discharge tubes with control electrode or semiconductor devices with control electrode using devices of a triode or transistor type requiring continuous application of a control signal using semiconductor devices only with automatic control of output voltage or current, e.g. switching regulators including plural semiconductor devices as final control devices for a single load
- H02M3/1582—Buck-boost converters
-
- H—ELECTRICITY
- H02—GENERATION; CONVERSION OR DISTRIBUTION OF ELECTRIC POWER
- H02M—APPARATUS FOR CONVERSION BETWEEN AC AND AC, BETWEEN AC AND DC, OR BETWEEN DC AND DC, AND FOR USE WITH MAINS OR SIMILAR POWER SUPPLY SYSTEMS; CONVERSION OF DC OR AC INPUT POWER INTO SURGE OUTPUT POWER; CONTROL OR REGULATION THEREOF
- H02M1/00—Details of apparatus for conversion
- H02M1/0003—Details of control, feedback or regulation circuits
- H02M1/0025—Arrangements for modifying reference values, feedback values or error values in the control loop of a converter
Definitions
- the present invention relates to a DC-DC converter that converts a DC voltage and a control circuit thereof, and more particularly, to a technology that is effective when applied to a step-up / step-down DC-DC converter that can output by stepping up or down an input voltage.
- step-up / step-down DC-DC converter that can output a voltage by stepping up or stepping down the input voltage as a DC-DC converter that converts a varying direct-current voltage into a direct-current voltage having a predetermined potential as an input voltage.
- examples of inventions related to such a step-up / step-down DC-DC converter include those described in Patent Document 1 and Patent Document 2, for example.
- FIG. 6 shows a configuration of the step-up / step-down DC-DC converter disclosed in Patent Document 2.
- This step-up / step-down DC-DC converter includes nMOS transistors Q3 and Q4 connected in series between an input terminal to which a DC voltage Vin supplied from a DC power source such as a battery is applied and a ground point, and a smoothing capacitor C2.
- nMOS transistors Q1 and Q2 connected in series between the connected output terminal and the ground, bleeder resistors R1 and R2 that divide the output voltage Vout to generate the feedback voltage FB, and the feedback voltage FB
- An error amplifier AMP1 that outputs a voltage VA corresponding to the potential difference from the voltage Vref
- an inverting amplifier AMP2 that inverts the output VA of the error amplifier
- a triangular wave VTRI that is used to control the output voltage by PWM (pulse width modulation).
- Generated triangular wave generation circuit TWG generated triangular wave VTRI and output VA of error amplifier AMP1 or its inverted voltage
- a pair of PWM comparator CMP1, CMP2 which receives the B.
- An inductor (coil) L is connected between the connection node N1 of the nMOS transistors Q1 and Q2 and the connection node N2 of the nMOS transistors Q3 and Q4.
- Q4 is driven on and off by the output (PWM pulse) of CMP2.
- the nMOS transistor Q1 is driven on and off by the inverted signal of the output of the PWM comparator CMP1
- Q3 is driven by the inverted signal of the output of the CMP2.
- step-up / step-down DC-DC converter shown in FIG. 6, as shown in FIG. 7, when the input voltage Vin is lower than the target output voltage, that is, when the feedback voltage VA is higher than the peak voltage Vp of the triangular wave VTRI. , Q3 is continuously on, Q4 is continuously off, and Q1 and Q2 are driven with PWM pulses to output a voltage Vout obtained by boosting Vin.
- the input voltage Vin is higher than the target output voltage, that is, when the voltage VB obtained by inverting the feedback voltage VA with respect to Vref is higher than the peak voltage Vp of the triangular wave
- Q1 is continuously turned on and Q2 is continuously turned off.
- Q3 and Q4 are driven by PWM pulses, and a voltage Vout obtained by stepping down Vin is output.
- the triangular wave generating circuit TWG that generates a triangular wave has an upper limit voltage V1 that defines the upper peak value of the triangular wave and a lower limit value that defines the lower peak value of the triangular wave.
- the triangular wave generating circuit TWG is configured to generate the triangular wave VTRI using the upper limit voltage V1 and the lower limit voltage V2.
- Such a triangular wave generation circuit TWG includes, for example, a charge / discharge circuit having a constant current source and a capacitor, and a comparator that generates charge / discharge switching timing using the upper limit voltage V1 and the lower limit voltage V2 as comparison voltages. Can do.
- the reference voltage Vref in the inverting amplifier AMP2 is set lower than the peak value Vp of the triangular wave VTRI. Yes.
- the upper limit voltage V1 supplied to the triangular wave generating circuit is supplied as it is as the reference voltage in the inverting amplifier.
- a voltage FB2 obtained by inverting the feedback voltage FB1 with respect to the voltage V1 is generated from the inverting amplifier as shown in FIG. 8A, for example. It is configured to be supplied to the PWM comparator on the boost side.
- the upper limit voltage V1 that defines the upper peak value of the triangular wave is supplied as it is as the reference voltage in the inverting amplifier as described above, due to delays or the like generated in the comparator constituting the triangular wave generating circuit, The peak value of the triangular wave is higher than the upper limit voltage V1.
- the error amplifier (AMP1) or The reference voltage of the inverting amplifier (AMP2) becomes a triangular wave due to manufacturing variations in gain of the inverting amplifier (AMP2), offsets of the amplifiers (AMP1, AMP2) and comparators (CMP1, CMP2), and variations in bleeder resistance (R1, R2).
- a pulse for turning on the transistor (Q2) is output at a timing when it is not necessary to turn on the boosting transistor (Q2).
- the overlap period Ts occurs and switching loss increases. It was found.
- the present invention has been made paying attention to the problems as described above.
- the object of the present invention is to provide a circuit for generating a triangular wave for PWM control of the output voltage, a PWM comparator, and an inverting amplifier for inverting the feedback voltage.
- a PWM comparator for PWM control of the output voltage
- an inverting amplifier for inverting the feedback voltage.
- it is possible to reduce the switching loss in the transition period of switching of the step-up / step-down operation and improve the power efficiency.
- a switching control circuit that generates and outputs an off / on signal of a first switching element for flowing current into a voltage conversion inductor of a step-up / step-down DC-DC converter and a second switching element for drawing current from the inductor There,
- An error amplification circuit that outputs a voltage corresponding to the output voltage of the DC-DC converter;
- An inverting amplifier circuit for inverting the output of the error amplifier circuit with reference to a predetermined voltage;
- a waveform generation circuit for generating a triangular wave;
- a first voltage comparison circuit that receives the output of the error amplification circuit and the output of the waveform generation circuit;
- a second voltage comparison circuit that receives the output of the inverting amplification circuit and the output of the waveform generation circuit;
- a voltage generation circuit for generating an inversion reference voltage to be supplied to the inversion amplifier circuit; With The inverted reference voltage supplied to the inverting amplifier circuit is configured not to be lower than the highest potential of the triangular wave supplied to the first
- the reference voltage of the inverting amplifier circuit does not become lower than the peak value of the triangular wave supplied to the voltage comparison circuit.
- the switching element that controls the current is prevented from being turned on / off, and the switching loss can be reduced to improve the power efficiency.
- the inversion reference voltage generated by the voltage generation circuit is set to a potential higher than a peak value of a triangular wave generated by the waveform generation circuit, and the inversion reference voltage and the peak are set.
- the potential difference from the value is set based on the gain variation of the operational amplifiers constituting the error amplification circuit and the inverting amplification circuit, the offset of the operational amplifier, and the offsets of the first voltage comparison circuit and the second voltage comparison circuit. Configure as follows.
- the potential difference between the reference voltage and the peak value of the triangular wave is set, so even if the gain of the amplifier varies or the amplifier or comparator has an offset, the inverted reference voltage is higher than the peak value of the triangular wave.
- the switching loss during the transition period of switching of the step-up / step-down operation can be reduced.
- the inversion reference voltage generated by the voltage generation circuit has a feedback voltage fluctuation caused by at least a gain variation of an operational amplifier constituting the error amplification circuit, rather than a peak value of a triangular wave generated by the waveform generation circuit.
- You may comprise so that it may be set to the electric potential higher than a minute.
- the reference voltage of the inverting amplifier circuit is set to a potential higher than the fluctuation amount of the feedback voltage caused by the variation in the gain of the operational amplifier that constitutes the error amplifier circuit, which is the biggest cause of the lowering of the triangular wave peak value. Therefore, it is possible to set a condition for avoiding the inversion reference voltage from becoming lower than the peak value of the triangular wave relatively easily.
- the inverted reference voltage and the peak value are The potential difference is set in consideration of the variation of the bleeder resistance constituting the voltage dividing circuit.
- the voltage generation circuit for generating the inversion reference voltage includes a resistance component in which a plurality of resistors are connected in series between a constant voltage terminal to which a constant voltage is applied and a ground terminal to which a ground potential is applied.
- a first voltage extracted from a first node of the resistor voltage divider circuit is supplied to the waveform generation circuit as a voltage defining a peak value of the triangular wave, and a second node of the resistor voltage divider circuit
- the second voltage higher than the first voltage extracted from the first voltage is supplied to the inverting amplifier circuit as the inverting reference voltage.
- the voltage generation circuit is responsive to a variable voltage source capable of changing a generated voltage, a peak value detection circuit for detecting a peak value of a triangular wave generated by the waveform generation circuit, and an output of the peak value detection circuit And a voltage control circuit for controlling the inversion reference voltage generated by the variable voltage source.
- a voltage clamp circuit that clamps the peak value of the triangular wave supplied from the waveform generation circuit to the first and second voltage comparison circuits to a potential lower than the inversion reference voltage may be provided.
- the reference voltage of the inverting amplifier circuit does not become lower than the peak value of the chopping wave supplied to the voltage comparison circuit. In this case, the switching element is prevented from being turned on / off, and the switching loss can be reduced to improve the power efficiency.
- the voltage conversion inductor, the first switching element for flowing current into the inductor, the second switching element for drawing current from the inductor, and the first switching element being off A third switching element for flowing a current to the inductor during a current period, and a fourth switching element for flowing a current from the inductor to an output terminal while the second switching element is off
- a switching control circuit having the above-described configuration for generating a signal for controlling on / off of the first to fourth switching elements constitutes a step-up / step-down DC-DC converter.
- a step-up / step-down DC-DC converter including a circuit for generating a triangular wave for PWM control of an output voltage, a PWM comparator, and an inverting amplifier for inverting the feedback voltage
- the gain of the amplifier constituting the switching control circuit Even if the bleeder resistance varies or the amplifier or comparator has an offset, the switching loss during the transition period of switching of the buck-boost operation can be increased by making the reference voltage of the inverting amplifier higher than the peak value of the triangular wave. There is an effect that the power efficiency can be improved by reducing.
- FIG. 1 is a circuit configuration diagram showing an embodiment of a step-up / step-down DC-DC converter to which the present invention is applied.
- FIG. 2 is a circuit configuration diagram illustrating a configuration example of a voltage generation circuit in the switching control circuit of the embodiment of FIG. 1. It is explanatory drawing which shows the relationship between the voltage produced
- FIG. 2 is a waveform diagram showing operation waveforms of the DC-DC converter of FIG. 1.
- FIG. 3 is a circuit diagram showing a second embodiment of a step-up / step-down DC-DC converter to which the present invention is applied.
- FIG. 6 is a circuit configuration diagram showing a configuration example of a conventional buck-boost DC-DC converter (Patent Document 2). It is a wave form diagram which shows the mode of the change of the signal of each part and the electric potential in the conventional buck-boost DC-DC converter. It is a wave form diagram which shows the mode of the change of the signal of each part and electric potential in the conventional buck-boost DC-DC converter.
- FIG. 1 shows an embodiment of a step-up / step-down DC-DC converter to which the present invention is applied.
- the step-up / step-down DC-DC converter of this embodiment is a MOS transistor (insulated gate type) connected in series between an input terminal IN to which a DC voltage Vin supplied from a DC power source 10 such as a battery is applied and a ground point.
- Field effect transistors) Q3, Q4, MOS transistors Q1, Q2 connected in series between the output terminal OUT to which the smoothing capacitor C2 is connected and the ground point, and the transistors Q1-Q4 are turned on and off.
- a switching control circuit 20 that outputs a signal.
- An inductor (coil) L is connected between a connection node N1 of the MOS transistors Q3 and Q4 and a connection node N2 of the MOS transistors Q1 and Q2.
- p-channel MOS transistors are used as the transistors Q1 and Q3
- n-channel MOS transistors are used as the transistors Q2 and Q4.
- RL indicates a load connected to the output terminal as an equivalent resistance
- C1 and C2 are smoothing capacitors.
- the switching control circuit 20 divides the output voltage Vout to generate a feedback voltage FB, bleeder resistors R1 and R2, an error amplification circuit 21 that outputs a voltage corresponding to the potential difference between the feedback voltage FB and the reference voltage Vref,
- An inverting amplifier circuit 22 for inverting the output of the error amplifier circuit 21, a waveform generation circuit 23 for generating a sawtooth waveform signal RAMP as a triangular wave used for PWM (pulse width modulation) control, and the waveform generation circuit 23
- the voltage generation circuit 24 for generating the upper limit voltage V1 and the lower limit voltage V2 of the waveform signal RAMP generated in Step 1, the waveform signal RAMP from the waveform generation circuit 23, and the output voltage FB1 of the error amplification circuit 21 are input.
- the second comparator 2 that receives the comparator 25, the waveform signal RAMP, and the output voltage FB2 of the inverting amplifier circuit 22 as inputs. Provided with a door.
- MOS transistors Q1 and Q2 are turned on and off by inverters INV1 and INV2 that invert the output of the second comparator 26, and Q3 and Q4 are turned on and off by buffer drivers BFF1 and BFF2 that output signals in phase with the output of the first comparator 25, respectively. Driven. A constant voltage V0 that is higher than the voltage V1 generated by the voltage generation circuit 24 by ⁇ V is supplied to the inverting amplifier circuit 22 as an inverting reference voltage.
- the output of the second comparator 26 is continuously at a low level, the transistor Q1 is continuously on, Q2 is continuously off, and the PWM pulse is output from the first comparator 25. Then, the transistors Q3 and Q4 are complementarily turned on and off. As a result, a voltage Vout obtained by stepping down the input voltage Vin is output.
- Vin approaches Vout in the boosting operation the output FB2 of the inverting amplifier circuit 22 increases, and the duty of the control pulse becomes 100% (Q1 is always on) when Vin ⁇ Vout. As Vin approaches Vout and Vin> Vout, the Q1 changes from 100% ON to Q3 99% ON.
- FIG. 2A shows a specific circuit example of the voltage generation circuit 24.
- the voltage generation circuit 24 is constituted by a constant voltage circuit CVG and a resistance voltage dividing circuit composed of series resistors R11, R12, R13, and R14 for the constant voltage Vc generated by the constant voltage circuit CVG.
- the highest reference voltage V0 is extracted from the connection node N11 between the resistors R11 and R12
- the upper limit voltage V1 of the waveform signal RAMP is extracted from the connection node N12 between the resistors R12 and R13
- the resistors R13 and R14 are connected.
- the lower limit voltage V2 of the waveform signal RAMP is extracted from the node N13.
- the reference voltage V0 is always higher than the upper limit voltage V1 of the waveform signal RAMP.
- the potential difference ⁇ V between the reference voltage V0 and the upper limit voltage V1 is set to a desired value by appropriately setting the values of the resistors R11 to R14. ⁇ V is also the case where the manufacturing variations of the elements constituting the circuit overlap and the reference voltage V0 is in a state where it approaches the peak value Vpeak1 (V1) of the actual waveform signal (hereinafter referred to as a triangular wave) RAMP. , It is desirable that the relationship V0> Vpeak1 is maintained.
- the lower limit voltage V2 may be a ground potential (0V).
- FIG. 3 shows operation waveforms of the DC-DC converter of FIG.
- the reference voltage V0 of the inverting amplifier circuit 22 is always higher than the upper limit voltage V1 of the waveform signal RAMP by ⁇ V, so that the input voltage Vin is increased during the boosting operation and boosted.
- Ts for simultaneously turning on and off the step-up transistors Q1, Q2 and step-down transistors Q3, Q4, and the p-channel MOS transistors Q1, Q1
- a switching stop period Tc occurs in which Q3 is continuously on and n-channel MOS transistors Q2 and Q4 are continuously off.
- the switching loss in the transition period of the step-up / step-down switching can be reduced, and the power efficiency is improved.
- parameters to be considered when determining the reference voltage V0 to be supplied to the inverting amplifier circuit 22 are the amplifier AMP1 that constitutes the error amplifier circuit 21 and the inverting amplifier circuit 22 , 2 DC gains A1, A2, amplifiers AMP1, 2 and offsets Voff1, 2, 3, and 4 of comparators 25, 26, resistance values of bleeder resistors R1, R2, and the like.
- ⁇ V ( ⁇ Vout ⁇ R2 / (R1 + R2)) / A1 (1) It is.
- ⁇ Vout in the above formula (1) is the value when the transistors Q1 and Q3 are on and Q2 and Q4 are off.
- Vout ⁇ Vin and the regulation is deteriorated.
- the output voltage range or output voltage accuracy
- Vout2 (Vref1 ⁇ (2 ⁇ V0 ⁇ Vpeak1) / A1) ⁇ (R1 + R2) / R2 Is obtained.
- Vout1 and Vout2 the difference between Vout1 and Vout2 is the voltage fluctuation value when the step-down operation and the step-up operation are stopped.
- V0 Vpeak1 + ⁇ V
- ⁇ Vout ⁇ V ⁇ 2 (R1 + R2) / A1 ⁇ R2 Is obtained.
- Vout target output voltage value
- the output voltage must be within X% of the target value (2% or 5% as an example), including all the variation factors. Don't be.
- This X% includes, for example, factors such as gain variations of the amplifiers AMP1 and AMP2, offsets of the amplifiers and comparators, variations of the resistors R1 and R2, and variations of the reference voltage Vref.
- the accuracy of the output voltage is the boost operation. It is a value obtained by adding the accuracy of each operation at the time of time + step-down operation + step-up / step-down stop.
- the boosting operation is performed. Designed to satisfy each output error by allocating errors such as “40” for time, “40” for step-down operation, and “20” for step-down / step-down operation. It is necessary to have voltage accuracy.
- step-up / step-down is stopped.
- the error distribution at the time of step-up operation, step-down operation, and step-down / step-down can be changed by various methods. , “45”, “10”, or “33”, “33”, “33”, etc., there is no problem as long as it is within the total accuracy. Needless to say, the values of the output voltage Vout, amplifier gain A1, resistors R1 and R2, and the like vary depending on the system to be implemented.
- FIG. 4 shows a second embodiment of the step-up / step-down DC-DC converter using the switching control circuit 20 that always generates a voltage higher than the upper limit voltage V1 of the waveform signal RAMP as the reference voltage V0 of the inverting amplifier circuit 22. It is shown.
- FIG. 5 shows a third embodiment of the switching control circuit 20.
- the reference voltage V0 of the inverting amplifier circuit 22 is prevented from becoming lower than the peak of the triangular wave RAMP.
- a clamp circuit 29 that clamps the peak of the triangular wave RAMP supplied to the comparators 25 and 26 so as not to be higher than the reference voltage V0 supplied to the inverting amplifier circuit 22 is provided.
- the clamp circuit 29 includes, for example, an operational amplifier AMP3 in which a constant voltage V1 ( ⁇ V0) is applied to an inverting input terminal, and a triangular wave RAMP generated by a triangular wave generation circuit (waveform signal generation circuit) 23 is input to a non-inverting input terminal;
- the pMOS transistor Q5 is connected between the power supply voltage terminal VDD and a signal line that transmits the triangular wave RAMP, and the output of the operational amplifier AMP3 is applied to the gate terminal.
- the operational amplifier AMP3 controls the transistor Q5 so that the peak of the triangular wave RAMP does not exceed the constant voltage V1. Clamp.
- a switching stop period Tc occurs, so that switching loss in the transition period of switching of the step-up / step-down can be reduced, and power efficiency is improved.
- FIG. 5 shows a case where the voltage applied to the inverting input terminal of the operational amplifier AMP3 and the upper limit voltage supplied to the triangular wave generation circuit 23 are the same (V1), but V1 ⁇ V1 ′ ⁇ A voltage V1 ′ such as V0 may be applied to the inverting input terminal of the operational amplifier AMP3.
- the present invention is not limited to the embodiment.
- the p-channel MOS transistors are used as the switching elements Q1 and Q3 in the DC-DC converter of the above embodiment
- n-channel MOS transistors may be used.
- the buffer driver BFF1 in FIG. 1 may be replaced with an inverter
- the inverter INV1 may be replaced with a buffer driver.
- a DC-DC converter can be configured using a rectifying diode instead of the MOS transistors Q2 and Q3 as switching elements in FIG.
- the sawtooth wave is used as the triangular wave supplied to the PWM comparator (25, 26), but a narrowly defined triangular wave having a rising slope and a falling slope (see FIG. 8 (A)) may be used.
- the constant voltage circuit CVG is provided as the voltage generation circuit 24.
- the constant voltage Vc divided by the resistance voltage dividing circuits (R11 to R14) is supplied from the outside of the semiconductor integrated circuit. You may comprise so that it may give.
- the present invention is not limited thereto, and includes a waveform generation circuit that generates a triangular wave for PWM.
- the present invention can be widely used for DC-DC converters that require a voltage corresponding to the peak value of the triangular wave.
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Abstract
Description
昇降圧DC-DCコンバータの電圧変換用のインダクタに電流を流し込むための第1のスイッチング素子とインダクタから電流を引くための第2のスイッチング素子のオフ、オン信号を生成し出力するスイッチング制御回路であって、
DC-DCコンバータの出力電圧に応じた電圧を出力する誤差増幅回路と、
前記誤差増幅回路の出力を所定の電圧を基準にして反転する反転増幅回路と、
三角波を生成する波形生成回路と、
前記誤差増幅回路の出力と前記波形生成回路の出力とを入力とする第1の電圧比較回路と、
前記反転増幅回路の出力と前記波形生成回路の出力とを入力とする第2の電圧比較回路と、
前記反転増幅回路に供給される反転基準電圧を生成する電圧生成回路と、
を備え、
前記反転増幅回路に供給される前記反転基準電圧が、前記第1および第2の電圧比較回路に供給される三角波の最も高い電位よりも低い電位にならないように構成したものである。
なお、上記昇圧動作でVinがVoutに近づいてくると、反転増幅回路22の出力FB2が上昇し、Vin≒Voutで制御パルスのデューティが100%(Q1が常にオン)になる。さらにVinがVoutに近づいて、Vin>Voutの関係になると、Q1の100%オンから、Q3の99%オンに変わって行く。
ΔV=(ΔVout×R2/(R1+R2))/A1 ……(1)
である。
Va1=Vpeak1 ・・・条件1
が成立する。この時のVoutをVout1とすると、上記条件1より、
Vpeak1=(Vref1-Vout1×R2/(R1+R2))×A1
が導かれる。この式を変形することで、
Vout1=(Vref1-Vpeak1/A1)×(R1+R2)/R2
が得られる。
Va2=Vpeak1 ・・・条件2
が成立する。この時、Va2=2×V0-Va1であるので、
Vpeak1=2×V0-Va1
が得られる。これを変形すると、
Va1=2×V0-Vpeak1 ……(2)
となる。また、Va1とVoutの関係は、
Va1=(Vref1-Vout×R2/(R1+R2))×A1
であるので、式(2)より、
2×V0-Vpeak1=(Vref1-Vout×R2/(R1+R2))×A1
が得られる。この時(条件2)の出力VoutをVout2とすると、
Va1=2×V0-Vpeak1
=(Vref1-Vout2×R2/(R1+R2))×A1
Vout2=(Vref1-(2×V0-Vpeak1)/A1)×(R1+R2)/R2
が得られる。
ΔVout=Vout1-Vout2
=(Vref1-Vpeak1/A1)×(R1+R2)/R2
-(Vref1-(2×V0-Vpeak1)/A1)×(R1+R2)/R2
=(-Vpeak1+(2×V0-Vpeak1))×(R1+R2)/A1・R2
=(V0-Vpeak1)×2(R1+R2)/A1・R2
となる。ここで、V0=Vpeak1+ΔVであるので、
ΔVout=ΔV×2(R1+R2)/A1・R2
が得られる。
ΔVout=(Vout×X/100)×(20/100)
=ΔV×2(R1+R2)/A1・R2
を満たすようにΔVを設定すれば良い。従って、例えば出力3.3Vで規格値2%とすると、トータルバラツキは3.3×0.02=66mVであるので、
ΔVout=66×20/100=13.2[mV]
となり、ΔV×2(R1+R2)/A1・R2=13.2が得られる。ここで、仮に、R1=R2、A1=100倍とした場合には、
ΔV=0.33[V]
となる。
21 誤差増幅回路
22 反転増幅回路
23 波形生成回路(三角波発生回路)
24 電圧生成回路
25 第1コンパレータ(第1の電圧比較回路)
26 第2コンパレータ(第2の電圧比較回路)
27 ピーク値検出回路
28 電圧制御回路
29 クランプ回路
L コイル(インダクタ)
Q1~Q4 スイッチング素子
AMP1 誤差増幅回路のアンプ
AMP2 反転増幅回路のアンプ
Claims (8)
- 昇降圧DC-DCコンバータの電圧変換用のインダクタに電流を流し込むための第1のスイッチング素子とインダクタから電流を引くための第2のスイッチング素子のオフ、オン信号を生成し出力するスイッチング制御回路であって、
DC-DCコンバータの出力電圧に応じた電圧を出力する誤差増幅回路と、
前記誤差増幅回路の出力を所定の電圧を基準にして反転する反転増幅回路と、
三角波を生成する波形生成回路と、
前記誤差増幅回路の出力と前記波形生成回路の出力とを入力とする第1の電圧比較回路と、
前記反転増幅回路の出力と前記波形生成回路の出力とを入力とする第2の電圧比較回路と、
前記反転増幅回路に供給される反転基準電圧を生成する電圧生成回路と、
を備え、
前記反転増幅回路に供給される前記反転基準電圧が、前記第1および第2の電圧比較回路に供給される三角波の最も高い電位よりも低い電位にならないように構成されていることを特徴とするスイッチング制御回路。 - 前記電圧生成回路により生成される前記反転基準電圧が、前記波形生成回路により生成される三角波のピーク値よりも高い電位となるように設定され、前記反転基準電圧と前記ピーク値との電位差は、前記誤差増幅回路および前記反転増幅回路を構成するオペアンプのゲインのばらつき、前記オペアンプのオフセット、および第1の電圧比較回路および第2の電圧比較回路のオフセットに基づいて設定されることを特徴とする請求項1に記載のスイッチング制御回路。
- 前記電圧生成回路により生成される前記反転基準電圧は、前記波形生成回路により生成される三角波のピーク値よりも、少なくとも前記誤差増幅回路を構成するオペアンプのゲインのばらつきによって生じるフィードバック電圧の変動分よりも高い電位に設定されることを特徴とする請求項1に記載のスイッチング制御回路。
- DC-DCコンバータの出力電圧を分圧して前記誤差増幅回路に供給するフィードバック電圧を生成するブリーダ抵抗からなる分圧回路を備える場合に、前記反転基準電圧と前記ピーク値との電位差は、前記分圧回路を構成するブリーダ抵抗のばらつきも考慮して設定されることを特徴とする請求項2または3に記載のスイッチング制御回路。
- 前記反転基準電圧を発生する電圧生成回路は、定電圧が印加される定電圧端子と接地電位が印加される接地端子との間に複数の抵抗が直列に接続された抵抗分圧回路からなり、
前記抵抗分圧回路の第1ノードから取り出された第1の電圧が前記波形生成回路へ前記三角波のピーク値を規定する電圧として供給され、前記抵抗分圧回路の第2ノードから取り出された前記第1の電圧よりも高い第2の電圧が、前記反転基準電圧として前記反転増幅回路に供給されることを特徴とする請求項1~4のいずれかに記載のスイッチング制御回路。 - 前記電圧生成回路は、
発生する電圧を変更可能な可変電圧源と、
前記波形生成回路により生成される三角波のピーク値を検出するピーク値検出回路と、
前記ピーク値検出回路の出力に応じて前記可変電圧源が発生する前記反転基準電圧を制御する電圧制御回路と、
を備えることを特徴とする請求項1~4のいずれかに記載のスイッチング制御回路。 - 前記波形生成回路より前記第1および第2の電圧比較回路に供給される三角波のピーク値を前記反転基準電圧よりも低い電位にクランプする電圧クランプ回路を備えることを特徴とする請求項1に記載のスイッチング制御回路。
- 電圧変換用のインダクタと、該インダクタに電流を流し込むための第1のスイッチング素子と、前記インダクタから電流を引くための第2のスイッチング素子と、前記第1のスイッチング素子がオフされている期間に前記インダクタへ電流を流すための第3のスイッチング素子と、前記第2のスイッチング素子がオフされている期間に前記インダクタからの電流を出力端子へ流すための第4のスイッチング素子と、前記第1~第4のスイッチング素子をオン、オフ制御する信号を生成する請求項1~6のいずれかに記載のスイッチング制御回路と、を備えることを特徴とする昇降圧DC-DCコンバータ。
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Families Citing this family (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP5493916B2 (ja) * | 2010-01-28 | 2014-05-14 | ミツミ電機株式会社 | 昇降圧dc−dcコンバータおよびスイッチング制御回路 |
US8841895B2 (en) * | 2012-06-04 | 2014-09-23 | Texas Instruments Deutschland Gmbh | Electronic device for average current mode DC-DC conversion |
JP5802638B2 (ja) * | 2012-09-21 | 2015-10-28 | 株式会社東芝 | 昇降圧型電源回路 |
US9395738B2 (en) | 2013-01-28 | 2016-07-19 | Nvidia Corporation | Current-parking switching regulator with a split inductor |
US9800158B2 (en) | 2013-01-30 | 2017-10-24 | Nvidia Corporation | Current-parking switching regulator downstream controller |
US9804621B2 (en) * | 2013-02-05 | 2017-10-31 | Nvidia Corporation | Current-parking switching regulator downstream controller pre-driver |
US9459635B2 (en) | 2013-02-08 | 2016-10-04 | Nvidia Corporation | Current-parking switching regulator upstream controller |
US9389617B2 (en) | 2013-02-19 | 2016-07-12 | Nvidia Corporation | Pulsed current sensing |
US9639102B2 (en) | 2013-02-19 | 2017-05-02 | Nvidia Corporation | Predictive current sensing |
JP6257363B2 (ja) * | 2014-02-06 | 2018-01-10 | エスアイアイ・セミコンダクタ株式会社 | スイッチングレギュレータ制御回路及びスイッチングレギュレータ |
US9614428B2 (en) * | 2014-04-16 | 2017-04-04 | Allegro Microsystems, Llc | Switching regulator circuit allowing a lower input voltage |
AT517437B1 (de) | 2015-06-17 | 2018-06-15 | Omicron Electronics Gmbh | Prüfvorrichtung und Verfahren zum Betreiben einer Prüfvorrichtung |
CN105471264B (zh) * | 2015-12-24 | 2018-05-29 | 矽力杰半导体技术(杭州)有限公司 | 用于四开关升降压变换器的控制电路和控制方法 |
IT201600080294A1 (it) * | 2016-07-29 | 2018-01-29 | St Microelectronics Srl | Dispositivo e metodo di controllo ad anello chiuso di un convertitore di potenza |
US10511223B2 (en) | 2016-12-09 | 2019-12-17 | Allegro Microsystems, Llc | Voltage regulator having boost and charge pump functionality |
CN108023468A (zh) * | 2017-12-28 | 2018-05-11 | 杰华特微电子(杭州)有限公司 | 开关电源控制电路及开关电源 |
CN111082657A (zh) * | 2018-10-18 | 2020-04-28 | 圣邦微电子(北京)股份有限公司 | 降压-升压变换器和控制方法 |
US11418118B1 (en) * | 2019-02-08 | 2022-08-16 | Renesas Electronics America Inc. | Regulation loop control for voltage regulation in a switch mode power supply |
JP7381397B2 (ja) | 2020-04-28 | 2023-11-15 | ローム株式会社 | 電源装置 |
US11594969B2 (en) | 2020-12-30 | 2023-02-28 | Astec International Limited | Non-inverting buck-boost converter |
CN113422512B (zh) * | 2021-06-11 | 2024-05-07 | 拓尔微电子股份有限公司 | 一种四开关控制电路 |
CN113783170A (zh) * | 2021-09-13 | 2021-12-10 | 成都新欣神风电子科技有限公司 | 一种高可靠性浪涌电压抑制方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03135107A (ja) * | 1989-10-19 | 1991-06-10 | Mitsubishi Electric Corp | 三角波発生器 |
JP2004320892A (ja) * | 2003-04-16 | 2004-11-11 | Rohm Co Ltd | 電源装置 |
JP2008131746A (ja) * | 2006-11-21 | 2008-06-05 | Ricoh Co Ltd | 昇降圧型スイッチングレギュレータ |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH05161029A (ja) | 1991-12-03 | 1993-06-25 | Mitsubishi Electric Corp | 水平位相調整回路 |
US5402060A (en) | 1993-05-13 | 1995-03-28 | Toko America, Inc. | Controller for two-switch buck-boost converter |
JP3223844B2 (ja) * | 1997-06-27 | 2001-10-29 | 日本電気株式会社 | 基準電圧発生装置 |
JP3718830B2 (ja) | 2001-02-26 | 2005-11-24 | 株式会社日立製作所 | 電力変換装置 |
JP3953443B2 (ja) | 2003-07-08 | 2007-08-08 | ローム株式会社 | 昇降圧dc−dcコンバータ及びこれを用いたポータブル機器 |
US7180274B2 (en) | 2004-12-10 | 2007-02-20 | Aimtron Technology Corp. | Switching voltage regulator operating without a discontinuous mode |
JP2007097361A (ja) * | 2005-09-30 | 2007-04-12 | Matsushita Electric Ind Co Ltd | 昇降圧コンバータ |
JP2007151340A (ja) * | 2005-11-29 | 2007-06-14 | Ricoh Co Ltd | 昇降圧型スイッチングレギュレータ |
US7570033B1 (en) * | 2006-04-03 | 2009-08-04 | National Semiconductor Corporation | Apparatus and method for PWM buck-or-boost converter with smooth transition between modes |
US7518349B2 (en) * | 2006-05-31 | 2009-04-14 | Intersil Americas Inc. | Current multiplier/divider-configured feed-forward compensation for buck-mode converter controller with programmed switching frequency |
US7737668B2 (en) * | 2007-09-07 | 2010-06-15 | Panasonic Corporation | Buck-boost switching regulator |
US20090102440A1 (en) * | 2007-10-23 | 2009-04-23 | Advanced Analogic Technologies, Inc. | Buck-Boost Switching Voltage Regulator |
JP2009124877A (ja) | 2007-11-15 | 2009-06-04 | Asahi Kasei Electronics Co Ltd | 電源出力制御装置 |
JP5399734B2 (ja) | 2008-09-30 | 2014-01-29 | スパンション エルエルシー | 出力電圧制御装置、出力電圧制御方法および電子機器 |
JP5493916B2 (ja) | 2010-01-28 | 2014-05-14 | ミツミ電機株式会社 | 昇降圧dc−dcコンバータおよびスイッチング制御回路 |
-
2010
- 2010-01-28 JP JP2010016115A patent/JP5625369B2/ja active Active
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2011
- 2011-01-17 CN CN201180007667.9A patent/CN102742135B/zh active Active
- 2011-01-17 WO PCT/JP2011/050627 patent/WO2011093155A1/ja active Application Filing
- 2011-01-17 US US13/575,713 patent/US9048729B2/en active Active
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH03135107A (ja) * | 1989-10-19 | 1991-06-10 | Mitsubishi Electric Corp | 三角波発生器 |
JP2004320892A (ja) * | 2003-04-16 | 2004-11-11 | Rohm Co Ltd | 電源装置 |
JP2008131746A (ja) * | 2006-11-21 | 2008-06-05 | Ricoh Co Ltd | 昇降圧型スイッチングレギュレータ |
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