WO2011086628A1 - 貼り合わせウェーハの製造方法 - Google Patents
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- WO2011086628A1 WO2011086628A1 PCT/JP2010/006754 JP2010006754W WO2011086628A1 WO 2011086628 A1 WO2011086628 A1 WO 2011086628A1 JP 2010006754 W JP2010006754 W JP 2010006754W WO 2011086628 A1 WO2011086628 A1 WO 2011086628A1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
- H01L21/3247—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering for altering the shape, e.g. smoothing the surface
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
- H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/3065—Plasma etching; Reactive-ion etching
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/324—Thermal treatment for modifying the properties of semiconductor bodies, e.g. annealing, sintering
Definitions
- the present invention relates to a method for manufacturing a bonded wafer using an ion implantation separation method.
- one wafer is made into a thin film by grinding / polishing and ion implantation separation method (also called Smart Cut (registered trademark) method). Is generally known.
- the grinding / polishing method is, for example, bonding two silicon wafers directly or through an oxide film without using an adhesive, and increasing the bond strength by heat treatment (1000 to 1200 ° C.). Later, one of the wafers is ground and polished to form a thin film.
- the advantage of this method is that the SOI layer crystallinity and the reliability of the buried oxide film are equivalent to those of ordinary silicon wafers.
- the disadvantages are that the film thickness uniformity of the SOI layer is limited (at most ⁇ 0.3 ⁇ m), and the cost is high because two silicon wafers are used to manufacture one SOI wafer. .
- the ion implantation separation method specifically, for example, at least one kind of gas ions of hydrogen ions and rare gas ions is ion-implanted into one main surface (bond wafer) of at least one of two silicon wafers.
- the ion implantation layer peeling layer
- the ion implanted surface and the main surface of the other silicon wafer base wafer
- This ion implantation delamination method has, for example, an advantage that a thin film SOI wafer having a SOI layer thickness uniformity of ⁇ 10 nm or less can be easily manufactured, and an advantage that the peeled bond wafer can be reused multiple times to reduce costs.
- a thin film SOI wafer having a SOI layer thickness uniformity of ⁇ 10 nm or less can be easily manufactured, and an advantage that the peeled bond wafer can be reused multiple times to reduce costs.
- the surface of the SOI wafer immediately after peeling has poor roughness, it cannot be used as it is as a substrate for device fabrication, and an additional process for planarization is required.
- planarization treatment planarization by CMP (Chemical Mechanical Polishing), planarization by high-temperature heat treatment in an inert gas atmosphere, or planarization by heat treatment in a hydrogen or hydrogen chloride gas atmosphere is generally known. From the viewpoint of cost reduction, a flattening heat treatment method in a hydrogen or hydrogen chloride atmosphere is considered the most advantageous method (Patent Document 1).
- a bonded wafer is manufactured by an ion implantation separation method using a silicon single crystal wafer, as shown in FIG.
- the bond wafer 11 is peeled off by the ion implantation layer 12 to thereby remove the base wafer.
- a bonded wafer 16 having a silicon thin film (SOI layer) 15 on 13 is fabricated (FIG. 2B).
- the bonded wafer 16 after peeling is heat treated in an atmosphere containing hydrogen or hydrogen chloride (hereinafter referred to as gas) using a single wafer epitaxial layer growth reactor or the like. Etching) is performed (FIG. 2C).
- this method is a method of flattening while etching the SOI layer, and the film thickness of the SOI layer has a problem that the wafer peripheral portion is thin and the central portion is thick and poorly distributed.
- the film thickness uniformity of the thin film (SOI layer) is poor, the device characteristics vary. Therefore, it is required to improve the film thickness uniformity of the bonded wafer.
- the present invention has been made in view of the above circumstances, and a thin film excellent in film thickness uniformity even when a heat treatment for flattening a thin film surface of a bonded wafer after peeling is performed in an ion implantation peeling method. It aims at providing the manufacturing method of the bonded wafer which can obtain the bonded wafer which has this.
- an ion implantation layer is formed by ion implantation of at least one kind of gas ions of hydrogen ions and rare gas ions from the surface of a bond wafer, and the ion implantation of the bond wafer is performed.
- a bonded wafer having a thin film on the base wafer is manufactured by peeling the bond wafer with the ion implantation layer, and thereafter
- a bonding window characterized in that the surface of the susceptor is coated with a silicon film in advance.
- the wafer for mounting the bonded wafer is placed in advance.
- the surface of the susceptor With a silicon film, when the bonded wafer is subsequently placed on the susceptor and subjected to planarization heat treatment, etching around the bonded wafer is suppressed, and the film thickness is uniform. An excellent planarization heat treatment can be performed, and a bonded wafer with high flatness can be manufactured.
- a silicon single crystal wafer can be used as the bond wafer and the base wafer.
- a silicon single crystal wafer can be used as the bond wafer and the base wafer, and a bonded wafer having a silicon thin film with excellent film thickness uniformity can be manufactured.
- the silicon film to be coated on the susceptor is coated on the surface excluding the region where the back surface of the bonded wafer is in contact with the susceptor.
- the silicon film that coats the susceptor is coated on the surface excluding the region where the back surface of the bonded wafer contacts the susceptor, the silicon film does not contact the back surface of the bonded wafer. It is possible to suppress the occurrence of protrusions on the back surface of the bonded wafer, to obtain a bonded wafer in which the film thickness uniformity of the thin film is good and the generation of protrusions on the back surface is suppressed.
- a dummy wafer is placed on the susceptor, and the surface of the susceptor is coated with the silicon film.
- the dummy wafer is taken out once.
- a dummy wafer is placed on the susceptor, and after the surface of the susceptor is coated with a silicon film, the dummy wafer is taken out once to remove the silicon film from the surface excluding the region where the back surface of the bonded wafer contacts the susceptor. Can be coated in advance.
- an epitaxial layer having excellent film thickness uniformity can be obtained.
- a bonded wafer having a thick SOI layer or the like using an ion implantation separation method can be manufactured.
- the surface of the susceptor for mounting the bonded wafer used for the heat treatment for flattening the thin film surface after delamination is coated with a silicon film in advance.
- etching at the peripheral portion of the bonded wafer is suppressed, and a bonded wafer having a thin film with excellent film thickness uniformity can be manufactured.
- the silicon film that coats the susceptor is coated on the surface excluding the region where the back surface of the bonded wafer contacts the susceptor, the silicon film does not contact the back surface of the bonded wafer.
- production of the protrusion of a bonded wafer back surface can be suppressed.
- Example 1 shows the manufacturing method of the bonded wafer of this invention. It is explanatory drawing which shows the manufacturing method of the conventional bonded wafer. It is explanatory drawing of the generation
- Example 2 (a) Film thickness distribution after planarization heat treatment (plan view, AA ′ sectional view, BB ′ sectional view), and (b) an observation view of protrusions on the back surface of the SOI wafer. . It is the film thickness distribution after planarization heat processing in a comparative example.
- a heat treatment for flattening the surface of the silicon thin film in an atmosphere containing hydrogen or hydrogen chloride is performed.
- the film thickness of the silicon thin film has a problem that the wafer peripheral portion is thin and the central portion is thick and has a poor uniformity distribution. Therefore, a method for producing a bonded wafer that can obtain a thin film with excellent film thickness uniformity is required.
- the present inventor has previously coated the surface of the susceptor used for heat treatment for flattening the thin film surface after peeling with a silicon film in the ion implantation peeling method. After that, when the bonded wafer was placed on the susceptor and flattening heat treatment was performed, it was found that etching around the bonded wafer was suppressed, and flattening heat treatment with excellent film thickness uniformity was possible. .
- the bond wafer 1 and the base wafer 3 for example, two silicon single crystal bare wafers are prepared, and at least one kind of gas ion of hydrogen ion or rare gas ion is ion-implanted from the surface of the bond wafer 1 to perform ion implantation.
- An injection layer 2 is formed, and the surface of the bond wafer 1 subjected to ion implantation and the surface of the base wafer 3 are bonded together via an oxide film 4 (FIG. 1A).
- the bond wafer material is not limited to a silicon single crystal, and an SiGe crystal, a compound semiconductor, or the like can be used.
- a base wafer material an insulating material such as quartz is used in addition to a semiconductor material such as a silicon single crystal. be able to.
- other ion implantation conditions such as implantation energy, implantation dose, and implantation temperature can be appropriately selected so that a thin film having a predetermined thickness can be obtained. .
- the bond wafer 1 and the base wafer 3 are bonded together through the oxide film 4.
- the bonding wafer 1 and the base wafer 3 are bonded directly without using the oxide film 4. May be combined.
- the oxide film 4 may be formed in advance on one side of the bond wafer 1 or the base wafer 3, or may be formed on both wafers.
- the bonded wafer 6 having the thin film 5 on the base wafer 3 is manufactured by peeling the bond wafer with the ion implantation layer 2 (FIG. 1B).
- This peeling is not particularly limited, but can be performed by performing a heat treatment at about 300 to 1100 ° C. in an inert gas atmosphere such as Ar. Further, before bonding the bond wafer 1 and the base wafer 3, the bonding surface of one or both wafers is subjected to plasma treatment to increase the bonding strength, thereby eliminating the peeling heat treatment and mechanically. It can also be peeled off.
- the bonded wafer 6 is placed on a susceptor 8 whose surface has been coated with a silicon film 7 in advance, and heat treatment is performed to flatten the surface of the thin film 5 in an atmosphere containing hydrogen or hydrogen chloride. (FIG. 1 (c)).
- the silicon film can be coated using a gas such as silane, trichlorosilane, or dichlorosilane.
- the difference in activation energy of the silicon film as shown in FIG. 3A (depot (deposition) reaction proceeds on the low temperature side).
- the bonded wafer 23 is placed on the susceptor 22 coated with the silicon film 21 and subjected to planarization heat treatment, the coated silicon is etched.
- the protrusion 24 reflecting the surface shape of the susceptor may be formed by moving and re-depositing (depositing) on the back surface of the bonded wafer 23.
- the silicon film to be coated on the susceptor is coated on the surface excluding the area where the back surface of the bonded wafer contacts the susceptor, that is, the silicon film is coated so that the silicon film does not contact the bonded wafer.
- a dummy wafer 9 is placed on the susceptor 8 as shown in FIG.
- the surface can be coated with a silicon film 7 (FIG. 1 (c′-1)), and then the dummy wafer 9 is taken out once (FIG. 1 (c′-2)).
- a susceptor having no silicon film can be manufactured in a region where a bonded wafer is placed.
- the silicon film 7 is coated using the dummy wafer 9, and after the dummy wafer 9 is taken out, a plurality of sheets are continuously formed.
- the dummy wafer 9 is used to coat the susceptor 8 again with the silicon film 7, and then a plurality of sheets are continuously bonded to the bonded wafer 6. It is preferable to perform heat treatment.
- an epitaxial layer can be grown on the thin film 5 of the bonded wafer 6 obtained, and the film thickness of the bonded wafer manufactured using the method for manufacturing a bonded wafer according to the present invention is reduced.
- An epitaxial layer with excellent uniformity can be obtained. Accordingly, a bonded wafer having a thin film such as a relatively thick SOI layer having a uniform film thickness can be manufactured.
- Example 1 Example 1, Example 2, comparative example
- An SOI wafer having an SOI layer thickness of 250 nm and an oxide film layer of 300 nm was prepared by a hydrogen ion implantation separation method. Thereafter, planarization heat treatment is performed. Before the planarization heat treatment, as shown in Table 1 below, in Example 1, a silicon film is formed on the entire surface of the susceptor for mounting the SOI wafer used in the planarization heat treatment. In Example 2, the silicon film was coated on the surface excluding the region where the back surface of the SOI wafer and the susceptor were in contact with each other. In the comparative example, the susceptor was not coated with a silicon film.
- Example 1 The coating of the silicon film of Example 1 and Example 2 was performed under the following conditions. Temperature: 1080 ° C Gas flow rate: dichlorosilane 450sccm, H 2 53slm Time: 3 minutes
- Table 1 shows the etching amount of each SOI wafer. Temperature: 1050 ° C Gas flow rate: HCl 400sccm, H 2 55slm Time: 7 minutes
- Table 1 below shows the film thickness uniformity after the planarization heat treatment (the value obtained by dividing the PV value of the SOI film thickness after the planarization heat treatment by the etching amount (%)) and the presence or absence of protrusions on the back surface of the SOI wafer.
- . 4A and 4B show the film thickness distribution after the planarization heat treatment of Example 1 and the observation views (2 mm square) of the back surface of the SOI wafer, respectively.
- FIG. 5A and FIG. 5B show the film thickness distribution after the planarization heat treatment of Example 2 and the observation views (2 mm square) of the back surface of the SOI wafer, respectively.
- the film thickness distribution after the planarization heat processing of a comparative example is shown in FIG.
- the SOI film thickness distribution was measured using AcuMap manufactured by ADE, and the back surface was measured using a non-contact surface shape measuring instrument manufactured by WYKO.
- the scale in the film thickness direction is substantially the same scale for FIGS. 4A and 5A.
- FIG. 6 uses a scale approximately four times these.
- Example 1 the epitaxial layer was grown after the planarization heat treatment (temperature: 1080 ° C., gas flow rate: dichlorosilane 450 sccm, H 2 53 slm, time: 3 minutes, epitaxial layer thickness: 3 ⁇ m) .
- Table 1 shows the results of film thickness distribution after epitaxial growth.
- Example 2 From the results in Table 1 and FIGS. 4 to 6, it was found that the film thickness uniformity was remarkably improved by coating the surface of the susceptor with a silicon film before the planarization heat treatment. Further, as in Example 2, the silicon film is coated on the surface excluding the region where the back surface of the bonded wafer and the susceptor are in contact with each other, thereby preventing projections on the back surface of the bonded wafer during the planarization heat treatment. I was able to. Moreover, in Example 1 and Example 2, the epitaxial wafer excellent in film thickness uniformity was able to be produced.
- the present invention is not limited to the above embodiment.
- the above-described embodiment is an exemplification, and the present invention has any configuration that has substantially the same configuration as the technical idea described in the claims of the present invention and that exhibits the same effects. It is contained in the technical range.
Abstract
Description
また、ボンドウェーハ1にイオン注入層2を形成する際、注入エネルギー、注入線量、注入温度等その他のイオン注入条件を、所定の厚さの薄膜を得ることができるように適宜選択することができる。
また、図1(a)では、ボンドウェーハ1とベースウェーハ3を酸化膜4を介して貼り合わせているが、本発明の貼り合わせウェーハの製造方法においては、酸化膜4を介さずに直接貼り合わせても良い。酸化膜4を介して貼り合わせる場合には、予めボンドウェーハ1又はベースウェーハ3の片方に酸化膜4が形成されていても良いし、両ウェーハに形成されていても良い。
また、ボンドウェーハ1とベースウェーハ3とを貼り合わせる前に、どちらか一方又は両方のウェーハの貼り合わせ面にプラズマ処理を施して、結合強度を高めることによって、剥離熱処理を省略し、機械的に剥離させることもできる。
このようにダミーウェーハを用いれば、貼り合わせウェーハが載置される領域はシリコン膜がないサセプタを作製することができる。このサセプタに貼り合わせウェーハ6を載置し、薄膜5の表面を平坦化する熱処理を施すことで(図1(c’-3))、薄膜5の膜厚均一性が良く、更に、貼り合わせウェーハ6の裏面に突起物の発生がない貼り合わせウェーハ6を製造することができる。
直径300mmのシリコン単結晶ウェーハを2枚準備し、水素イオン注入剥離法により、SOI層の厚さが250nm、酸化膜層が300nmのSOIウェーハを作製した。その後、平坦化熱処理を施すが、この平坦化熱処理の前に、下記表1に示すように、実施例1では平坦化熱処理時に用いるSOIウェーハを載置するためのサセプタの全表面に、シリコン膜をコーティングしておき、実施例2では、SOIウェーハの裏面とサセプタが接触する領域を除く表面にシリコン膜をコーティングしておいた。比較例では、サセプタにシリコン膜のコーティングは行わなかった。
温度:1080℃
ガス流量:ジクロロシラン 450sccm、H2 53slm
時間:3分
温度:1050℃
ガス流量:HCl 400sccm、H2 55slm
時間:7分
この際、SOI膜厚分布はADE社製AcuMapを用い、裏面の観察はWYKO社製非接触表面形状測定器を用いて測定した。尚、図4(a)、図5(a)、図6の断面図において、膜厚方向の目盛は、図4(a)、図5(a)についてはほぼ同一の尺度が用いられているのに対し、図6はこれらの約4倍の尺度が用いられている。
Claims (5)
- ボンドウェーハの表面から水素イオン、希ガスイオンの少なくとも一種類のガスイオンをイオン注入してイオン注入層を形成し、前記ボンドウェーハのイオン注入した表面とベースウェーハの表面とを直接又は酸化膜を介して貼り合わせた後、前記イオン注入層でボンドウェーハを剥離させることにより、前記ベースウェーハ上に薄膜を有する貼り合わせウェーハを作製し、その後、該貼り合わせウェーハに、水素又は塩化水素を含む雰囲気中で前記薄膜の表面を平坦化する熱処理を施す貼り合わせウェーハの製造方法において、
前記平坦化熱処理時に用いる前記貼り合わせウェーハを載置するためのサセプタの表面を、予めシリコン膜でコーティングしておくことを特徴とする貼り合わせウェーハの製造方法。
- 前記ボンドウェーハ及び前記ベースウェーハとして、シリコン単結晶ウェーハを用いることを特徴とする請求項1に記載の貼り合わせウェーハの製造方法。
- 前記サセプタにコーティングするシリコン膜を、前記貼り合わせウェーハの裏面が前記サセプタと接触する領域を除く表面にコーティングすることを特徴とする請求項1又は請求項2に記載の貼り合わせウェーハの製造方法。
- 前記貼り合わせウェーハの裏面と前記サセプタとが接触する領域を除くサセプタの表面のシリコン膜のコーティングを、前記サセプタにダミーウェーハを載置し、該サセプタの表面を前記シリコン膜でコーティングした後に前記ダミーウェーハを一度取り出すことで行うことを特徴とする請求項3に記載の貼り合わせウェーハの製造方法。
- 前記平坦化熱処理を行った貼り合わせウェーハの薄膜上に、エピタキシャル層を成長させることを特徴とする請求項1乃至請求項4のいずれか一項に記載の貼り合わせウェーハの製造方法。
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US13/514,414 US8691665B2 (en) | 2010-01-12 | 2010-11-18 | Method for producing bonded wafer |
CN201080056111.4A CN102652347B (zh) | 2010-01-12 | 2010-11-18 | 贴合晶片的制造方法 |
KR1020127017904A KR101722401B1 (ko) | 2010-01-12 | 2010-11-18 | 접합 웨이퍼의 제조 방법 |
EP10842988.7A EP2525390B1 (en) | 2010-01-12 | 2010-11-18 | Method for producing bonded wafer |
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JP2010004271A JP5521561B2 (ja) | 2010-01-12 | 2010-01-12 | 貼り合わせウェーハの製造方法 |
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WO2013088636A1 (ja) * | 2011-12-15 | 2013-06-20 | 信越半導体株式会社 | Soiウェーハの製造方法 |
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JP5799740B2 (ja) | 2011-10-17 | 2015-10-28 | 信越半導体株式会社 | 剥離ウェーハの再生加工方法 |
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KR101722401B1 (ko) | 2017-04-03 |
KR20120112533A (ko) | 2012-10-11 |
TWI493608B (zh) | 2015-07-21 |
JP2011146438A (ja) | 2011-07-28 |
TW201131625A (en) | 2011-09-16 |
CN102652347B (zh) | 2015-07-01 |
US20120244679A1 (en) | 2012-09-27 |
JP5521561B2 (ja) | 2014-06-18 |
US8691665B2 (en) | 2014-04-08 |
CN102652347A (zh) | 2012-08-29 |
EP2525390A4 (en) | 2013-07-03 |
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EP2525390B1 (en) | 2016-05-11 |
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