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US3785862A - Method for depositing refractory metals - Google Patents

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US3785862A
US3785862A US3785862DA US3785862A US 3785862 A US3785862 A US 3785862A US 3785862D A US3785862D A US 3785862DA US 3785862 A US3785862 A US 3785862A
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layer
hexafluoride
tungsten
silicon
tube
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W Grill
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RCA Corp
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    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227Inductive arrangements or effects of, or between, wiring layers
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/52Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • HELECTRICITY
    • H01BASIC ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES; ELECTRIC SOLID STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

A method for depositing a refractory metal on a semiconductor oxide coating, comprising simultaneously etching the oxide coating with the metallic hexafluoride and depositing a relatively thin layer of the refractory metal by reduction of the hexafluoride, and thereafter depositing a relatively thick layer of the refractory metal by reduction of the hexafluoride alone.

Description

United States Patent Grill Jan. 15, 1974 METHOD FOR DEPOSITING REFRACTORY METALS [75] Inventor: William Augustus Grill, Parsippany,

[73] Assignee: RCA Corporation, New York, NY.

[22] Filed: Dec. 14, 1970 [21] Appl. No.: 97,796

[52] US. Cl 117/217, 117/107.2 R, 117/227, 156/17 [51] Int. Cl B44d 1/18 [58] Field of Search 117 /1072 R, 212, 117/217, 201,227; 156/17 [56] I References Cited UNITED STATES PATENTS 3,477,872 ll/l969 Amick ..l17/212 w my 3/1966 Corrigan et a1 156/17 7/1968 Merkelet al. 156/17 Primary Examiner-Cameron K. Weiffenbach 57 ABSTRACT A method for depositing a refractory metal on a semiconductor oxide coating, comprising simultaneously etching the oxide coating with the metallic hexafluoride and depositing a relatively thin layer of the refractory metal by reduction of the hexafluoride, and thereafter depositing a relatively thick layer of the refractory metal by reduction of the hexafluoride alone.

3 Claims, 6 Drawing Figures woman/4 l/ra/vmzw IiMF/WI/Ii M r MI) I METHOD FOR DEPOSITING REFRACTORY METALS BACKGROUND OF THE INVENTION The present invention relates to an improved method for depositing a refractory metal on certain substrates and, more particularly, to an improved method for depositing tungsten on a substrate which comprises silicon dioxide.

An important advance in the ability to deposit refractory metals on silicon dioxide layers is disclosed in US. Pat. No. 3,477,872 to Amick. This method is a two-step process in which the oxide layer is first etched with the hexafiuoride of the refractory metal, in an inert atmosphere. Thereafter, the refractory metal is deposited on the etched oxide layer by the hydrogen reduction of the hexafluoride. This process results in a refractory metal layer which adheres well to the oxide layer. However, it is often difficult to control the etching rate in a reproducible manner; thus, the oxide is often etched back beyond the PN junctions of the device which extend to the device surface, thereby exposing the junctions and making the device unusable.

SUMMARY OF THE INVENTION The present invention comprises an improved process for depositing tungsten or molybdenum on a silicon dioxide layer. The process comprises the steps of heating the silicon dioxide layer in an enclosed chamber to a temperature of about 500C to 800C. An inert gas, such as nitrogen, and a reducing gas, such as hydrogen, are introduced into the chamber in the ratio of between about20:l to 40:1, respectively. The silicon dioxide layer is then treated with a vaporized substance selected from the group consistingoftungsten hexafluoride and molybdenum hexafluoride for a brief period, in order to etch the silicon dioxide layer and deposit a relatively thin layer of tungsten or molybdenum thereon. The chamber is then purged of all the unre' acted hexafluoride. The inert gas flow is discontinued, and additional reducinggas and newly vaporized hexafluoride are mixed in the chamber to reduce the hexafluoride and-deposit a relatively thick layer of the metal constituentthereof on the thin layer.

Treatment of the silicon oxide surface with the hexafluoride etches the oxide'layer, modifying its properties such that a refractory metal layer adheres much better than without such treatment; additionally, the simultaneous reduction of a small amount of the hexafluoride controls the etching attack during the etching step, which protects the silicon dioxide over the PN junctions from further etching.

THE DRAWINGS FIG. 1 is a cross-section of a semiconductor chip with circuit components already fabricated therein, and provided with a silicon oxide layer on which tungsten is to be deposited in accordance with the method of this invention.

FIG. 2 is a view like that of FIG. 1 showing further steps which may precede the carrying out of the present method.

FIG. 3 is a schematic diagram, partially in section, of apparatus that could be used in carrying out the method of the present invention.

FIG. 4 is a view like that of FIGS. 1 and 2 illustrating a first step in carrying out the present method.

FIG. 5 is a view like that of FIG. 4 showing a further processing step in carrying out the method of the present invention.

FIG. 6 is a view like that of FIG. 5 showing a further processing step that may be used in making a microcircult.

DETAILED DESCRIPTION EXAMPLE A specific example will now be given of how the method of the present invention can be utilized in making a microcircuit of the'silicon monolithic type, but it will be understood that this is by way of example only and that the method is not limited to the manufacture of any particular product.

As shown in FIG. 1, the microcircuit being fabricated comprises a single crystal chip of silicon 2 having a transistor 4 and a diffused resistor 6 fabricated therein. The transistor 4 includes a base region 8 and an emitter region 10 made by diffusing suitable impurities into one surface of the chip 2. The transistor 4 also includes a collector region which is part of the chip 2 outside the base region 8. The resistor 6 is also made by diffusing suitable impurities into the chip 2. The entire surface of the chip 2, into which the circuit components 4 and 6 are fabricated, is covered with a silicon dioxide layer 12 which protects the PN junctions exposed at the surface of the silicon chip, and also serves as an insulating substrate for carrying metal interconnections.

The circuit components are to be interconnected with conductors made of tungsten. In order that interconnecting conductors can make contact with the circuit components, as shown in FIG. 2, suitable openings are made in the silicon dioxide layer 12 using conventional photoresist masking and etching techniques. By these techniques, an opening 14 in the layer 12 is made to expose a part of the base region 8, and an opening 16 is made to expose a part of the emitter region 10. Similar openings 18 and 20 are provided to expose portions of the opposite ends of the resistor 6.

In order to carry out the processing steps of the present method, the chip 2, as shown in FIG. 2, is placed within a quartz furnace tube 22 which is a part of the apparatus shown in FIG. 3. The assembly is supported on the top of a susceptor block 24 made of carbon coated with silicon carbide. The susceptor block rests on a tilted quartz support 26. The interior of the carbon block contains a thermocouple 28 connected by wires 29 to an RF generator, not shown. The furnace tube 22 is provided with an inlet tube 30 and a flow meter 32 which measures the flow rate of the incoming gas. The furnace tube is also provided with an outlet tube 34 so that exhaust gases may be passed off to a fume hood or other disposal means, not shown. A gas manifold 35 is connected to the flow meter 32 which measures the incoming flow of gas to the furnace tube 22. Connected to the manifold 35 is a flow meter 36 and an inlet tube 38 provided with suitable valves for admitting measured quantities of an inert gas to the system; in this example, nitrogen is used. Also connected to the gas manifold 35 is a second flow meter 40 and an inlet tube 42, provided with suitable valves, for admitting a reducing gas into the system; in this example, hydrogen is used. Included in the hydrogen inlet line is a palladium diffuser 44, which serves to purify the hydrogen gas. Also connected to the manifold 35 is a third flow meter 46 and an inlet tube 48 for admitting tungsten hexafluoride into the system. The gas inlet tube 48 is provided with a branch tube 50 which has a valve for admitting nitrogen into the line for purging purposes.

Before introducing the microcircuit chip into the furnace tube 22, the silicon dioxide surface may first be suitably cleaned, e.g., by rinsing in Methanol, or any other suitable cleaning agent. This step is not essential and may be omitted if the silicon dioxide surface is already sufficiently clean.

After the microcircuit is placed within the furnace tube 22, the tube is closed off and then heated by means of an RF induction coil 52 from the RF generator previously mentioned but not shown, to a temperature of about 500C to 800C (preferably at about 700C). Meanwhile, nitrogen is admitted through the inlet tube 38 and the flow meter 36 so that it passes through the manifold 35, the flow meter 32 and the inlet tube 30, to enter the furnace tube 22 at a rate of about 30 cfh (cubic feet per hour).

Tungsten hexafluoride in gaseous form is then admitted through the inlet tube 48 and the flow meter 46 to join the nitrogen stream in the manifold 35 and pass into the furnace tube 22 at a rate of about 30 cc per minute (about 0.063 cfh). Hydrogen is also admitted through the inlet tube 42 and the flow meter 40 at a rate of about 1.0 cfh to join the nitrogen and tungsten hexafluoride streams in the manifold 35, and pass into the furnace tube 22. It is necessary to maintain the ratio of nitrogen to hydrogen between about to 40:l, respectively, because it has been found that a ratio of significantly below 20:] results in an undesirable amount of hydrogen reduction, while a ratio significantly above 40:1 results in an undesirably high etching rate. A ratio of about 30:1 nitrogen to hydrogen is optimum.

As the mixture of nitrogen, hydrogen, and tungsten hexafluoride passes over the microcircuit assembly, the silicon which is exposed at the bottom of the openings l4, l6, l8, and 20 in the silicon dioxide layer 12, reacts with the tungsten hexafluoride, and by a silicon replacement reaction, a thin layer of tungsten 54 is deposited in the openings and on the silicon (FIG. 4). At the same time, the tungsten hexafluoride gas etches the surface of the silicon dioxide layer 12 and roughens it slightly; simultaneously, the hydrogen reacts with the tungsten hexafluoride, and, by a hydrogen reduction process a thin layer 56 of tungsten, about 2,000A. thick, is deposited over the silicon dioxide layer 12, as shown in FIG. 4. The present step of treatment is permitted to continue for a few seconds.

At the conclusion of the etching and partial deposition step, the tungsten hexafluoride flow is terminated, and the tungsten hexafluoride is purged from the apparatus by permitting nitrogen to continue flowing into the system at a rate of about 4,000 cc per minute (about 8.4 cfh) for a time sufficient to sweep all the unreacted hexafluoride out of the furnace tube 22. The nitrogen flow is then discontinued.

The hydrogen flow is continued through the furnace tube 22 at a rate of about 2,000 cc per minute (about 4.2 cfli). Next, tungsten hexafluoride at a rate of about 30 cc per minute (about 0.063 cfh) is again admitted into the gaseous stream through the inlet tube 48 and the flow meter 46. The heating temperature of the assembly is the same as mentioned previously. Under these conditions, as shown in FIG. 5, the hydrogen reduces the tungsten hexafluoride and deposits tungsten on all of the heated surface. Thus, a relatively thick layer of tungsten is deposited on the entire surface of the thin layers of tungsten 54 and 56 over the silicon and the silicon dioxide. Suitably, the composite thick tungsten layer 56' is about 2.0 microns thick. At the conclusion of the tungsten deposition process, the tungsten hexafluoride and hydrogen flows are discontinued, and nitrogen is admitted through the branch line 50 to purge the apparatus of the corrosive tungsten hexafluoride to prevent attack of the apparatus walls.

In order to remove unwanted tungsten from the layer 56 and leave only the desired pattern of interconnections, excess tungsten can be removed with any suitable masking and etching technique, resulting in a microcircuit like that shown in FIG. 6.

Although the method has been illustrated with an example in which tungsten is the deposited metal, molybdenum can be similarly deposited from molybdenum hexafluoride.

I claim:

1. An improved process for depositing tungsten or molybdenum on a silicon dioxide layer, comprising the steps of:

a. heating said silicon dioxide layer in an enclosed chamber to a temperature of about 500C. to 800C;

b. introducing an inert gas and a reducing gas into said chamber;

0. treating said silicon dioxide layer with a vaporized substance selected from the group consisting of tungsten hexafluoride and molybdenum hexafluoride for a brief period to etch said silicon dioxide layer and deposit a thin layer of tungsten or molybdenum thereon,

d. purging all of the unreacted hexafluoride from said chamber,

e. discontinuing the introduction of said inert gas into said chamber, and thereafter f. mixing additional reducing gas with more of said vaporized substance in said chamber to reduce said substance and deposit a thick layer of the metal constituent thereof on said thin layer.

2. A process according to claim 1, wherein the ratio of inert gas to reducing gas is between about 20:] to 40:1.

3. A process according to claim 2, wherein said reducing gas consists essentially of hydrogen.

Claims (2)

  1. 2. A process according to claim 1, wherein the ratio of inert gas to reducing gas is between about 20:1 to 40:1.
  2. 3. A process according to claim 2, wherein said reducing gas consists essentially of hydrogen.
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Cited By (28)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3881242A (en) * 1972-11-08 1975-05-06 Ferranti Ltd Methods of manufacturing semiconductor devices
US4265935A (en) * 1977-04-28 1981-05-05 Micro Power Systems Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
US4283439A (en) * 1977-12-23 1981-08-11 Vlsi Technology Research Association Method of manufacturing a semiconductor device by forming a tungsten silicide or molybdenum silicide electrode
US4343676A (en) * 1981-03-26 1982-08-10 Rca Corporation Etching a semiconductor material and automatically stopping same
US4349408A (en) * 1981-03-26 1982-09-14 Rca Corporation Method of depositing a refractory metal on a semiconductor substrate
US4404235A (en) * 1981-02-23 1983-09-13 Rca Corporation Method for improving adhesion of metal film on a dielectric surface
US4471004A (en) * 1983-04-28 1984-09-11 General Electric Company Method of forming refractory metal conductors of low resistivity
US4584207A (en) * 1984-09-24 1986-04-22 General Electric Company Method for nucleating and growing tungsten films
US4617087A (en) * 1985-09-27 1986-10-14 International Business Machines Corporation Method for differential selective deposition of metal for fabricating metal contacts in integrated semiconductor circuits
US4650696A (en) * 1985-10-01 1987-03-17 Harris Corporation Process using tungsten for multilevel metallization
US4732801A (en) * 1986-04-30 1988-03-22 International Business Machines Corporation Graded oxide/nitride via structure and method of fabrication therefor
US4741928A (en) * 1985-12-27 1988-05-03 General Electric Company Method for selective deposition of tungsten by chemical vapor deposition onto metal and semiconductor surfaces
US4808552A (en) * 1985-09-11 1989-02-28 Texas Instruments Incorporated Process for making vertically-oriented interconnections for VLSI devices
US4902533A (en) * 1987-06-19 1990-02-20 Motorola, Inc. Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide
US4957880A (en) * 1985-05-29 1990-09-18 Kabushiki Kaisha Toshiba Method for producing semiconductor device including a refractory metal pattern
US5026664A (en) * 1988-04-07 1991-06-25 Hitachi, Ltd. Method of providing a semiconductor IC device with an additional conduction path
US5037775A (en) * 1988-11-30 1991-08-06 Mcnc Method for selectively depositing single elemental semiconductor material on substrates
US5084414A (en) * 1985-03-15 1992-01-28 Hewlett-Packard Company Metal interconnection system with a planar surface
US5112439A (en) * 1988-11-30 1992-05-12 Mcnc Method for selectively depositing material on substrates
US5182231A (en) * 1988-04-07 1993-01-26 Hitachi, Ltd. Method for modifying wiring of semiconductor device
US5356659A (en) * 1986-07-31 1994-10-18 At&T Bell Laboratories Metallization for semiconductor devices
US6022485A (en) * 1997-10-17 2000-02-08 International Business Machines Corporation Method for controlled removal of material from a solid surface
US6258174B1 (en) * 1990-02-19 2001-07-10 Canon Kabushiki Kaisha Gas supplying apparatus
US20040060512A1 (en) * 2002-09-30 2004-04-01 Waldhauer Ann P. High temperature anneal with improved substrate support
US7211144B2 (en) * 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
US20080311741A1 (en) * 2005-03-14 2008-12-18 Narishi Gonohe Selective W-Cvd Method and Method for Forming Multi-Layered Cu Electrical Interconnection
US20100025395A1 (en) * 2008-07-29 2010-02-04 Ivoclar Vivadent Ag Apparatus for the heating of molding, in particular dental-ceramic moldings
US20120244679A1 (en) * 2010-01-12 2012-09-27 Shin-Etsu Handotai Co., Ltd. Method for producing bonded wafer

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS52138961U (en) * 1976-04-16 1977-10-21
JPS54151577U (en) * 1978-04-10 1979-10-22
DE3141567C2 (en) * 1981-10-20 1986-02-06 Siemens Ag, 1000 Berlin Und 8000 Muenchen, De

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3477872A (en) * 1966-09-21 1969-11-11 Rca Corp Method of depositing refractory metals

Cited By (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3881242A (en) * 1972-11-08 1975-05-06 Ferranti Ltd Methods of manufacturing semiconductor devices
US4265935A (en) * 1977-04-28 1981-05-05 Micro Power Systems Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
US4283439A (en) * 1977-12-23 1981-08-11 Vlsi Technology Research Association Method of manufacturing a semiconductor device by forming a tungsten silicide or molybdenum silicide electrode
US4404235A (en) * 1981-02-23 1983-09-13 Rca Corporation Method for improving adhesion of metal film on a dielectric surface
US4343676A (en) * 1981-03-26 1982-08-10 Rca Corporation Etching a semiconductor material and automatically stopping same
US4349408A (en) * 1981-03-26 1982-09-14 Rca Corporation Method of depositing a refractory metal on a semiconductor substrate
US4471004A (en) * 1983-04-28 1984-09-11 General Electric Company Method of forming refractory metal conductors of low resistivity
US4584207A (en) * 1984-09-24 1986-04-22 General Electric Company Method for nucleating and growing tungsten films
US5084414A (en) * 1985-03-15 1992-01-28 Hewlett-Packard Company Metal interconnection system with a planar surface
US4957880A (en) * 1985-05-29 1990-09-18 Kabushiki Kaisha Toshiba Method for producing semiconductor device including a refractory metal pattern
US4808552A (en) * 1985-09-11 1989-02-28 Texas Instruments Incorporated Process for making vertically-oriented interconnections for VLSI devices
US4617087A (en) * 1985-09-27 1986-10-14 International Business Machines Corporation Method for differential selective deposition of metal for fabricating metal contacts in integrated semiconductor circuits
US4650696A (en) * 1985-10-01 1987-03-17 Harris Corporation Process using tungsten for multilevel metallization
US4741928A (en) * 1985-12-27 1988-05-03 General Electric Company Method for selective deposition of tungsten by chemical vapor deposition onto metal and semiconductor surfaces
US4732801A (en) * 1986-04-30 1988-03-22 International Business Machines Corporation Graded oxide/nitride via structure and method of fabrication therefor
US5356659A (en) * 1986-07-31 1994-10-18 At&T Bell Laboratories Metallization for semiconductor devices
US4902533A (en) * 1987-06-19 1990-02-20 Motorola, Inc. Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide
US5026664A (en) * 1988-04-07 1991-06-25 Hitachi, Ltd. Method of providing a semiconductor IC device with an additional conduction path
US5182231A (en) * 1988-04-07 1993-01-26 Hitachi, Ltd. Method for modifying wiring of semiconductor device
US5037775A (en) * 1988-11-30 1991-08-06 Mcnc Method for selectively depositing single elemental semiconductor material on substrates
US5112439A (en) * 1988-11-30 1992-05-12 Mcnc Method for selectively depositing material on substrates
US6258174B1 (en) * 1990-02-19 2001-07-10 Canon Kabushiki Kaisha Gas supplying apparatus
US6254719B1 (en) 1997-10-17 2001-07-03 International Business Machines Corporation Method for controlled removal of material from a solid surface
US6022485A (en) * 1997-10-17 2000-02-08 International Business Machines Corporation Method for controlled removal of material from a solid surface
US7211144B2 (en) * 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
US20080317954A1 (en) * 2001-07-13 2008-12-25 Xinliang Lu Pulsed deposition process for tungsten nucleation
US7695563B2 (en) 2001-07-13 2010-04-13 Applied Materials, Inc. Pulsed deposition process for tungsten nucleation
US20040060512A1 (en) * 2002-09-30 2004-04-01 Waldhauer Ann P. High temperature anneal with improved substrate support
US7704327B2 (en) * 2002-09-30 2010-04-27 Applied Materials, Inc. High temperature anneal with improved substrate support
US20080311741A1 (en) * 2005-03-14 2008-12-18 Narishi Gonohe Selective W-Cvd Method and Method for Forming Multi-Layered Cu Electrical Interconnection
US7790590B2 (en) * 2005-03-14 2010-09-07 Ulvac, Inc. Selective W-CVD method and method for forming multi-layered Cu electrical interconnection
US20100025395A1 (en) * 2008-07-29 2010-02-04 Ivoclar Vivadent Ag Apparatus for the heating of molding, in particular dental-ceramic moldings
US20120244679A1 (en) * 2010-01-12 2012-09-27 Shin-Etsu Handotai Co., Ltd. Method for producing bonded wafer
US8691665B2 (en) * 2010-01-12 2014-04-08 Shin-Etsu Handotai Co., Ltd. Method for producing bonded wafer

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FR2118011A1 (en) 1972-07-28 application
BE776573A (en) 1972-04-04 grant
CA960923A1 (en) grant
FR2118011B1 (en) 1975-08-29 grant
GB1364898A (en) 1974-08-29 application
DE2161055A1 (en) 1972-06-29 application
CA960923A (en) 1975-01-14 grant
JPS517156B1 (en) 1976-03-05 grant

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