GB1364898A - Method for depositing refractory metal - Google Patents

Method for depositing refractory metal

Info

Publication number
GB1364898A
GB1364898A GB5735171A GB5735171A GB1364898A GB 1364898 A GB1364898 A GB 1364898A GB 5735171 A GB5735171 A GB 5735171A GB 5735171 A GB5735171 A GB 5735171A GB 1364898 A GB1364898 A GB 1364898A
Authority
GB
United Kingdom
Prior art keywords
chamber
deposition
mof
dec
sio
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB5735171A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
RCA Corp
Original Assignee
RCA Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by RCA Corp filed Critical RCA Corp
Publication of GB1364898A publication Critical patent/GB1364898A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5227—Inductive arrangements or effects of, or between, wiring layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical Vapour Deposition (AREA)
  • Electrodes Of Semiconductors (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

1364898 Coating with tungsten or molybdenum RCA CORPORATION 9 Dec 1971 [14 Dec 1970] 57351/71 Heading C7F [Also in Division H1] A silicon dioxide layer is coated with W or Mo by deposition from WF 6 or MoF 6 . A silicon chip 2, having a transistor 8, 10 and resistor 6 fabricated therein, has a coating of SiO 2 12, etched to form openings 14, 16, 18, 20. The chip 2 is heated in a chamber to 500-800‹C, preferably 700‹C after which an inert gas, e.g. N 2 , reducing gas, e.g. H 2 , and gaseous WF 6 (or MoF 6 ) are fed in, the ratio of N 2 :H 2 being between 20:1 and 40:1. A deposit of W 54, is formed in the openings 14, 16, 18, 20 by Si replacement, whilst the gaseous WF 6 etches the SiO 2 surface, and a thin layer of W 56, is formed by reduction of the WF 6 . After this partial deposition, the WF 6 flow is stopped, the chamber purged with N 2 , and then WF 6 and H 2 only are fed in resulting in extra deposition of W on the previous layer 56. Finally, the chamber is again purged with N 2 . Unwanted W (or Mo) can be removed by any suitable etching technique.
GB5735171A 1970-12-14 1971-12-09 Method for depositing refractory metal Expired GB1364898A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US9779670A 1970-12-14 1970-12-14

Publications (1)

Publication Number Publication Date
GB1364898A true GB1364898A (en) 1974-08-29

Family

ID=22265175

Family Applications (1)

Application Number Title Priority Date Filing Date
GB5735171A Expired GB1364898A (en) 1970-12-14 1971-12-09 Method for depositing refractory metal

Country Status (7)

Country Link
US (1) US3785862A (en)
JP (1) JPS517156B1 (en)
BE (1) BE776573A (en)
CA (1) CA960923A (en)
DE (1) DE2161055A1 (en)
FR (1) FR2118011B1 (en)
GB (1) GB1364898A (en)

Families Citing this family (31)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1399163A (en) * 1972-11-08 1975-06-25 Ferranti Ltd Methods of manufacturing semiconductor devices
JPS52138961U (en) * 1976-04-16 1977-10-21
US4265935A (en) * 1977-04-28 1981-05-05 Micro Power Systems Inc. High temperature refractory metal contact assembly and multiple layer interconnect structure
JPS5487175A (en) * 1977-12-23 1979-07-11 Cho Lsi Gijutsu Kenkyu Kumiai Method of fabricating semiconductor
JPS54151577U (en) * 1978-04-10 1979-10-22
US4404235A (en) * 1981-02-23 1983-09-13 Rca Corporation Method for improving adhesion of metal film on a dielectric surface
US4343676A (en) * 1981-03-26 1982-08-10 Rca Corporation Etching a semiconductor material and automatically stopping same
US4349408A (en) * 1981-03-26 1982-09-14 Rca Corporation Method of depositing a refractory metal on a semiconductor substrate
DE3141567C2 (en) * 1981-10-20 1986-02-06 Siemens AG, 1000 Berlin und 8000 München Process for producing layers consisting of tantalum, tungsten or molybdenum at low temperatures and using these layers
US4471004A (en) * 1983-04-28 1984-09-11 General Electric Company Method of forming refractory metal conductors of low resistivity
US4584207A (en) * 1984-09-24 1986-04-22 General Electric Company Method for nucleating and growing tungsten films
US5084414A (en) * 1985-03-15 1992-01-28 Hewlett-Packard Company Metal interconnection system with a planar surface
JPS61274345A (en) * 1985-05-29 1986-12-04 Toshiba Corp Manufacture of semiconductor device
US4808552A (en) * 1985-09-11 1989-02-28 Texas Instruments Incorporated Process for making vertically-oriented interconnections for VLSI devices
US4617087A (en) * 1985-09-27 1986-10-14 International Business Machines Corporation Method for differential selective deposition of metal for fabricating metal contacts in integrated semiconductor circuits
US4650696A (en) * 1985-10-01 1987-03-17 Harris Corporation Process using tungsten for multilevel metallization
US4741928A (en) * 1985-12-27 1988-05-03 General Electric Company Method for selective deposition of tungsten by chemical vapor deposition onto metal and semiconductor surfaces
US4732801A (en) * 1986-04-30 1988-03-22 International Business Machines Corporation Graded oxide/nitride via structure and method of fabrication therefor
EP0275299A1 (en) * 1986-07-31 1988-07-27 AT&T Corp. Semiconductor devices having improved metallization
US4902533A (en) * 1987-06-19 1990-02-20 Motorola, Inc. Method for selectively depositing tungsten on a substrate by using a spin-on metal oxide
JP2733244B2 (en) * 1988-04-07 1998-03-30 株式会社日立製作所 Wiring formation method
US5182231A (en) * 1988-04-07 1993-01-26 Hitachi, Ltd. Method for modifying wiring of semiconductor device
US5037775A (en) * 1988-11-30 1991-08-06 Mcnc Method for selectively depositing single elemental semiconductor material on substrates
US5112439A (en) * 1988-11-30 1992-05-12 Mcnc Method for selectively depositing material on substrates
ATE139866T1 (en) * 1990-02-19 1996-07-15 Canon Kk METHOD FOR PRODUCING DEPOSITED METAL LAYER CONTAINING ALUMINUM AS A MAIN COMPONENT USING ALKYL ALUMINUM HYDRIDE
US6022485A (en) 1997-10-17 2000-02-08 International Business Machines Corporation Method for controlled removal of material from a solid surface
US7211144B2 (en) * 2001-07-13 2007-05-01 Applied Materials, Inc. Pulsed nucleation deposition of tungsten layers
US7704327B2 (en) * 2002-09-30 2010-04-27 Applied Materials, Inc. High temperature anneal with improved substrate support
JP4941921B2 (en) * 2005-03-14 2012-05-30 株式会社アルバック Selective W-CVD method and Cu multilayer wiring fabrication method
DE102008035235B4 (en) * 2008-07-29 2014-05-22 Ivoclar Vivadent Ag Device for heating molded parts, in particular dental ceramic molded parts
JP5521561B2 (en) * 2010-01-12 2014-06-18 信越半導体株式会社 Manufacturing method of bonded wafer

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3477872A (en) * 1966-09-21 1969-11-11 Rca Corp Method of depositing refractory metals

Also Published As

Publication number Publication date
JPS517156B1 (en) 1976-03-05
CA960923A (en) 1975-01-14
BE776573A (en) 1972-04-04
FR2118011A1 (en) 1972-07-28
DE2161055A1 (en) 1972-06-29
FR2118011B1 (en) 1975-08-29
US3785862A (en) 1974-01-15

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee