WO2011010653A1 - 被膜表面処理方法、及び被膜表面処理装置 - Google Patents
被膜表面処理方法、及び被膜表面処理装置 Download PDFInfo
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- WO2011010653A1 WO2011010653A1 PCT/JP2010/062217 JP2010062217W WO2011010653A1 WO 2011010653 A1 WO2011010653 A1 WO 2011010653A1 JP 2010062217 W JP2010062217 W JP 2010062217W WO 2011010653 A1 WO2011010653 A1 WO 2011010653A1
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- 238000000034 method Methods 0.000 title claims abstract description 57
- 239000000758 substrate Substances 0.000 claims abstract description 95
- 238000009832 plasma treatment Methods 0.000 claims abstract description 25
- 239000011248 coating agent Substances 0.000 claims description 71
- 238000000576 coating method Methods 0.000 claims description 71
- 238000004544 sputter deposition Methods 0.000 claims description 41
- 238000004381 surface treatment Methods 0.000 claims description 33
- 230000015572 biosynthetic process Effects 0.000 claims description 13
- 230000014509 gene expression Effects 0.000 claims description 4
- 239000011148 porous material Substances 0.000 abstract 3
- 239000010408 film Substances 0.000 description 83
- 239000007789 gas Substances 0.000 description 16
- 239000010949 copper Substances 0.000 description 15
- 229910052802 copper Inorganic materials 0.000 description 13
- 239000000463 material Substances 0.000 description 13
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 12
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 11
- 229910052710 silicon Inorganic materials 0.000 description 11
- 239000010703 silicon Substances 0.000 description 11
- 230000000694 effects Effects 0.000 description 9
- 235000012431 wafers Nutrition 0.000 description 9
- 239000011261 inert gas Substances 0.000 description 7
- 239000002245 particle Substances 0.000 description 6
- 239000004065 semiconductor Substances 0.000 description 5
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 description 4
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 4
- 230000007423 decrease Effects 0.000 description 4
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 3
- 229910052786 argon Inorganic materials 0.000 description 3
- 238000005229 chemical vapour deposition Methods 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 239000011651 chromium Substances 0.000 description 2
- 238000005516 engineering process Methods 0.000 description 2
- 229910052737 gold Inorganic materials 0.000 description 2
- 229910052743 krypton Inorganic materials 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 229910052763 palladium Inorganic materials 0.000 description 2
- 238000005240 physical vapour deposition Methods 0.000 description 2
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 2
- 229910052709 silver Inorganic materials 0.000 description 2
- VYZAMTAEIAYCRO-UHFFFAOYSA-N Chromium Chemical compound [Cr] VYZAMTAEIAYCRO-UHFFFAOYSA-N 0.000 description 1
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000004888 barrier function Effects 0.000 description 1
- 229910052804 chromium Inorganic materials 0.000 description 1
- 238000001816 cooling Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000004907 flux Effects 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000001307 helium Substances 0.000 description 1
- 229910052734 helium Inorganic materials 0.000 description 1
- SWQJXJOGLNCZEY-UHFFFAOYSA-N helium atom Chemical compound [He] SWQJXJOGLNCZEY-UHFFFAOYSA-N 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- DNNSSWSSYDEUBZ-UHFFFAOYSA-N krypton atom Chemical compound [Kr] DNNSSWSSYDEUBZ-UHFFFAOYSA-N 0.000 description 1
- 229910052751 metal Inorganic materials 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 239000010944 silver (metal) Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000013077 target material Substances 0.000 description 1
- 238000002230 thermal chemical vapour deposition Methods 0.000 description 1
- 239000010409 thin film Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
- 238000001947 vapour-phase growth Methods 0.000 description 1
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
- H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
- H01L21/321—After treatment
- H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
- H01L21/32131—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer by physical means only
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
- H01L21/76883—Post-treatment or after-treatment of the conductive material
Definitions
- the present invention relates to a coating surface treatment method and a coating surface treatment apparatus.
- This application claims priority based on Japanese Patent Application No. 2009-170576 filed in Japan on July 21, 2009, the contents of which are incorporated herein by reference.
- Sputtering plays an important role as a method for forming a thin film wiring in a multilayer wiring technology indispensable for manufacturing a semiconductor element such as an LSI.
- a target made of a wiring material is provided at a predetermined interval so as to face a substrate that is a film formation target.
- the ratio of the depth to the entrance diameter of the micropore or microgroove is called the aspect ratio, but the film thickness of the inner bottom surface of the microhole or microgroove having a high aspect ratio is smaller than the film thickness of the substrate surface.
- the bottom coverage ratio of the film thickness on the inner bottom surface of the micropores or microgrooves to the film thickness on the substrate surface
- the side coverage ratio of the film thickness of the inner wall surface of the micropore or microgroove to the film thickness of the substrate surface
- One of the causes of these tendencies is that sputtered particles made of a wiring material knocked out of the target collide with the sputtering gas in the vacuum chamber and scatter while reaching the substrate surface, and the sputtered particles are scattered on the substrate. It is mentioned that the rate of incidence perpendicular to the angle decreases. Sputtered particles incident on the substrate from an oblique direction do not reach the inside of the high aspect ratio micropores or microgrooves, but are deposited at the opening ends of the micropores or microgrooves.
- Patent Document 1 A method of suppressing the degree is disclosed (Patent Document 1).
- the inner wall surface on the inner side (center side of the substrate) of the fine hole or groove provided in the substrate is shaded.
- the micropores or microgrooves provided on the edge side of the base are particularly large in the shadow area compared to the micropores or microgrooves provided in the center of the base, so that the surface of the coating has minute irregularities. The degree of occurrence will also increase.
- aspects according to the present invention provide a coating surface treatment method and coating surface treatment apparatus capable of flattening fine irregularities on the surface of a coating film formed on the inner wall surface of fine holes or fine grooves formed in a substrate. For the purpose.
- the coating surface treatment method uses a substrate in which fine holes or grooves are formed on the film formation surface, and forms a coating on the entire surface of the substrate including the inner wall surface and the inner bottom surface of the holes or grooves. And planarizing the coating formed on the inner wall surface of the hole or groove by performing plasma treatment on the surface of the coating.
- the film surface treatment method is characterized in that the film is formed on the substrate by sputtering.
- the coating surface treatment method uses a vacuum chamber in which a target is disposed so as to face the substrate in the sputtering method, and when the coating is formed on the substrate, the first plasma is applied to the target.
- the second plasma is generated at a position close to the substrate when the film is generated at a close position and the film is flattened.
- the coating surface treatment method is characterized in that the second plasma is distributed so that the plasma treatment is performed on the entire area of the coating film formed on the substrate.
- the DC power applied to the target is represented as Cp (A), and when the coating is flattened, the DC power applied to the target is Cp (B), when forming the film on the substrate, the gas pressure when generating the plasma is expressed as P (A), and when generating the plasma when flattening the film
- the gas pressure is expressed as P (B)
- the high-frequency power applied to the substrate is expressed as Sp (A), and is applied to the substrate when the coating is flattened.
- the high frequency power to be expressed is represented by Sp (B)
- the following formula (1), formula (2), and formula (3) are satisfied.
- a film surface treatment apparatus is characterized by using the above film surface treatment method.
- the film surface treatment method and the film surface treatment apparatus according to the aspect of the present invention can flatten the film surface formed on the inner wall surface of the fine hole or groove of the substrate.
- channel Sectional drawing of the coated fine groove
- the film surface treatment method of the present embodiment uses a substrate in which fine holes or grooves are formed on the film formation surface, and forms a film on the entire surface of the substrate including the inner wall surface and inner bottom surface of the hole or groove.
- a known film forming method can be applied, for example, a PVD method such as sputtering or vapor deposition, or vapor phase growth such as thermal CVD or plasma CVD. Laws can be applied.
- the sputtering method or the plasma CVD method is preferable because the process A and the process B described later can be performed in the same film forming apparatus.
- the film formation method of the process A is a sputtering method
- the film formed on the inner wall surface of the fine hole or groove formed in the substrate is finer than the case where the CVD method is used. It is more preferable because unevenness is likely to occur, and the effect of flattening the surface of the coating film is obtained in the step B described later.
- the material of the substrate used in the step A is not particularly limited as long as it can withstand the film formation method and can withstand plasma treatment in the later-described step B.
- a substrate of a semiconductor element is preferable. is there.
- the substrate material of the semiconductor element include silicon and silicon oxide (SiO 2 ).
- a coating such as a metal barrier layer may be formed on the substrate in advance.
- the size of the minute hole or groove may be the size of a minute hole (via) or minute groove (trench) formed in a general semiconductor substrate. That is, the opening diameter of the fine holes or fine grooves is preferably 1.0 nm or more and 10 ⁇ m or less, more preferably 1.0 nm or more and 1.0 ⁇ m or less, and further preferably 1.0 nm or more and 0.5 ⁇ m or less. The effect of this embodiment is more fully acquired as it is the said range.
- the material of the film formed on the substrate materials used in the known PVD method and CVD method can be applied, and examples thereof include wiring materials used for wiring of semiconductor elements. More specifically, gold (Au), silver (Ag), copper (Cu), palladium (Pd), nickel (Ni), aluminum (Al), chromium (Cr), tantalum (Ta), silicon (Si) Among these, Au, Ag, Cu, and Pd are preferable, and Cu is more preferable because the effect of the present embodiment is excellent.
- the film forming method is a sputtering method
- the target material may be the same as the above-described film material.
- the film thickness of the film formed on the inner wall surface of the fine hole or groove is not particularly limited, and may be a film thickness of 1.0 nm to 1.0 ⁇ m, for example.
- the size of the minute unevenness that can be formed on the surface of the film formed with a film thickness in this range can be about 0.5 to 3 times the film thickness.
- a film forming apparatus that can be used to form a coating film on a substrate in which fine holes or grooves are formed on the film formation surface in the step A
- a cathode electrode 4 is fixed to the ceiling of the vacuum chamber 10 of the sputtering apparatus 1, and a target 5 is disposed on the surface thereof.
- a DC power supply 9 for applying a negative voltage is connected to the cathode electrode 4.
- a magnetic circuit 8 made of a permanent magnet is provided at the back surface position of the cathode electrode 4 outside the vacuum chamber 10, and the magnetic flux formed by the magnetic circuit 8 penetrates the cathode electrode 4 and the target 5, and reaches the surface of the target 5.
- a leakage magnetic field is formed. When sputtering is performed, electrons are trapped in the leakage magnetic field, and the plasma is densified.
- the target 5 may be a target made of a known material used for sputtering, and the material is not particularly limited, but is a copper target made of copper because the effect of the present embodiment can be obtained more sufficiently. It is preferable.
- a substrate electrode 6 is provided on the bottom surface of the vacuum chamber 10, and a substrate 7 is disposed on the surface of the substrate electrode 6 so as to face the target 5 substantially in parallel.
- the substrate electrode 6 is connected to a high frequency power source 13 for applying a high frequency bias power.
- the base electrode 6 is provided with a heater 11 electrically insulated by an insulating portion 11a, and the temperature of the base 7 can be adjusted to -50 to 600 ° C.
- the vacuum chamber 10 is provided with a gas inlet 2 and a vacuum exhaust 3.
- a gas cylinder such as an inert gas is connected to the gas introduction port 2, and a vacuum pump is connected to the vacuum exhaust port 3 (the gas cylinder and the vacuum pump are not shown).
- a 10 nm-thickness film is formed on the entire surface of the substrate on which the film is formed on a substrate on which fine holes or fine grooves having an opening diameter of 50 nm are formed. Can be formed. At that time, a plurality of minute irregularities having a size of about 5 nm can be generated particularly on the inner side of the film formed on the inner wall surface of the minute hole or minute groove. The size and the generation area of such minute unevenness can vary depending on the film forming conditions in the sputtering apparatus.
- the film formation conditions are as follows because a film suitable for the film surface treatment method of the present embodiment can be efficiently formed. Is preferred.
- the DC power (cathode power) applied to the target 5 is preferably 10 kW to 50 kW, more preferably 10 kW to 35 kW, and even more preferably 10 kW to 20 kW.
- the gas pressure (pressure in the vacuum chamber 10) when generating the plasma is preferably 0.001 Pa to 0.5 Pa, more preferably 0.01 Pa to 0.25 Pa, and 0.01 Pa to 0.1 Pa. Is more preferable.
- the high frequency power (stage high frequency power) of the high frequency power supply 13 applied to the substrate 7 is preferably 0 W or more and 100 W or less, more preferably 30 W or more and 80 W or less, and further preferably 40 W or more and 60 W or less.
- the frequency of the high-frequency power source 13 applied to the substrate 7 is preferably 1.0 MHz or more and 13.56 MHz or less because a coating suitable for the coating surface treatment method of the present embodiment can be efficiently formed.
- a preferable combination of each range of the cathode power, the pressure in the vacuum chamber 10 and the high frequency power of the stage is that the cathode power is in a range of 10 kW to 50 kW, and the pressure in the vacuum chamber 10 is 0.001 Pa.
- the range is 0.5 Pa or less and the stage high frequency power is 0 W or more and 100 W or less.
- a more preferable combination of the ranges of the cathode power, the pressure in the vacuum chamber 10 and the high frequency power of the stage is that the cathode power is in the range of 10 kW to 35 kW, and the pressure in the vacuum chamber 10 is 0.
- the range is from 01 Pa to 0.25 Pa, and the stage high-frequency power is from 30 W to 80 W.
- a more preferable combination of the ranges of the cathode power, the pressure in the vacuum chamber 10 and the high frequency power of the stage is that the cathode power is in the range of 10 kW to 20 kW, and the pressure in the vacuum chamber 10 is 0.
- the range is from 01 Pa to 0.1 Pa, and the stage high-frequency power is from 40 W to 60 W.
- a film suitable for the film surface treatment method of the present embodiment can be formed more efficiently.
- step B of the coating surface treatment method of the present embodiment as a method of performing plasma processing on the surface of the coating film formed in step A, plasma generation is performed in the vicinity of the substrate, thereby reducing the thickness of the coating film. Any method can be used as long as the surface of the coating is brought close to the surface of the coating while being suppressed, and the fine irregularities generated on the coating formed on the inner wall surface of the fine holes or grooves of the substrate are flattened. . It is preferable that the film formation method in the step A is a sputtering method or a CVD method because the step B can be performed in the same film formation apparatus following the step A.
- the plasma used in the step B is generated by ionizing an inert gas in a vacuum chamber equipped with an anode and a cathode.
- a sputtering apparatus 1 shown in FIG. 1 can be used as an apparatus provided with such a vacuum chamber.
- the target 5 is disposed in the vacuum chamber 10 so as to face the base body 7 substantially in parallel.
- An intermediate region between the substrate 7 and the target 5 is indicated by a dotted line L in FIG.
- the first plasma used in the step A is generated on the target 5 side when viewed from the intermediate region
- the second plasma used in the step B is viewed from the intermediate region.
- the first plasma can easily sputter the target 5. Since the sputtering efficiency in the process A is increased, the film can be efficiently formed on the entire film formation surface of the substrate 7.
- the second plasma is positioned relatively close to the substrate 7 and the plasma treatment on the substrate 7 can be performed more efficiently. it can.
- the space of the vacuum chamber 10 is equally divided into five when viewed from the base body 7 toward the target 5, and the first area, the second area, the third area, the fourth area, and the fifth area are sequentially arranged from the base body 7 side. This is called a region.
- the intermediate area is included in the third area.
- the first plasma is more preferably generated in the fourth region or 5, and more preferably in the fifth region.
- the second plasma is more preferably generated in the first region or 2 and more preferably in the second region from the viewpoint of increasing the planarization efficiency by the plasma treatment in the step B.
- the coating formed on the substrate 7 may be reduced depending on the plasma density and the time for which the plasma treatment is performed.
- the positions of the first plasma and the second plasma are specified in the region to which the center of each plasma belongs. Even if the plasma is distributed over a plurality of regions, the position of the plasma is specified in the region to which the center of the plasma belongs.
- the second plasma is generated on the substrate 7 side when viewed from the intermediate region, the effect of the present embodiment is excellent, so that the plasma treatment is performed on the entire region of the coating film formed on the substrate.
- the second plasma is distributed as applied.
- the range in which the second plasma is distributed is an extent to which the minute irregularities generated on the film formed on the inner wall surface of the minute hole or groove of the substrate 7 by the plasma treatment for a predetermined time can be flattened. Means the range in which the second plasma exists.
- the first plasma is generated on the target 5 side when viewed from the intermediate region and the second plasma is generated on the substrate 7 side when viewed from the intermediate region as described above, this embodiment is implemented. Since the effect of the form is excellent, it is preferable to distribute the second plasma in a wider area than the first plasma.
- the range in which the first plasma is distributed means a range in which the first plasma exists at a plasma density at which the film can be formed on the substrate 7 by sputtering for a predetermined time.
- the plasma treatment condition is as follows. The following is preferable because the fine unevenness can be efficiently planarized by the surface treatment method.
- the direct current power (cathode power) applied to the target 5 is preferably 0 kW to 9 kW, more preferably 0 kW to 6 kW, and even more preferably 0 kW to 3 kW.
- the gas pressure (pressure in the vacuum chamber 10) when generating the second plasma is preferably 1.0 Pa or more and 18 Pa or less, more preferably 4.0 Pa or more and 15 Pa or less, and further preferably 8.0 Pa or more and 12 Pa or less.
- the high frequency power (stage high frequency power) of the high frequency power supply 13 applied to the substrate 7 is preferably 150 W or more and 650 W or less, more preferably 200 W or more and 500 W or less, and further preferably 250 W or more and 350 W or less.
- the frequency of the high-frequency power source 13 applied to the substrate 7 is preferably 1.0 MHz or more and 13.56 MHz or less because the minute unevenness can be efficiently planarized by the coating surface treatment method of the present embodiment.
- a preferable combination of each range of the cathode power, the pressure in the vacuum chamber 10 and the high frequency power of the stage is that the cathode power is in the range of 0 kW to 9 kW, and the pressure in the vacuum chamber 10 is 1.0 Pa.
- the range is 18 Pa or less and the stage high frequency power is 150 W or more and 650 W or less.
- a more preferable combination of each range of the cathode power, the pressure in the vacuum chamber 10 and the high frequency power of the stage is that the cathode power is in a range of 0 kW to 6 kW, and the pressure in the vacuum chamber 10 is 4.
- the range is from 0 Pa to 15 Pa, and the stage high-frequency power is from 200 W to 500 W.
- a more preferable combination of the ranges of the cathode power, the pressure in the vacuum chamber 10 and the high frequency power of the stage is that the cathode power is in the range of 0 kW to 3 kW, and the pressure in the vacuum chamber 10 is 8.
- the range is from 0 Pa to 12 Pa, and the stage high-frequency power is from 250 W to 350 W.
- the second plasma having a plasma density suitable for the coating surface treatment method of the present embodiment can be generated relatively close to the substrate 7, so that the fine unevenness can be flattened. This can be done more efficiently.
- the effect of this embodiment is further improved. Therefore, the following is more preferable.
- the DC power Cp applied to the target in the steps A and B is expressed as Cp (A) and Cp (B), and the gas pressure P when the plasma is generated in the steps A and B is expressed as P (A), P
- the high-frequency power Sp applied to the substrate in the steps A and B is expressed as Sp (A) and Sp (B)
- the following expressions (1), (2), and (3) ) Is more preferable.
- the direct current power (cathode power) applied to the target 5 is made smaller in the process B than in the process A, and the gas pressure (pressure in the vacuum chamber 10) when generating the plasma is set in the process.
- the step B is higher than the step A, and the high-frequency power (stage high-frequency power) applied to the substrate 7 is higher in the step B than the step A.
- a preferred combination of the ranges of the cathode power, the pressure in the vacuum chamber 10 and the high-frequency power of the stage in the step A, the cathode power in the step B, and the pressure in the vacuum chamber 10 And combinations with preferred combinations of the respective ranges of the stage high frequency power. Further, a more preferable combination of the ranges of the cathode power in the step A, the pressure in the vacuum chamber 10, and the stage high-frequency power, the cathode power in the step B, the pressure in the vacuum chamber 10, and A combination with a more preferable combination of each range of the stage high frequency power is more preferable.
- the second plasma having a plasma density suitable for the coating surface treatment method of the present embodiment can be generated relatively close to the substrate 7, so that the fine unevenness can be flattened. It can be performed even more efficiently.
- the substrate temperature in the plasma treatment in the step B is preferably ⁇ 50 ° C. or more and 550 ° C. or less, more preferably 25 ° C. or more and 400 ° C. or less, and more preferably 25 ° C. or more and 300 ° C. or less because the effect of this embodiment is excellent. Further preferred.
- a cooling device may be provided on the base holder. Within the above substrate temperature range, the substrate temperature can be easily adjusted, and the film formed on the inner wall surface of the fine hole or groove can be efficiently planarized by plasma treatment.
- the time of the plasma treatment in the step B is preferably 3.0 seconds or more and 60 seconds or less, and preferably 3.0 seconds or more and 40 seconds or less, although it depends on the degree of minute unevenness of the coating on the inner wall surface. More preferably, it is more preferably performed in 3.0 seconds or more and 20 seconds or less. If it is not less than the above lower limit value, planarization can be sufficiently performed, and if it is not more than the above upper limit value, planarization can be performed while suppressing a decrease in the film thickness.
- an inert gas used in a known sputtering method can be applied, and examples thereof include argon (Ar), krypton (Kr), and helium (He).
- Ar argon
- Kr krypton
- He helium
- Ar or Kr is preferable, and Ar is more preferable because the coating film can be efficiently planarized.
- the sputtering apparatus 1 shown in FIG. 1 has means ⁇ for controlling the DC power applied to the target 5 connected to the DC power source 9 to be smaller in the process B than in the process A.
- the means ⁇ for example, an external device for controlling the DC power supply 9 can be appropriately installed.
- the sputtering apparatus 1 shown in FIG. 1 has means ⁇ for controlling the pressure of the vacuum chamber 10 when generating the plasma to be higher in the process B than in the process A.
- an external device for controlling a vacuum pump connected to the vacuum exhaust port 3 may be appropriately installed.
- the sputtering apparatus 1 shown in FIG. 1 has means ⁇ for controlling the high-frequency power applied to the substrate 7 by the substrate electrode 6 to be larger in the process B than in the process A.
- the means ⁇ for example, an external device for controlling the high-frequency power source 13 connected to the base electrode 6 may be appropriately installed.
- Step A and Step B were performed using the sputtering apparatus 1 shown in FIG.
- the target 5 was a copper target made of copper.
- a film 22 made of copper is formed on the silicon wafer 21 having a plurality of fine grooves (trench) having an opening diameter of 50 nm and an aspect ratio of 3.7 formed on the film formation surface by using the sputtering apparatus 1 shown in FIG. Filmed (see FIG. 2).
- a coating 23 having a thickness of about 8 nm was formed on the inner wall surface of the fine groove, and in particular, a plurality of irregularities having a size of about 6 nm were formed on the coating 23 on the inner wall surface on the inner side (center side of the silicon wafer 21).
- the sputtering conditions in this step A are the DC power (cathode power) applied to the target 5, the gas pressure when generating plasma (pressure in the vacuum chamber 10), and the high frequency power (stage high frequency) applied to the silicon wafer 21. Power) and processing time are shown in Table 1.
- the frequency of the high-frequency power source 13 is 1.0 MHz to 13.56 MHz, and Ar is used as an inert gas.
- the first plasma generated under these conditions was generated in the fifth region on the copper target 5 side as seen from the intermediate region represented by the dotted line L of the vacuum chamber 10.
- the plasma generation conditions in this step B are DC power (cathode power) applied to the copper target 5, gas pressure when generating plasma (pressure in the vacuum chamber 10), and high frequency power (stage) applied to the silicon wafer 21.
- Table 2 shows the high frequency power) and the processing time.
- the frequency of the high-frequency power source 13 is 1.0 MHz to 13.56 MHz, and Ar is used as an inert gas.
- the second plasma generated under these conditions was generated in the second region on the silicon wafer 21 side as viewed from the intermediate region represented by the dotted line L of the vacuum chamber 10. In addition, the second plasma was distributed over a wider area than the first plasma.
- Example 1 By the above plasma treatment, in Example 1, the coating 23 before the plasma treatment became a coating 24 that was smoothly flattened by the plasma treatment (see FIG. 3A). In Example 2, the film 23 before the plasma treatment became a film 25 flattened by the plasma treatment (see FIG. 3B), and the size of the unevenness was reduced to half or less. In Example 3, the film 23 before the plasma treatment was slightly flattened by the plasma treatment, but the effect was limited, and the size of the unevenness was hardly changed before and after the plasma treatment (FIG. 3C).
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Abstract
Description
本願は、2009年7月21日に、日本に出願された特願2009-170576号に基づき優先権を主張し、その内容をここに援用する。
スパッタ法で用いられる一般的なスパッタ装置の真空槽内には、配線材料からなるターゲットが成膜対象である基体に対向するように所定の間隔で離れて設けられている。真空槽外部のターゲット裏面部に設けられた永久磁石等を用いた磁気回路によってターゲット表面に磁界を形成させ、ターゲットに負電圧を印加することにより真空槽内に導入したアルゴン(Ar)等のスパッタリングガスのプラズマをターゲット近辺に発生させ、電離したスパッタリングガスイオンをターゲットに入射させ、ターゲット表面から配線材料を飛び出させて、基体表面に付着させることにより配線材料からなる被膜が成膜される。
本発明に係る態様は、基体に形成された微細な孔又は微細な溝の内壁面に成膜された被膜の表面の微小な凹凸を平坦化できる被膜表面処理方法及び被膜表面処理装置を提供することを目的とする。
上記被膜表面処理方法は、スパッタ法によって前記基体に前記被膜を形成することを特徴とする。
上記被膜表面処理方法は、前記スパッタ法において、前記基体に対向するようにターゲットが配置されている真空槽を用い、前記基体に前記被膜を形成する際には、第1のプラズマを該ターゲットに近い位置に発生させ、前記被膜を平坦化する際には、第2のプラズマを該基体に近い位置に発生させることを特徴とする。
上記被膜表面処理方法は、前記基体に成膜した前記被膜の全域に対して前記プラズマ処理を施すように、前記第2のプラズマを分布させることを特徴とする。
上記被膜表面処理方法は、前記基体に前記被膜を形成するときに、前記ターゲットに印加する直流電力をCp(A)と表し、前記被膜を平坦化するときに、前記ターゲットに印加する直流電力をCp(B)と表し、前記基体に前記被膜を形成するときに、前記プラズマを発生させる際のガス圧をP(A)と表し、前記被膜を平坦化するときに、前記プラズマを発生させる際のガス圧をP(B)と表し、前記基体に前記被膜を形成するときに、前記基体に印加する高周波電力をSp(A)と表し、前記被膜を平坦化するときに、前記基体に印加する高周波電力をSp(B)と表す場合、以下の式(1)、式(2)、及び式(3)を満たすことを特徴とする。
P(A)< P(B) ・・・(2)
Sp(A)<Sp(B) ・・・(3)
本実施形態の被膜表面処理方法は、被成膜面に微細な孔又は溝が形成された基体を用い、該孔又は溝の内壁面及び内底面を含む前記基体の全面に被膜を形成する工程Aと、前記被膜の表面に対してプラズマ処理を施すことにより、前記孔又は溝の内壁面の被膜を平坦化する工程Bと、を有する。
前記工程Aにおいて、基体の全面に被膜を成膜する方法としては、公知の成膜方法を適用することができ、例えばスパッタ法や蒸着等のPVD法、熱CVDやプラズマCVD等の気相成長法などが適用できる。これらの成膜方法のうち、スパッタ法又はプラズマCVD法であると、前記工程Aと後述の工程Bとを同じ成膜装置内で進めることができるので好ましい。また、前記工程Aの成膜方法がスパッタ法である方が、CVD法を用いた場合よりも基体に形成された微細な孔又は溝の内壁面に成膜された被膜の特にインナー側に微小な凹凸が生じやすく、後述の工程Bにおいてその被膜表面を平坦化する効果がより得られるので、より好ましい。
成膜方法がスパッタ法である場合は、ターゲットの材料を上述の被膜の材料と同じものにすればよい。
真空槽10外のカソード電極4の裏面位置には、永久磁石からなる磁気回路8が設けられており、その磁気回路8が形成する磁束がカソード電極4とターゲット5を貫通し、ターゲット5表面に漏洩磁界が形成されるように構成されている。スパッタリングを行う際にはその漏洩磁界に電子がトラップされ、プラズマが高密度化する。
カソード電極4に負電圧を印加することにより放電が開始され、真空槽内10に導入された不活性ガスのプラズマが発生し、ターゲット5からスパッタリング粒子が叩き出されて、基体7の表面へ到達して被膜を形成する。
前記ターゲット5としては、スパッタに用いられる公知の材質からなるターゲットであればよく、その材質は特に制限されないが、本実施形態の効果がより十分に得られることから、銅からなる銅ターゲットであることが好ましい。
基体電極6は高周波バイアス電力を印加する高周波電源13に接続されている。また、基体電極6には絶縁部11aによって電気的に絶縁されたヒーター11が設けられており、基体7の温度を-50~600℃に調節することができる。
前記ターゲット5に印加する直流電力(カソードパワー)は、10kW以上50kW以下が好ましく、10kW以上35kW以下がより好ましく、10kW以上20kW以下がさらに好ましい。
前記プラズマを発生させる際のガス圧(真空槽10内の圧力)は、0.001Pa以上0.5Pa以下が好ましく、0.01Pa以上0.25Pa以下がより好ましく、0.01Pa以上0.1Pa以下がさらに好ましい。
前記基体7に印加する高周波電源13の高周波電力(ステージ高周波パワー)は、0W以上100W以下が好ましく、30W以上80W以下がより好ましく、40W以上60W以下がさらに好ましい。
前記基体7に印加する高周波電源13の周波数としては、本実施形態の被膜表面処理方法に適した被膜を効率良く形成できることから、1.0MHz以上13.56MHz以下が好ましい。
前記カソードパワー、前記真空槽10内の圧力、及び前記ステージ高周波パワーのそれぞれの範囲のより好ましい組み合わせは、前記カソードパワーが10kW以上35kW以下の範囲であり、前記真空槽10内の圧力が0.01Pa以上0.25Pa以下の範囲であり、且つ前記ステージ高周波パワーが30W以上80W以下の範囲である。
前記カソードパワー、前記真空槽10内の圧力、及び前記ステージ高周波パワーのそれぞれの範囲のさらに好ましい組み合わせは、前記カソードパワーが10kW以上20kW以下の範囲であり、前記真空槽10内の圧力が0.01Pa以上0.1Pa以下の範囲であり、且つ前記ステージ高周波パワーが40W以上60W以下の範囲である。
上記組み合わせであると、本実施形態の被膜表面処理方法に適した被膜を一層効率良く形成することができる。
本実施形態の被膜表面処理方法における工程Bにおいて、前記工程Aで成膜した被膜の表面に対してプラズマ処理を施す方法としては、基体近傍でプラズマを発生させることによって、該被膜の膜減りを抑制しながら該被膜の表面にプラズマを接近させて表面処理を行い、該基体の微細な孔又は溝の内壁面に成膜された被膜に生じた微小な凹凸を平坦化できる方法であればよい。
前記工程Aにおける成膜方法がスパッタ法又はCVD法であると、前記工程Aに続いて前記工程Bを同じ成膜装置内で進めることができるので好ましい。
本実施形態の被膜表面処理方法では、前記工程Aで用いる第1のプラズマは該中間域から見てターゲット5側に発生させ、且つ、前記工程Bで用いる第2のプラズマは該中間域から見て基体7側に発生させることが好ましい。
前記第1のプラズマを該中間域から見てターゲット5側に発生させることにより、前記第2のプラズマが基体7の比較的近傍に位置し、前記第1のプラズマがターゲット5をスパッタし易くなり、工程Aにおけるスパッタリングの効率が高まるので、基体7の被成膜面全面に効率良く被膜を形成することができる。
前記第2のプラズマを該中間域から見て基体7側に発生させることにより、前記第2のプラズマが基体7の比較的近傍に位置し、基体7に対するプラズマ処理をより効率的に施すことができる。
前記第1のプラズマは、工程Aにおけるスパッタリングの効率を高める観点から、該第4領域又は5に発生させることがより好ましく、該第5領域に発生させることがさらに好ましい。
前記第2のプラズマは、工程Bにおけるプラズマ処理による前記平坦化の効率を高める観点から、該第1領域又は2に発生させることがより好ましく、該第2領域に発生させることがさらに好ましい。該第1領域に前記第2のプラズマを発生させた場合、プラズマ密度やプラズマ処理を施す時間にもよるが、基体7に成膜した被覆が膜減りする恐れがある。
これらの第1のプラズマ及び第2のプラズマの位置は、それぞれのプラズマの中心が属する領域で特定される。仮に前記プラズマが複数の領域にまたがって分布する場合でもそのプラズマの中心が属する領域でそのプラズマの位置が特定される。
ここで、前記第2のプラズマが分布する範囲とは、所定時間のプラズマ処理によって基体7の微細な孔又は溝の内壁面に成膜された被膜に生じた前記微小な凹凸を平坦化できる程度のプラズマ密度でその第2のプラズマが存在する範囲を意味する。
前記第1のプラズマが分布する範囲とは、所定時間のスパッタリングによって基体7に前記被膜を成膜できる程度のプラズマ密度でその第1のプラズマが存在する範囲を意味する。
前記ターゲット5に印加する直流電力(カソードパワー)は、0kW以上9kW以下が好ましく、0kW以上6kW以下がより好ましく、0kW以上3kW以下がさらに好ましい。
前記第2のプラズマを発生させる際のガス圧(真空槽10の圧力)は、1.0Pa以上18Pa以下が好ましく、4.0Pa以上15Pa以下がより好ましく、8.0Pa以上12Pa以下がさらに好ましい。
前記基体7に印加する高周波電源13の高周波電力(ステージ高周波パワー)は、150W以上650W以下が好ましく、200W以上500W以下がより好ましく、250W以上350W以下がさらに好ましい。
前記基体7に印加する高周波電源13の周波数としては、本実施形態の被膜表面処理方法による前記微小な凹凸の平坦化を効率良く行えることから、1.0MHz以上13.56MHz以下が好ましい。
前記カソードパワー、前記真空槽10内の圧力、及び前記ステージ高周波パワーのそれぞれの範囲のより好ましい組み合わせは、前記カソードパワーが0kW以上6kW以下の範囲であり、前記真空槽10内の圧力が4.0Pa以上15Pa以下の範囲であり、且つ前記ステージ高周波パワーが200W以上500W以下の範囲である。
前記カソードパワー、前記真空槽10内の圧力、及び前記ステージ高周波パワーのそれぞれの範囲のさらに好ましい組み合わせは、前記カソードパワーが0kW以上3kW以下の範囲であり、前記真空槽10内の圧力が8.0Pa以上12Pa以下の範囲であり、且つ前記ステージ高周波パワーが250W以上350W以下の範囲である。
上記組合わせであると、本実施形態の被膜表面処理方法に適したプラズマ密度を有する第2のプラズマを、基体7の比較的近傍に発生させることができるので、前記微小な凹凸の平坦化を一層効率良く行うことができる。
P(A)< P(B) ・・・(2)
Sp(A)<Sp(B) ・・・(3)
また、前記工程Aにおける前記カソードパワー、前記真空槽10内の圧力、及び前記ステージ高周波パワーのそれぞれの範囲のより好ましい組み合わせと、前記工程Bにおける前記カソードパワー、前記真空槽10内の圧力、及び前記ステージ高周波パワーのそれぞれの範囲のより好ましい組み合わせとの組み合せがより好ましい。
さらに、前記工程Aにおける前記カソードパワー、前記真空槽10内の圧力、及び前記ステージ高周波パワーのそれぞれの範囲のさらに好ましい組み合わせと、前記工程Bにおける前記カソードパワー、前記真空槽10内の圧力、及び前記ステージ高周波パワーのそれぞれの範囲のさらに好ましい組み合わせとの組み合せがさらに好ましい。
上記組合わせであると、本実施形態の被膜表面処理方法に適したプラズマ密度を有する第2のプラズマを、基体7の比較的近傍に発生させることができるので、前記微小な凹凸の平坦化をより一層効率良く行うことができる。
上記下限値以上であると平坦化を十分に行うことができ、上記上限値以下であると、被膜の膜減りを抑制しつつ平坦化を行うことができる。
図1に示すスパッタ装置1では、直流電源9に接続されたターゲット5に印加する直流電力を前記工程Aに比べて前記工程Bの方でより小さくなるように制御する手段αを有する。該手段αとして、例えば前記直流電源9を制御する外部装置を適宜設置することが挙げられる。
また、図1に示すスパッタ装置1では、前記プラズマを発生させる際の真空槽10の圧力を前記工程Aに比べて前記工程Bの方でより高くなるように制御する手段βを有する。該手段βとして、例えば真空排気口3に接続された真空ポンプを制御する外部装置を適宜設置することが挙げられる。
さらに、図1に示すスパッタ装置1では、基体電極6により前記基体7に印加する高周波電力を前記工程Aに比べて前記工程Bの方でより大きくなるように制御する手段γを有する。該手段γとして、例えば前記基体電極6に接続された高周波電源13を制御する外部装置を適宜設置することが挙げられる。
実施例1~3では、図1に示すスパッタ装置1を用いて工程Aおよび工程Bを行った。なお、前記ターゲット5は、銅からなる銅ターゲットを用いた。
つぎに、プラズマ発生条件を表2に示すように設定し、前記シリコンウエハ21に成膜された銅からなる被膜22の表面に対して、それぞれ異なるプラズマ処理を施して、微細溝の内壁面の被膜23を平坦化した。その結果を表2に併記し、図3A~3Cに示す。
Claims (6)
- 被膜表面処理方法であって、
被成膜面に微細な孔又は溝が形成された基体を用い、該孔又は溝の内壁面及び内底面を含む前記基体の全面に被膜を形成することと、
前記被膜の表面に対してプラズマ処理を施すことにより、前記孔又は溝の前記内壁面に形成された前記被膜を平坦化することと、
を有することを特徴とする被膜表面処理方法。 - スパッタ法によって前記基体に前記被膜を形成することを特徴とする請求項1に記載の被膜表面処理方法。
- 前記スパッタ法において、前記基体に対向するようにターゲットが配置されている真空槽を用い、
前記基体に前記被膜を形成する際には、第1のプラズマを該ターゲットに近い位置に発生させ、
前記被膜を平坦化する際には、第2のプラズマを該基体に近い位置に発生させることを特徴とする請求項2に記載の被膜表面処理方法。 - 前記基体に成膜した前記被膜の全域に対して前記プラズマ処理を施すように、前記第2のプラズマを分布させることを特徴とする請求項3に記載の被膜表面処理方法。
- 前記基体に前記被膜を形成するときに、
前記ターゲットに印加する直流電力をCp(A)と表し、
前記被膜を平坦化するときに、
前記ターゲットに印加する直流電力をCp(B)と表し、
前記基体に前記被膜を形成するときに、
前記プラズマを発生させる際のガス圧をP(A)と表し、
前記被膜を平坦化するときに、
前記プラズマを発生させる際のガス圧をP(B)と表し、
前記基体に前記被膜を形成するときに、
前記基体に印加する高周波電力をSp(A)と表し、
前記被膜を平坦化するときに、
前記基体に印加する高周波電力をSp(B)と表す場合、
以下の式(1)、式(2)、及び式(3)を満たすことを特徴とする請求項2乃至請求項4のいずれか一項に記載の被膜表面処理方法。
Cp(A)>Cp(B) ・・・(1)
P(A)< P(B) ・・・(2)
Sp(A)<Sp(B) ・・・(3) - 被膜表面処理装置であって、請求項1乃至請求項5のいずれか一項に記載の被膜表面処理方法を用いることを特徴とする被膜表面処理装置。
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CN201080022769.3A CN102449741B (zh) | 2009-07-21 | 2010-07-21 | 覆膜表面处理方法 |
JP2011523668A JP5335916B2 (ja) | 2009-07-21 | 2010-07-21 | 被膜表面処理方法 |
US13/386,264 US20120121818A1 (en) | 2009-07-21 | 2010-07-21 | Coating surface processing method and coating surface processing apparatus |
KR1020117030098A KR101318240B1 (ko) | 2009-07-21 | 2010-07-21 | 피막 표면 처리 방법 및 피막 표면 처리 장치 |
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JP (1) | JP5335916B2 (ja) |
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020027885A (ja) * | 2018-08-13 | 2020-02-20 | 富士ゼロックス株式会社 | 半導体素子の製造方法 |
JP2023516865A (ja) * | 2020-06-16 | 2023-04-21 | アプライド マテリアルズ インコーポレイテッド | パルスバイアスを使用したオーバーハングの低減 |
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CN111235539B (zh) * | 2020-03-10 | 2021-04-20 | 摩科斯新材料科技(苏州)有限公司 | 一种小孔内壁薄膜沉积方法及装置 |
Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07273046A (ja) * | 1994-03-31 | 1995-10-20 | Sony Corp | 高融点金属層のcvd方法およびそのcvd装置 |
JPH10116831A (ja) * | 1996-10-11 | 1998-05-06 | Sharp Corp | 銅のインターフェース導電性を向上させる方法およびその方法を用いて形成された銅導電体インターフェース |
JPH1140668A (ja) * | 1997-07-18 | 1999-02-12 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2004063556A (ja) * | 2002-07-25 | 2004-02-26 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2005109444A (ja) * | 2003-09-08 | 2005-04-21 | Tokyo Electron Ltd | プラズマエッチング方法 |
JP2007311584A (ja) * | 2006-05-19 | 2007-11-29 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2009176886A (ja) * | 2008-01-23 | 2009-08-06 | Nec Electronics Corp | 半導体装置の製造方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH06302543A (ja) * | 1993-04-09 | 1994-10-28 | Nippon Steel Corp | 半導体装置の製造方法 |
KR0144956B1 (ko) * | 1994-06-10 | 1998-08-17 | 김광호 | 반도체 장치의 배선 구조 및 그 형성방법 |
US6593241B1 (en) * | 1998-05-11 | 2003-07-15 | Applied Materials Inc. | Method of planarizing a semiconductor device using a high density plasma system |
US6124203A (en) * | 1998-12-07 | 2000-09-26 | Advanced Micro Devices, Inc. | Method for forming conformal barrier layers |
TW504756B (en) * | 2000-07-21 | 2002-10-01 | Motorola Inc | Post deposition sputtering |
US6448177B1 (en) * | 2001-03-27 | 2002-09-10 | Intle Corporation | Method of making a semiconductor device having a dual damascene interconnect spaced from a support structure |
CN100355058C (zh) * | 2001-05-04 | 2007-12-12 | 东京毅力科创株式会社 | 具有连续沉积和蚀刻的电离pvd |
JP4589591B2 (ja) * | 2002-02-05 | 2010-12-01 | キヤノンアネルバ株式会社 | 金属膜作製方法及び金属膜作製装置 |
JP2008041977A (ja) * | 2006-08-08 | 2008-02-21 | Nec Electronics Corp | 半導体回路装置の製造方法 |
-
2010
- 2010-07-20 TW TW099124052A patent/TWI435386B/zh not_active IP Right Cessation
- 2010-07-21 CN CN201080022769.3A patent/CN102449741B/zh active Active
- 2010-07-21 US US13/386,264 patent/US20120121818A1/en not_active Abandoned
- 2010-07-21 KR KR1020117030098A patent/KR101318240B1/ko active IP Right Grant
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- 2010-07-21 JP JP2011523668A patent/JP5335916B2/ja not_active Expired - Fee Related
Patent Citations (7)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH07273046A (ja) * | 1994-03-31 | 1995-10-20 | Sony Corp | 高融点金属層のcvd方法およびそのcvd装置 |
JPH10116831A (ja) * | 1996-10-11 | 1998-05-06 | Sharp Corp | 銅のインターフェース導電性を向上させる方法およびその方法を用いて形成された銅導電体インターフェース |
JPH1140668A (ja) * | 1997-07-18 | 1999-02-12 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2004063556A (ja) * | 2002-07-25 | 2004-02-26 | Matsushita Electric Ind Co Ltd | 半導体装置の製造方法 |
JP2005109444A (ja) * | 2003-09-08 | 2005-04-21 | Tokyo Electron Ltd | プラズマエッチング方法 |
JP2007311584A (ja) * | 2006-05-19 | 2007-11-29 | Sanyo Electric Co Ltd | 半導体装置の製造方法 |
JP2009176886A (ja) * | 2008-01-23 | 2009-08-06 | Nec Electronics Corp | 半導体装置の製造方法 |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2020027885A (ja) * | 2018-08-13 | 2020-02-20 | 富士ゼロックス株式会社 | 半導体素子の製造方法 |
JP7183624B2 (ja) | 2018-08-13 | 2022-12-06 | 富士フイルムビジネスイノベーション株式会社 | 半導体素子の製造方法 |
JP2023516865A (ja) * | 2020-06-16 | 2023-04-21 | アプライド マテリアルズ インコーポレイテッド | パルスバイアスを使用したオーバーハングの低減 |
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JP5335916B2 (ja) | 2013-11-06 |
CN102449741B (zh) | 2014-07-23 |
TW201133617A (en) | 2011-10-01 |
US20120121818A1 (en) | 2012-05-17 |
CN102449741A (zh) | 2012-05-09 |
KR20120027030A (ko) | 2012-03-20 |
TWI435386B (zh) | 2014-04-21 |
KR101318240B1 (ko) | 2013-10-15 |
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