WO2010146850A1 - 不揮発性記憶装置及びその製造方法 - Google Patents
不揮発性記憶装置及びその製造方法 Download PDFInfo
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- WO2010146850A1 WO2010146850A1 PCT/JP2010/004002 JP2010004002W WO2010146850A1 WO 2010146850 A1 WO2010146850 A1 WO 2010146850A1 JP 2010004002 W JP2010004002 W JP 2010004002W WO 2010146850 A1 WO2010146850 A1 WO 2010146850A1
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
- H01L27/0688—Integrated circuits having a three-dimensional layout
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- H10B—ELECTRONIC MEMORY DEVICES
- H10B63/00—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices
- H10B63/30—Resistance change memory devices, e.g. resistive RAM [ReRAM] devices comprising selection components having three or more electrodes, e.g. transistors
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/011—Manufacture or treatment of multistable switching devices
- H10N70/061—Patterning of the switching material
- H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/20—Multistable switching devices, e.g. memristors
- H10N70/24—Multistable switching devices, e.g. memristors based on migration or redistribution of ionic species, e.g. anions, vacancies
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- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/821—Device geometry
- H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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- H—ELECTRICITY
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- H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
- H10N70/801—Constructional details of multistable switching devices
- H10N70/881—Switching materials
- H10N70/883—Oxides or nitrides
- H10N70/8833—Binary metal oxides, e.g. TaOx
Definitions
- the present invention relates to a variable resistance nonvolatile memory device and a manufacturing method thereof.
- a resistance change type nonvolatile material using a resistance change material made of a transition metal oxide whose oxygen number is insufficient (hereinafter referred to as oxygen-deficient type) as compared with a stoichiometric transition metal oxide.
- Storage devices have been proposed.
- Such a nonvolatile memory device includes an upper electrode layer, a lower electrode layer, and a resistance change layer sandwiched between the upper electrode layer and the lower electrode layer, and is provided between the upper electrode and the lower electrode.
- the resistance value of the variable resistance layer reversibly changes. Therefore, by associating information with this resistance value, the information can be stored without volatilization (see, for example, Patent Document 1, Patent Document 2, and Patent Document 3).
- Such a variable resistance nonvolatile memory device is expected to be finer, faster, and consume less power than a flash memory using a floating gate.
- variable resistance nonvolatile memory device there are problems with the individual film formation of the variable resistance film, the electrode, and the like, and the resist dimensions and resist shape after lithography, or the shape of each film after dry etching. Despite the absence, there was a problem that the initial resistance value varied.
- the present invention has been made to solve such a problem, and an object thereof is to provide a variable resistance nonvolatile memory device capable of suppressing variations in initial resistance values.
- iridium (Ir) is used as a material for an upper electrode or a lower electrode (hereinafter, sometimes collectively referred to as an electrode).
- platinum (Pt) is used as an electrode material.
- Such an electrode using iridium or platinum is usually formed by dry etching a thin film of iridium or platinum using a so-called hard mask (for example, a mask made of TiAlN) as a mask.
- a so-called resist mask made of a resist has a low selectivity to iridium or platinum thin film in dry etching
- a hard mask has a large selectivity to iridium or platinum thin film in dry etching.
- the hard mask is generally conductive.
- variable resistance layer oxygen in the oxygen-deficient transition metal oxide constituting the variable resistance layer contributes to the resistance change, so that the oxygen concentration in the variable resistance layer can be controlled.
- the resistance change operation on the one electrode side can be performed. It is necessary to form a high concentration oxygen layer.
- the variable resistance layer is configured by stacking two layers having different oxygen contents, and a layer having a high oxygen content is present on one electrode side. Since the resistance change operation on the one electrode side becomes possible, it is necessary to reliably form two layers having different oxygen contents in the manufacturing process.
- a resistance change layer is formed between the upper electrode layer and the lower electrode layer. Therefore, the original film of the resistance change layer and the original film of the lower electrode layer are etched in the process of forming the upper electrode layer, the resistance change layer, and the lower electrode layer by sequentially dry-etching each original film. During the etching, the electric charge of the etching plasma diffused from the upper electrode layer patterned in a predetermined shape flows through the resistance change layer (or its original film) to the original film side of the lower electrode layer (this The process will be described in detail through a comparative example in the embodiment of the present invention).
- the present invention has been made based on such knowledge.
- a method for manufacturing a nonvolatile memory device includes a top electrode layer, a bottom electrode layer, and a resistance change layer sandwiched between the top electrode layer and the bottom electrode layer.
- a step of depositing a lower electrode film on the substrate, a step of depositing a resistance change film on the lower electrode film, a step of depositing an upper electrode film on the resistance change film, and the upper electrode film Depositing a charge diffusion prevention mask film thereon, patterning the charge diffusion prevention mask film into a predetermined shape to form a charge diffusion prevention mask film comprising the charge diffusion prevention mask film, and the charge diffusion prevention mask Using the mask as a mask, dry etching the upper electrode film, the resistance change film, and the lower electrode film, thereby forming the upper electrode layer, the lower electrode layer, and the resistance change layer.
- the resistance change film is formed by laminating a first film containing an oxygen-deficient transition metal oxide and a second film containing an oxygen-deficient transition metal oxide having a higher oxygen content than the first film.
- at least one of the upper electrode film and the lower electrode film contains a simple substance or an alloy of a platinum group element, the charge diffusion prevention mask film is insulative, and an etching rate by the dry etching Is smaller than the upper electrode film and the lower electrode film.
- the “film” and the “layer” are only used for convenience, and there is no essential difference between them. If it is possible to distinguish the element of the non-volatile memory device from the original one finally processed into this element, the “film” and the “layer” may be unified into one or the other. Good.
- the insulating charge diffusion prevention mask is used as the upper electrode layer. Since it is formed as a mask above, the charge of the etching plasma can be suppressed by the insulating charge diffusion preventing layer on the upper electrode layer. As a result, it is possible to prevent the etching plasma charge from diffusing from the upper electrode layer to the resistance change layer, so that there is no disturbance in the profile of the oxygen concentration in the resistance change layer, and variations in the initial resistance value are suppressed.
- a nonvolatile memory device can be manufactured.
- the charge diffusion prevention mask film includes an insulating inorganic film made of an insulating inorganic material and a conductive metal film made of metal formed on the insulating inorganic film, and the charge diffusion prevention mask film
- the step of depositing may include a step of depositing the inorganic insulating film on the upper electrode film and a step of depositing the conductive metal film on the inorganic insulating film.
- the insulating inorganic material of the inorganic insulating film is one material selected from Ta 2 O 5 , SiN, and SiON or a combination of two or more materials.
- TaO x whose composition has a smaller oxygen number than Ta 2 O 5 can be used as a material of the resistance change layer.
- SiN and SiON can be used as a material for an interlayer insulating layer of a nonvolatile memory device. Therefore, with such a configuration, a nonvolatile memory device can be manufactured using a material normally used in the manufacturing process of the nonvolatile memory device without using a material dedicated to the charge diffusion prevention mask film.
- the charge diffusion prevention mask film is insulative and includes a single film whose etching rate by dry etching is smaller than that of the upper electrode film and the lower electrode film, and the step of depositing the charge diffusion prevention mask film includes The step of depositing the single film on the upper electrode film may be employed.
- single film means “one film”.
- the single film is preferably made of Ta 2 O 5 .
- the film made of Ta 2 O 5 is insulative, and the etching rate by dry etching can be made sufficiently smaller than that of a film made of a single element or an alloy of a platinum group element. Therefore, with such a configuration, a single film that is “insulating and has an etching rate by dry etching smaller than that of the upper electrode film and the lower electrode film” can be preferably configured.
- the platinum group element is platinum, iridium, or palladium.
- the charge diffusion preventing mask film and the resistance change film may be composed of the same element. According to this manufacturing method, the conditions for etching the charge diffusion prevention mask film and the conditions for etching the resistance change film can be made the same, and the etching can be easily performed. Furthermore, since the charge diffusion preventing film and the resistance change film can be deposited using the same device, the device can be manufactured at a lower cost than a conventional nonvolatile memory device.
- the charge diffusion prevention layer made of the single film, the upper electrode layer, the lower electrode layer, and the resistance change layer are covered. Then, a step of forming an interlayer insulating layer on the substrate may be included.
- the nonvolatile memory device of the present invention includes an upper electrode layer, a lower electrode layer, a resistance change layer sandwiched between the upper electrode layer and the lower electrode layer, and a part of the upper electrode layer.
- the upper electrode layer and the lower electrode layer contains a simple substance or an alloy of a platinum group element, and the charge diffusion prevention mask has an insulating property.
- the etching rate by dry etching is smaller than that of the upper electrode layer and the lower electrode layer.
- the material of the charge diffusion prevention mask is one material selected from Ta 2 O 5 , SiN, and SiON or a combination of two or more materials.
- the charge diffusion prevention mask is preferably made of Ta 2 O 5 .
- the platinum group element is platinum, iridium, or palladium.
- the charge diffusion prevention mask and the resistance change layer may be composed of the same element. When configured in this way. A low-cost nonvolatile memory device can be obtained as compared with a conventional nonvolatile memory device.
- the present invention is configured as described above, and has an effect of suppressing variations in initial resistance values in a nonvolatile memory device.
- FIG. 1 is a cross-sectional view showing a configuration of a nonvolatile memory device according to Embodiment 1 of the present invention.
- 2A to 2C are cross-sectional views illustrating steps of the method for manufacturing the nonvolatile memory device according to Embodiment 1 of the present invention.
- 3A and 3B are cross-sectional views illustrating the steps of the method for manufacturing the nonvolatile memory device according to Embodiment 1 of the present invention.
- FIGS. 4A to 4D are diagrams illustrating etching in the process of forming the upper electrode layer, the resistance change layer, and the lower electrode layer by dry etching in the method for manufacturing the nonvolatile memory device according to the first embodiment of the present invention. It is sectional drawing which shows the flow of plasma.
- FIG. 5A to 5D are cross-sectional views showing the flow of etching plasma in the process of forming the upper electrode layer, the resistance change layer, and the lower electrode layer by dry etching in the comparative example.
- FIG. 6 is a cross-sectional view showing the configuration of the nonvolatile memory device according to Embodiment 2 of the present invention.
- 7A to 7C are cross-sectional views illustrating steps of the method for manufacturing the nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 8 is a cross-sectional view showing the steps of the method for manufacturing the nonvolatile memory device according to Embodiment 2 of the present invention.
- FIG. 9A to 9D show the flow of etching plasma in the process of forming the upper electrode layer, the resistance change layer, and the lower electrode layer by dry etching in the method for manufacturing the nonvolatile memory device according to this embodiment.
- FIG. FIG. 10 is a diagram showing the distribution of resistance values of the resistance change layer of the nonvolatile memory device according to the example of the present invention in comparison with the distribution of resistance values of the resistance change layer of the comparative example.
- FIG. 1 is a cross-sectional view showing the configuration of the nonvolatile memory device according to Embodiment 1 of the present invention.
- the nonvolatile memory device 10 ⁇ / b> A includes a nonvolatile memory element 101.
- the nonvolatile memory device 10A includes a nonvolatile memory element 101 and a thin film transistor 102 electrically connected to the nonvolatile memory element 101 (one transistor / 1 nonvolatile memory element type (active matrix type)).
- the nonvolatile memory device 10 ⁇ / b> A of the present embodiment is not necessarily provided with the thin film transistor 102.
- the nonvolatile memory device 10A includes one nonvolatile memory element 101 is exemplified, but it goes without saying that the nonvolatile memory device 10A may include a plurality of nonvolatile memory elements 101.
- the non-volatile storage device 10 ⁇ / b> A includes a substrate 11.
- the substrate 11 is composed of, for example, a silicon substrate.
- a pair of source / drain layers 12 are formed in a well (a boundary is not shown) at an interval.
- a gate layer 13 is formed above a region (channel region) between the pair of source / drain layers 12.
- a gate insulating film (not shown) is formed between the channel region and the gate layer 13.
- the pair of source / drain layers 12 and the gate layer 13 constitute a thin film transistor.
- a first interlayer insulating layer 14 is formed so as to cover the surface of the substrate 11 on which the pair of source / drain layers 12 is formed and the gate layer 13.
- the first interlayer insulating layer 14 is made of, for example, SiO 2 .
- the nonvolatile memory element 101 is formed on the first interlayer insulating layer 14. Specifically, the lower electrode layer 4 is formed on the first interlayer insulating layer 14, the resistance change layer 3 is formed on the lower electrode layer 4, and the upper electrode layer 2 is formed on the resistance change layer 3. Is formed. That is, the resistance change layer 3 is sandwiched between the upper electrode layer 2 and the lower electrode layer 4. These upper electrode layer 2, resistance change layer 3, and lower electrode layer 4 constitute a nonvolatile memory element 101. Further, a charge diffusion prevention mask 1A is formed on the upper electrode layer 2.
- a second interlayer insulating layer 19 is formed so as to cover the nonvolatile memory element 101, the charge diffusion prevention mask 1A, and the first interlayer insulating layer.
- the second interlayer insulating layer 19 is made of, for example, SiO 2 .
- FIG. 1 shows two wirings 18 a and 18 b among a plurality of wirings constituting the wiring group 18.
- the first contact 16 is formed so as to penetrate the second interlayer insulating layer 19 and the charge diffusion prevention mask 1A from the wiring 18b to the upper electrode layer 2 of the nonvolatile element 101. Thereby, the upper electrode layer 2 of the nonvolatile memory element 101 and the wiring 18b are electrically connected.
- a second contact 15 is formed so as to penetrate from the lower electrode 4 of the nonvolatile memory element 101 through the first interlayer insulating layer 14 to one source / drain layer 12 of the thin film transistor 102. Thereby, the lower electrode 4 of the nonvolatile memory element 101 and one of the source / drain layers 12 of the thin film transistor 102 are electrically connected.
- a third contact 17 is formed so as to penetrate the second interlayer insulating layer 19 and the first interlayer insulating layer 14 from the wiring 18a to the other of the source / drain layers 12 of the thin film transistor 102. Yes. As a result, the other source / drain layer 12 of the thin film transistor 102 and the wiring 18a are electrically connected.
- a predetermined electric pulse (voltage pulse or current pulse, or both) is applied between the wiring 18a and the wiring 18b by a voltage application device (not shown).
- the gate layer 13 is connected to a wiring (not shown), and a predetermined control voltage is applied through the wiring, whereby the operation of the thin film transistor 102 is controlled.
- the material of the resistance change layer 3 is also a material of the resistance change film 3 ′ (original film of the resistance change layer 3) in a method for manufacturing a nonvolatile memory device described later.
- the resistance change layer 3 includes a material whose resistance value changes according to a change in oxygen content (hereinafter referred to as an oxygen content change type resistance change material), and the oxygen content change type resistance change material includes: This contributes to a resistance change of the resistance change layer 3 by applying an electric pulse between the upper electrode layer 2 and the lower electrode layer 4.
- the reason for limiting the material of the resistance change layer 3 to the oxygen content change type resistance change material is that by optimizing the oxygen content of the material and its profile, it is possible to operate at a high speed with a pulse width of 100 ns or less. This is because the resistance change width can be one digit or more and the read margin can be increased.
- the resistance change layer 3 includes an oxygen content change resistance change material
- the resistance change layer 3 is substantially composed of an oxygen content change resistance change material, This means that an additive that does not affect the resistance change of the resistance change layer 3 may be included.
- a typical example of the oxygen content change resistance change material is an oxygen-deficient transition metal oxide.
- Preferred oxygen-deficient transition metal oxides include, for example, TaO x , HfO x , ZrO x , NiO x , VO x , ZnO x , NbO x , TiO x , WO x , CoO x , FeO x Number).
- the oxygen-deficient transition metal oxide has a lower oxygen number than the transition metal oxide having the stoichiometric composition, so that the transition metal oxide having the stoichiometric composition is generally insulated.
- the oxygen-deficient transition metal oxide exhibits semiconductor or conductor characteristics.
- the oxygen-deficient transition metal oxide When such an oxygen-deficient transition metal oxide is disposed and electrically connected between two electrodes, and electric pulses having different polarities are applied between the two electrodes (bipolar operation), the oxygen-deficient transition metal
- the resistance value of the oxide can be reversibly increased or decreased. The increased or decreased resistance value is maintained even after the application of the electric pulse between the two electrodes is stopped. It is presumed that the resistance change mechanism in the above case is as follows.
- the resistance change is caused by the fact that oxygen ions are collected at the interface between the resistance change layer and one of the pair of electrodes sandwiching the resistance change layer by an electric field at the vicinity of the interface of the resistance change layer. It is expressed by the diffusion of oxygen ions. Specifically, if a positive voltage is applied to the one electrode with respect to the other electrode, negatively charged oxygen ions gather at a site near the interface with the one electrode of the resistance change layer, and A high resistance layer is formed at the site to increase the resistance. On the contrary, if a negative voltage is applied to the one electrode with respect to the other electrode, oxygen ions gathered at a site near the interface with the one electrode diffuse from the site into the other resistance change layer.
- the resistance change layer in the vicinity of the interface with the one electrode is reduced in resistance.
- Oxygen ions near the interface diffuse to other parts of the resistance change film, but the volume of the other part of the resistance change film is much larger than the volume of the part near the interface. The resistance value of this part is not greatly increased.
- the material of the resistance change layer 3 is particularly preferably TaO x (0.8 ⁇ x ⁇ 1.9) among oxygen-deficient transition metal oxides. If TaO x (0.8 ⁇ x ⁇ 1.9), the operation speed of the nonvolatile memory device can be increased, and reversibly stable rewriting characteristics and the like can be obtained.
- the material of the resistance variable layer 3 illustrates a case where the TaO x (0.8 ⁇ x ⁇ 1.9 ). Details of the preferable composition range, characteristics, resistance change mechanism, and the like of TaO x are described in WO 2008/059701 A1 International Publication, so refer to it.
- the resistance change layer 3 includes a first resistance change layer (first layer) made of TaO x (0.8 ⁇ x ⁇ 1.9) and a second resistance change layer made of TaO y (x ⁇ y) ( (Second layer).
- first layer made of TaO x (0.8 ⁇ x ⁇ 1.9)
- second resistance change layer made of TaO y (x ⁇ y) ( (Second layer).
- the second resistance change layer needs to be positioned on a predetermined electrode side described later.
- the materials of the upper electrode layer 2 and the lower electrode layer 4 are the materials of the upper electrode film 2 ′ and the lower electrode film 4 ′ (original films of the upper electrode layer 2 and the lower electrode layer 4) in the method of manufacturing a nonvolatile memory device described later. But there is.
- At least one of the upper electrode layer 2 and the lower electrode layer 4 contains a simple substance or an alloy of a platinum group element.
- the upper electrode layer 2 and the lower electrode layer 4 may have a single layer structure or a multi-layer structure.
- the platinum group element means platinum (Pt) and iridium (Ir) palladium (Pd).
- the reason for limiting the materials of the upper electrode layer 2 and the lower electrode layer 4 in this way is that the problem of the present invention that the initial resistance value varies is that either the upper electrode layer or the lower electrode layer is made of platinum or iridium. In the case of dry etching of these, a conductive hard mask is used.
- platinum, iridium, and palladium all have higher standard electrode potentials than transition metals that make up a resistance change film such as Ta, Hf, Ni, etc., so that the electrodes themselves are less likely to be oxidized and promote oxidation / reduction reactions of resistance change materials. They are suitable as electrode materials, have a high melting point, and have similar properties such that they are hardly affected by acids and alkalis, and a hard mask is required for dry etching.
- At least one of the upper electrode layer 2 and the lower electrode layer 4 includes a single material or an alloy of one material selected from platinum, iridium, and palladium, or an alloy of a combination of two or more materials.
- the material of the resistance change layer 3 is an oxygen-deficient transition metal oxide
- one electrode (the above-mentioned predetermined electrode) of the upper electrode layer 2 and the lower electrode layer 4 is subjected to oxygen-deficient transition metal oxidation.
- a resistance change layer having a high oxygen concentration or a low oxygen concentration can be formed at the interface between the higher electrode and the resistance change film according to the applied voltage, and a stable operation can be obtained.
- the oxygen-deficient transition metal oxide is TaO x
- this condition is satisfied when platinum, iridium, palladium, or the like is used for one electrode and Ta, TaN, Ti, or the like is used for the other electrode. Fulfill.
- the material of the upper electrode 2 is platinum and the material of the lower electrode 4 is TaN will be exemplified.
- the material of the upper electrode 2 may be TaN
- the material of the lower electrode 4 may be platinum.
- the material of the charge diffusion prevention mask 1A is also a material of the charge diffusion prevention film 1A ′ (original film of the charge diffusion prevention layer 1A) in the method for manufacturing a nonvolatile memory device described later.
- the material of the charge diffusion prevention mask 1A needs to be insulative and have an etching rate by dry etching smaller than that of the upper electrode film 2 and the lower electrode film 4. Moreover, it is preferable that the adhesiveness with respect to the lower electrode layer (here upper electrode layer 2) is favorable.
- the charge diffusion preventing mask 1A may have such properties as a whole. Therefore, the charge diffusion preventing mask 1A may be a single layer structure or a multilayer structure having a plurality of layers. In the present embodiment, the case where the charge diffusion preventing mask 1A has a single layer structure is illustrated. Examples of the material of the charge diffusion prevention mask 1A having a single layer structure include Ta 2 O 5 and the like. Hereinafter, a case where the material of the charge diffusion prevention mask 1A is Ta 2 O 5 will be exemplified.
- the etching rate by dry etching can be made sufficiently smaller than a film made of a platinum group element or an alloy, there is an advantage that the shape of the mask can be accurately reflected as the shape of the upper electrode.
- the charge diffusion prevention mask 1A charge diffusion prevention mask film 1A '
- the resistance change layer 3 resistance change film 3'
- the conditions for etching the charge diffusion preventing film 1A 'and the conditions for etching the resistance change film 3' can be made the same and can be easily etched.
- the charge diffusion preventing film 1A 'and the resistance change film 3' can be deposited by the same device, the device can be manufactured at a lower cost than the conventional nonvolatile memory device.
- SiN, SiON, or the like can also be used because the etching rate by dry etching can be made sufficiently smaller than a film made of a single element or alloy of a platinum group element.
- These films are CVD films often used in a semiconductor process, and it is easy to increase the thickness of the mask layer. Further, it is a material used for the interlayer film, and it is easy to form a contact with the upper electrode of the resistance change element.
- FIGS. 3 (a) and 3 (b) are cross-sectional views showing the steps of the method for manufacturing the nonvolatile memory device according to Embodiment 1 of the present invention.
- a large number of nonvolatile memory elements 101 are formed on the substrate 11, but only one nonvolatile memory element 101 is shown here for simplification of the drawing.
- a part of the diagram is enlarged for easy understanding.
- a pair of source / drain layers 12 and a gate layer 13 are formed on the substrate 11.
- a first interlayer insulating layer 14 is formed on the substrate 11.
- a first contact 15 is formed so as to penetrate the first insulating layer 14 and reach one source or drain layer 12.
- the lower electrode film 4 ′, the resistance change film 3 ′, and the upper electrode film 2 ′ are formed so as to cover the first contact 15 on the first insulating layer. Are deposited in this order.
- the lower electrode film 4 ′, the resistance change film 3 ′, and the upper electrode film 2 ′ are original films of the lower electrode layer 4, the resistance change layer 3, and the upper electrode layer 2, respectively.
- a charge diffusion preventing film 1A ' is deposited on the upper electrode film 2'. These processes are performed by sputtering, for example.
- the resistance change layer 3 has the above-described two-layer structure
- the production condition for example, the oxygen concentration of the processing gas
- the oxygen concentration of the processing gas is changed in the middle, thereby containing oxygen.
- Two films having different amounts are sequentially deposited.
- a resist mask 24 having a predetermined shape is formed by a normal exposure process and development process, and the resist mask 24 is used as a mask to perform charge etching by a dry etching process.
- the diffusion prevention film 1A ′ is patterned into a predetermined shape (pattern). Thereby, a charge diffusion prevention mask 1A having a predetermined shape is formed.
- the resist mask 24 is removed, and then the upper electrode film 2 ′, the resistance change film 3 ′, and the lower electrode film 4 are formed by a dry etching process using the charge diffusion prevention mask 1A as a mask.
- Each ' is formed into a predetermined shape (pattern).
- the nonvolatile memory element 101 including the upper electrode layer 2, the resistance change layer 3, and the lower electrode layer 4 is formed in a state where the charge diffusion prevention mask 1A is formed on the upper electrode layer 2.
- charging damage due to the charge of the etching plasma to the resistance change layer 3 is reduced. This effect will be described in detail later.
- a second interlayer insulating layer 19 is formed on the first interlayer insulating layer 14 so as to cover the charge diffusion preventing layer 1A and the nonvolatile memory element 101.
- a second contact 16 is formed so as to penetrate the second interlayer insulating layer 19 and the charge diffusion prevention mask 1A and reach the upper electrode layer 2 of the nonvolatile memory element 101, and the second interlayer insulating layer 19
- the third contact 17 is formed so as to penetrate the first interlayer insulating layer 14 and reach the other source or drain layer 12.
- a wiring group 18 including a wiring 18 a and a wiring 18 b connected to the second contact 16 and the third contact 17 is formed on the upper surface of the second insulating layer 19.
- the nonvolatile memory device 10A is manufactured.
- FIGS. 5A to 5D are cross-sectional views showing the flow of etching plasma in the process of forming the upper electrode layer, the resistance change layer, and the lower electrode layer by dry etching in the comparative example.
- This comparative example is the same as the method for manufacturing the nonvolatile memory device according to the present embodiment except that the conductive hard mask 23 is used instead of the charge diffusion preventing mask 1A.
- the hard mask 23 is made of a conductive material such as TiAlN.
- the charge of the etching plasma is transferred from the conductive mask layer 23 to the upper part. Although it diffuses to the electrode layer 2, since the upper electrode layer 2 is formed at this point, the charge of this etching plasma diffuses through the upper electrode layer 2 to the resistance change film 3 ′. It is estimated that the charge of the etching plasma diffused to the resistance change film 3 ′ flows through the lower electrode film 4 ′ made of a conductive material. Therefore, at least charging damage to the resistance change film 3 ′ due to the charge of the etching plasma occurs.
- FIG. 5D shows a process of removing the hard mask 23 by etching. This step may be performed as necessary. For example, when the process of removing the hard mask 23 is included, the charge of the etching plasma is diffused to the upper electrode layer 2, the resistance change layer 3, and the lower electrode layer 4 as in the previous process. Therefore, at least in this process, charging damage to the resistance change layer 3 due to the etching plasma charge occurs.
- the charge diffusion prevention mask 1A of the upper electrode film 2 ′ is charged in the portion. Since the diffusion preventing mask 1A has an insulating property, the charge of the etching plasma is suppressed by the charge diffusion preventing mask 1A and is not diffused into the upper electrode film 2 ′. Further, the charge of the etching plasma diffused on the etching surface of the upper electrode film 2 ′ without the charge diffusion preventing mask 1 A flows through the upper electrode film 2 ′ and is not diffused into the resistance change layer 3. Thus, charging damage due to the etching plasma charge on the resistance change film 3 ′ does not occur in this process.
- FIG. 4B shows a process in which the etching of the upper electrode film 2 'is completed to form the upper electrode layer 2, and then the resistance change film 3' is patterned by etching.
- the charge diffusion prevention mask 1A has an insulating property in the portion of the resistance change film 3 ′ located below the charge diffusion prevention mask 1A, so that the charge of the etching plasma is suppressed by the charge diffusion prevention mask 1A. It is not diffused into the upper electrode layer 2. Therefore, the charge of the etching plasma is not diffused to the resistance change film 3 ′ in contact with the upper electrode layer 2. The charge of the etching plasma is directly diffused to the etching surface of the resistance change film 3 ′ where the charge diffusion preventing mask 1A is not present.
- the etching surface of the resistance change film 3 receives charging damage due to the electric charge of the etching plasma, since it is an etching surface, the portion damaged by the charging damage is removed. Thereby, charging damage due to the charge of the etching plasma to the resistance change layer 3 patterned as a nonvolatile memory element in this process is prevented.
- the charge of the etching plasma is suppressed by the charge diffusion prevention mask 1A in the portion located below the charge diffusion prevention mask 1A. Thus, it is not diffused into the upper electrode layer 2 and the resistance change layer 3.
- the charge of the etching plasma that diffuses to the etching surface of the lower electrode film 4 'without the charge diffusion preventing layer 1A flows through the lower electrode film 4'. Thereby, in this process, charging damage to the resistance change layer 3 due to the charge of the etching plasma is prevented.
- FIG. 4D shows a state after the etching of the lower electrode film 4 ′ is completed and the lower electrode layer 4 is formed.
- the charge diffusion prevention mask 1A is placed on the upper electrode layer 2, and the upper electrode layer, the resistance change layer, and the lower electrode are formed by dry etching.
- the step of forming the layer ends. Therefore, since the state where the charge diffusion prevention mask 1A exists is maintained until the end, the charge of the etching plasma is suppressed by the charge diffusion prevention mask 1A, and the upper electrode layer 2, the resistance change layer 3 and the lower electrode layer 4 are transferred. Not spread. Thereby, the formation of the nonvolatile memory element 101 is completed while the charging damage to the resistance change layer 3 due to the charge of the etching plasma is prevented.
- a first predetermined electric pulse (current pulse and / or voltage pulse) is applied between the lower electrode layer 4 and the upper electrode layer 2.
- the electrical pulse diffuses into the resistance change layer 3 disposed between the lower electrode layer 4 and the upper electrode layer 2.
- the resistance change layer 3 has the first predetermined resistance value and maintains this state.
- a second predetermined electric pulse is applied between the lower electrode layer 4 and the upper electrode layer 2, the resistance value of the resistance change layer 3 becomes the second predetermined resistance value. To maintain.
- the first predetermined resistance value and the second predetermined resistance value are associated with, for example, two values of binary data. Then, binary data can be written in the nonvolatile memory element 101 by applying the first or second predetermined electrical pulse to the resistance change layer 3. Further, by supplying a voltage or current that does not change the resistance value of the resistance change layer 3 to the nonvolatile memory element 101 and detecting the resistance value, the binary value written in the nonvolatile memory element 101 is detected. Data can be read out.
- the resistance change layer 3 disposed between the lower electrode layer 4 and the upper electrode layer 2 functions as a storage unit.
- a nonvolatile memory element 101 is connected to a thin film transistor 102 (voltage or current supply switch) composed of a gate layer 13 and a source / drain layer 12, and the nonvolatile memory element 101 is connected by this thin film transistor 102.
- a controlled voltage or current binary data can be written to the nonvolatile memory element 101 as described above, and further, the binary data written to the nonvolatile memory element 101 as described above can be written. Data can be read out.
- the resistance value of the resistance change layer 3 that records the binary data depends on the oxygen concentration distribution of the resistance change layer 3.
- the charge of the etching plasma is suppressed by the charge diffusion prevention mask 1A by forming the charge diffusion prevention mask 1A on the upper electrode layer 2 in the manufacturing process of the nonvolatile memory device 10A. Is done. Therefore, by diffusing from the upper electrode layer 2 to the resistance change layer 3, charging damage in which the oxygen concentration in the resistance change layer 3 is disturbed can be prevented. Thereby, the oxygen concentration of the resistance change layer 3 is stabilized, a resistance value (initial resistance value) with suppressed variation can be obtained, and stable binary data can be obtained (recorded).
- FIG. 6 is a cross-sectional view showing the configuration of the nonvolatile memory device according to Embodiment 2 of the present invention.
- the nonvolatile memory device 10B replaces the charge diffusion preventing mask 1A of the nonvolatile memory device 10A according to the first embodiment with a two-layered charge diffusion preventing mask 1B (FIG. 6). 7 (c)) is formed on the upper electrode layer 2 of the nonvolatile memory element 101. The rest is the same as the nonvolatile memory device 10A of the first embodiment.
- FIG. 7 (a) to 7 (c) and FIG. 8 are cross-sectional views showing the steps of the method for manufacturing the nonvolatile memory device according to Embodiment 2 of the present invention.
- the lower electrode film 4 ′, the resistance change film 3 ′, and the upper electrode film 2 ′ are arranged in this order so as to cover the first contact 15 on the first insulating layer. accumulate. Further, an insulating inorganic mask film 21 'and a conductive metal mask film 23' are sequentially deposited on the upper electrode film 2 '. These processes are performed by sputtering, for example.
- the charge diffusion prevention mask 1B has a laminated structure of a plurality of layers (here, two layers). Specifically, the charge diffusion prevention mask 1B is configured, for example, by forming a conductive metal mask layer 23 on an insulating inorganic mask layer 21.
- the material of the insulating inorganic mask layer 21 is an insulating inorganic material. And it is preferable that the adhesiveness with respect to the lower electrode layer (here upper electrode layer 2) is favorable.
- the material of the insulating mask layer 21 is preferably Ta 2 O 5 , SiN, or SiON. This is because these are made of materials that satisfy this condition and are used in the manufacturing process of the nonvolatile memory device 10B of the present embodiment.
- the material of the conductive metal mask layer 23 is a metal. Specifically, as the material of the conductive metal mask layer 23, the same material as that of a normal conductive hard mask can be used. In the present embodiment, for example, TiAlN is used.
- the insulating inorganic mask film 21 ′ and the conductive metal mask film 23 ′ are original films of the insulating inorganic mask layer 21 and the conductive metal mask layer 23, respectively.
- the insulating inorganic mask layer 21 is always located below the conductive metal mask layer 23 in the charge diffusion prevention mask 1B. Only when the insulating inorganic mask layer 21 is positioned below the conductive metal mask layer 23, the insulating inorganic mask layer 21 is protected from being eroded by the dry etching by the conductive metal mask layer 23. This is because the etching plasma diffusing into the mask layer 23 can be prevented from diffusing into the upper electrode layer 2 and the like located below the insulating inorganic mask layer 21.
- the insulating inorganic mask layer 21 is positioned above the conductive metal mask layer 23, the insulating inorganic mask layer 21 is eroded by dry etching, and the etching plasma is below the insulating inorganic mask layer 21. It becomes impossible to suppress the diffusion to the upper electrode layer 2 and the like located in the region.
- a resist mask 24 having a predetermined shape is formed by a normal exposure process and development process, and the resist mask 24 is used as a mask to conduct conductivity by a dry etching process.
- the conductive metal mask film 23 'and the insulating inorganic mask film 21' are patterned into a predetermined shape (pattern).
- the charge diffusion prevention mask 1B having a predetermined shape is formed.
- a conductive metal mask layer 23 having the same shape is laminated on an insulating inorganic mask layer 21 having a predetermined shape.
- the resist mask 24 is removed, and then the upper electrode film 2 ′, the resistance change film 3 ′, and the lower electrode film 4 are formed by a dry etching process using the charge diffusion prevention mask 1B as a mask.
- Each ' is formed into a predetermined shape (pattern).
- the nonvolatile memory element 101 including the upper electrode layer 2, the resistance change layer 3, and the lower electrode layer 4 is formed in a state where the charge diffusion prevention mask 1B is formed on the upper electrode layer 2.
- the conductive metal mask layer 23 of the charge diffusion prevention mask 1B has an etching rate smaller than that of the upper electrode film 2 ′, the resistance change film 3 ′, and the lower electrode film 4 ′, it appropriately functions as a mask in dry etching. . In this process, charging damage to the resistance change layer 3 due to etching plasma charges is reduced. This effect will be described in detail later.
- the conductive metal mask layer 23 is removed by etching. Thereafter, the nonvolatile memory device 10B is manufactured through the process shown in FIG. 3B of the first embodiment.
- FIG. 9A to 9D show the flow of etching plasma in the process of forming the upper electrode layer, the resistance change layer, and the lower electrode layer by dry etching in the method for manufacturing the nonvolatile memory device according to this embodiment.
- FIG. 9A to 9D show the flow of etching plasma in the process of forming the upper electrode layer, the resistance change layer, and the lower electrode layer by dry etching in the method for manufacturing the nonvolatile memory device according to this embodiment.
- the charge diffusion prevention mask 1B of the upper electrode film 2 ′ is charged in the portion. Since the diffusion preventing mask 1B has the insulating inorganic mask layer 21, the charge of the etching plasma is suppressed by the insulating inorganic mask layer 21 and is not diffused into the upper electrode film 2 ′. Further, the charge of the etching plasma diffused on the etching surface of the upper electrode film 2 ′ without the charge diffusion preventing mask 1 B flows through the upper electrode film 2 ′ and is not diffused into the resistance change layer 3. Thus, charging damage due to the etching plasma charge on the resistance change film 3 ′ does not occur in this process.
- FIG. 9B shows a process in which the etching of the upper electrode film 2 'is completed and the upper electrode layer 2 is formed, and then the resistance change film 3' is patterned by etching.
- the charge diffusion prevention mask 1B since the charge diffusion prevention mask 1B has the insulating inorganic mask layer 21 in the portion of the resistance change film 3 ′ located below the charge diffusion prevention mask 1B, the charge of the etching plasma is absorbed by the insulating inorganic mask layer. It is suppressed by 21 and is not diffused into the upper electrode layer 2. Therefore, the charge of the etching plasma is not diffused to the resistance change film 3 ′ in contact with the upper electrode layer 2.
- the charge of the etching plasma is directly diffused to the etching surface of the resistance change film 3 ′ where the charge diffusion prevention mask 1B is not present. As described above, it is assumed that the charge of the diffused etching plasma flows through the lower electrode film 4 ′. The Therefore, although the etching surface of the resistance change film 3 receives charging damage due to the electric charge of the etching plasma, since it is an etching surface, the portion damaged by the charging damage is removed. Thereby, charging damage due to the charge of the etching plasma to the resistance change layer 3 patterned as a nonvolatile memory element in this process is prevented.
- the charge of the etching plasma is suppressed by the charge diffusion prevention mask 1A in the portion located below the charge diffusion prevention mask 1A. Thus, it is not diffused into the upper electrode layer 2 and the resistance change layer 3.
- the charge of the etching plasma that diffuses to the etching surface of the lower electrode film 4 'without the charge diffusion preventing layer 1A flows through the lower electrode film 4'. Thereby, in this process, charging damage to the resistance change layer 3 due to the charge of the etching plasma is prevented.
- FIG. 9D shows a process of removing the conductive metal mask layer 23 by etching after the etching of the lower electrode film 4 ′ is completed and the lower electrode layer 4 is formed.
- the insulating inorganic mask layer 21 suppresses the etching plasma charge and does not diffuse into the upper electrode layer 2, the resistance change layer 3, and the lower electrode layer 4. Thereby, also in this process, charging damage to the resistance change layer 3 due to the charge of the etching plasma is prevented.
- nonvolatile memory device 10B As described above, also in the present embodiment, as in the first embodiment, charging damage due to the electric charge of the etching plasma to the resistance change layer 3 is suppressed in the manufacturing process of the nonvolatile memory device 10B. As a result, a nonvolatile memory device in which variation in initial resistance value is suppressed can be obtained. Then, by using the nonvolatile memory device 10B, for example, a nonvolatile memory device having a stable operation including a configuration of one transistor / 1 nonvolatile memory element can be manufactured.
- the present example embodies a method for manufacturing the nonvolatile memory device according to the second embodiment.
- TaN is deposited as a lower electrode layer film 4 ′ by 30 nm
- TaO x (0.8 ⁇ x ⁇ 1.9) is deposited as a resistance change film 3 ′ by 50 nm
- Platinum (Pt) is deposited to 50 nm as the electrode film 2 ′
- Ta 2 O 5 is deposited to 20 nm as the insulating inorganic mask film 21 ′
- TiAlN is deposited to 100 nm as the conductive metal mask film 23 ′.
- the second film made of TaO y (x ⁇ y) with a large amount may be formed to 5 nm.
- the oxidation treatment method is not limited to plasma oxidation, and for example, treatment having an effect of oxidizing the surface such as heat treatment in an oxygen atmosphere may be performed.
- Ta 2 O 5 may be deposited to 5 nm instead of oxidation after TaO x is deposited to 45 nm.
- the conductive metal mask film 23 'and the insulating inorganic mask film 21' are etched using the resist film 24 as a mask.
- the conductive metal mask layer 23 is removed by etching so that the insulating inorganic mask layer 21 remains on the upper surface of the upper electrode layer 2.
- a second interlayer insulating layer 19 is deposited and flattened using a CMP method. Thereafter, the second contact 16 is formed so as to penetrate the second interlayer insulating layer 19 and the insulating inorganic mask layer 21 and reach the upper electrode layer 2 by a semiconductor process used in a conventional semiconductor device, and A third contact 17 is formed so as to penetrate the two interlayer insulating layers 19 and the first interlayer insulating layer 14 and reach the source or drain layer 12. Next, a wiring group 18 including a wiring 18 a and a wiring 18 b connected to the second contact 16 and the third contact 17 is formed on the upper surface of the first interlayer insulating layer 14.
- FIG. 10 is a diagram showing the initial resistance of the resistance change layer 3 of the nonvolatile memory device 10B of Embodiment 2 created by the above manufacturing method and the distribution of resistance values of the resistance change layer of the comparative example. .
- the horizontal axis indicates the difference between the example of the present application and the comparative example, and the vertical axis indicates the resistance value normalized by the average value.
- the resistance distribution 1 shows the distribution of resistance values of the resistance change layer 3 in the example of the present application
- the resistance distribution 2 shows the distribution of resistance values of the resistance change layer 3 in the comparative example.
- the nonvolatile memory device of this example is manufactured by the manufacturing method of the example of the present application.
- the nonvolatile memory device of the comparative example is manufactured by the same manufacturing method as that of the embodiment except that a conductive hard mask made of TiAlN is used instead of the charge diffusion prevention mask 1B. Then, the initial resistance of these nonvolatile memory devices was measured, and the distribution was obtained.
- the variation in the resistance distribution (resistance distribution 1) of the example of the present application is reduced compared to the resistance distribution (resistance distribution 2) of the comparative example.
- the manufacturing method of the nonvolatile memory device according to the embodiment of the present invention can reduce the charging damage due to the etching plasma charge on the resistance change layer 3, and the embodiment of the present invention. In such a nonvolatile memory device, it was proved that charging damage due to the charge of the etching plasma to the resistance change layer 3 was reduced.
- the non-volatile memory device of one transistor / 1 non-volatile memory element is illustrated.
- the present invention is not limited to one diode (or nonlinear element) / 1 non-volatile memory element. You may apply to a memory
- the conductive metal mask layer 23 of the charge diffusion prevention mask 1B may be finally placed on the upper electrode layer 2.
- the nonvolatile memory device of the present invention is useful in various electronic devices such as digital home appliances, memory cards, portable telephones, and personal computers.
- the method for manufacturing a nonvolatile memory device of the present invention is useful as a method for manufacturing a nonvolatile memory device that can be used in various electronic devices such as digital home appliances, memory cards, mobile phones, and personal computers.
Abstract
Description
[構成]
<全体構成>
図1は本発明の実施の形態1に係る不揮発性記憶装置の構成を示す断面図である。
抵抗変化層3の材料は、後述する不揮発性記憶装置の製造方法における抵抗変化膜3’(抵抗変化層3のオリジナル膜)の材料でもある。
上部電極層2及び下部電極層4の材料は、後述する不揮発性記憶装置の製造方法における上部電極膜2’及び下部電極膜4’(上部電極層2及び下部電極層4のオリジナル膜)の材料でもある。
電荷拡散防止マスク1Aの材料は、後述する不揮発性記憶装置の製造方法における電荷拡散防止膜1A’(電荷拡散防止層1Aのオリジナル膜)の材料でもある。
次に、以上のように構成された不揮発性記憶装置の製造方法(本実施の形態1に係る不揮発性記憶装置の製造方法)を説明する。
次に、本実施の形態に係る不揮発性記憶装置の製造方法の作用効果を比較例と対比して説明する。
次に、以上のように構成され製造される本実施の形態の不揮発性記憶装置の動作を説明する。
図6は本発明の実施の形態2に係る不揮発性記憶装置の構成を示す断面図である。
図6に示すように、本実施の形態の不揮発性記憶装置10Bは、実施の形態1の不揮発性記憶装置10Aの電荷拡散防止マスク1Aに代えて、2層構造の電荷拡散防止マスク1B(図7(c)参照)を構成する絶縁性無機マスク層21が、不揮発性記憶素子101の上部電極層2の上に形成されている。これ以外は、実施の形態1の不揮発性記憶装置10Aと同じである。
次に、以上のように構成された不揮発性記憶装置の製造方法(本実施の形態2に係る不揮発性記憶装置の製造方法)を説明する。
次に、本実施の形態に係る不揮発性記憶装置の製造方法の作用効果を説明する。
1A’ 電荷拡散防止膜
2 上部電極層
2’ 上部電極膜
3 抵抗変化層
3’ 抵抗変化膜
4 下部電極層
4’ 下部電極膜
10A,10B 不揮発性記憶装置
11 基板
12 ソース/ドレイン層
13 ゲート層
14 第1の層間絶縁層
15 第1のコンタクト
16 第2のコンタクト
17 第3のコンタクト
18 配線群
18a,18b 配線
19 第2の層間絶縁層
21 絶縁性無機マスク層
21‘ 絶縁性無機マスク膜
23 導電性金属マスク層(ハードマスク)
23‘ 導電性金属マスク膜
24 レジストマスク
101 不揮発性記憶素子
102 薄膜トランジスタ
Claims (14)
- 上部電極層と、下部電極層と、前記上部電極層と前記下部電極層とに挟まれた抵抗変化層と、を備える不揮発性記憶装置の製造方法であって、
基板上に下部電極膜を堆積する工程と、
前記下部電極膜上に抵抗変化膜を堆積する工程と、
前記抵抗変化膜上に上部電極膜を堆積する工程と、
前記上部電極膜上に電荷拡散防止マスク膜を堆積する工程と、
前記電荷拡散防止マスク膜を所定の形状にパターニングして該電荷拡散防止マスク膜からなる電荷拡散防止マスクを形成する工程と、
前記電荷拡散防止マスクをマスクとして、前記上部電極膜、前記抵抗変化膜、及び前記下部電極膜をドライエッチングし、それにより、前記上部電極層、前記下部電極層、及び前記抵抗変化層を形成する工程と、を含み、
前記抵抗変化膜が、酸素不足型の遷移金属酸化物を含む第1膜と該第1膜より酸素含有量の高い酸素不足型の遷移金属酸化物を含む第2膜とが積層されて形成されており、
前記上部電極膜及び前記下部電極膜の少なくともいずれかが白金族元素の単体又は合金を含んでおり、
前記電荷拡散防止マスク膜は、絶縁性であり、かつ前記ドライエッチングによるエッチングレートが前記上部電極膜及び前記下部電極膜より小さい、不揮発性記憶装置の製造方法。 - 前記電荷拡散防止マスク膜は、絶縁性の無機材料からなる絶縁性無機膜と該絶縁性無機膜の上に形成された金属からなる導電性金属膜とを含んでおり、
前記電荷拡散防止マスク膜を堆積する工程は、前記上部電極膜上に前記無機絶縁膜を堆積する工程と、前記無機絶縁膜の上に前記導電性金属膜を堆積する工程と、を含む、請求項1に記載の不揮発性記憶装置の製造方法。 - 前記無機絶縁膜の絶縁性の無機材料が、Ta2O5、SiN、及びSiONから選択される1つの材料又は2以上の材料の組み合わせである、請求項2に記載の不揮発性記憶装置の製造方法。
- 前記電荷拡散防止マスク膜は、絶縁性であり、かつ前記ドライエッチングによるエッチングレートが前記上部電極膜及び前記下部電極膜より小さい単膜を含んでおり、
前記電荷拡散防止マスク膜を堆積する工程は、前記上部電極膜上に前記単膜を堆積する工程である、請求項1に記載の不揮発性記憶装置の製造方法。 - 前記単膜が、Ta2O5からなる、請求項4に記載の不揮発性記憶装置の製造方法。
- 前記白金族元素が、白金、イリジウム、又はパラジウムである、請求項1に記載の不揮発性記憶装置の製造方法。
- 前記電荷拡散防止マスク膜と前記抵抗変化膜とが同じ元素で構成されている、請求項1に記載の不揮発性記憶装置の製造方法。
- 前記上部電極層、前記下部電極層、及び前記抵抗変化層を形成する工程の後に、前記電荷拡散防止マスクのうちの前記導電性金属膜からなる層を除去する工程と、前記導電性金属膜からなる層が除去された電荷拡散防止層、前記上部電極層、前記下部電極層、及び前記抵抗変化層を覆うようにして、前記基板上に層間絶縁層を形成する工程と、を含む、請求項2に記載の不揮発性記憶装置の製造方法。
- 前記上部電極層、前記下部電極層、及び前記抵抗変化層を形成する工程の後に、前記単膜からなる電荷拡散防止層、前記上部電極層、前記下部電極層、及び前記抵抗変化層を覆うようにして、前記基板上に層間絶縁層を形成する工程を含む、請求項4に記載の不揮発性記憶装置の製造方法。
- 上部電極層と、
下部電極層と、
前記上部電極層と前記下部電極層とに挟まれた抵抗変化層と、
前記上部電極層の一部の上に形成された電荷拡散防止マスクと、を備え、
前記抵抗変化層が、酸素不足型の遷移金属酸化物を含む第1層と該第1層より酸素含有量の高い酸素不足型の遷移金属酸化物を含む第2層とが積層されて形成されており、
前記上部電極層及び前記下部電極層の少なくともいずれかが白金族元素の単体又は合金を含んでおり、
前記電荷拡散防止マスクは、絶縁性であり、かつドライエッチングによるエッチングレートが前記上部電極層及び前記下部電極層より小さい、不揮発性記憶装置。 - 前記電荷拡散防止マスクの材料が、Ta2O5、SiN、及びSiONから選択される1つの材料又は2以上の材料の組み合わせである、請求項10に記載の不揮発性記憶装置。
- 前記電荷拡散防止マスクが、Ta2O5からなる、請求項10に記載の不揮発性記憶装置。
- 前記白金族元素が、白金、イリジウム、又はパラジウムである、請求項10に記載の不揮発性記憶装置。
- 前記電荷拡散防止マスクと前記抵抗変化層とが同じ元素で構成されている、請求項10に記載の不揮発性記憶装置。
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Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014038984A (ja) * | 2012-08-20 | 2014-02-27 | Nec Corp | 抵抗変化素子、および抵抗変化素子の形成方法 |
Families Citing this family (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4972238B2 (ja) * | 2010-09-28 | 2012-07-11 | パナソニック株式会社 | 抵抗変化型不揮発性記憶素子のフォーミング方法 |
US9012880B2 (en) * | 2013-02-21 | 2015-04-21 | Winbond Electronics Corp. | Resistance memory device |
US9252359B2 (en) | 2013-03-03 | 2016-02-02 | Adesto Technologies Corporation | Resistive switching devices having a switching layer and an intermediate electrode layer and methods of formation thereof |
WO2014146003A1 (en) * | 2013-03-15 | 2014-09-18 | Adesto Technologies Corporation | Nonvolatile memory with semimetal or semiconductors electrodes |
US11639142B2 (en) | 2019-01-11 | 2023-05-02 | Ford Global Technologies, Llc | Electronic control module wake monitor |
TWI696179B (zh) * | 2019-07-09 | 2020-06-11 | 華邦電子股份有限公司 | 電阻式隨機存取記憶體及其重置方法 |
US11495743B2 (en) | 2020-05-05 | 2022-11-08 | Taiwan Semiconductor Manufacturing Company, Ltd. | Non-volatile memory device and manufacturing technology |
CN111564555B (zh) * | 2020-05-20 | 2022-04-12 | 浙江大学 | 一种改善工作稳定性及存储窗口的阻变存储器及制备方法 |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003282550A (ja) * | 2001-11-12 | 2003-10-03 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
WO2008149484A1 (ja) * | 2007-06-05 | 2008-12-11 | Panasonic Corporation | 不揮発性記憶素子およびその製造方法、並びにその不揮発性記憶素子を用いた不揮発性半導体装置 |
JP2009130139A (ja) * | 2007-11-22 | 2009-06-11 | Toshiba Corp | 不揮発性半導体記憶装置の製造方法 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6485988B2 (en) * | 1999-12-22 | 2002-11-26 | Texas Instruments Incorporated | Hydrogen-free contact etch for ferroelectric capacitor formation |
US7884349B2 (en) * | 2002-08-02 | 2011-02-08 | Unity Semiconductor Corporation | Selection device for re-writable memory |
KR100697282B1 (ko) | 2005-03-28 | 2007-03-20 | 삼성전자주식회사 | 저항 메모리 셀, 그 형성 방법 및 이를 이용한 저항 메모리배열 |
JP4580284B2 (ja) * | 2005-06-20 | 2010-11-10 | Okiセミコンダクタ株式会社 | 強誘電体素子の製造方法 |
JP2007227500A (ja) * | 2006-02-22 | 2007-09-06 | Seiko Epson Corp | 半導体記憶装置および半導体記憶装置の製造方法 |
CN101636840B (zh) | 2006-11-17 | 2011-05-25 | 松下电器产业株式会社 | 非易失性存储元件、非易失性存储器件、非易失性半导体器件以及非易失性存储元件的制造方法 |
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Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2003282550A (ja) * | 2001-11-12 | 2003-10-03 | Hynix Semiconductor Inc | 半導体素子の製造方法 |
WO2008149484A1 (ja) * | 2007-06-05 | 2008-12-11 | Panasonic Corporation | 不揮発性記憶素子およびその製造方法、並びにその不揮発性記憶素子を用いた不揮発性半導体装置 |
JP2009130139A (ja) * | 2007-11-22 | 2009-06-11 | Toshiba Corp | 不揮発性半導体記憶装置の製造方法 |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2014038984A (ja) * | 2012-08-20 | 2014-02-27 | Nec Corp | 抵抗変化素子、および抵抗変化素子の形成方法 |
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US8610102B2 (en) | 2013-12-17 |
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