WO2010106922A1 - Dispositif semiconducteur et son procédé de fabrication - Google Patents

Dispositif semiconducteur et son procédé de fabrication Download PDF

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Publication number
WO2010106922A1
WO2010106922A1 PCT/JP2010/053572 JP2010053572W WO2010106922A1 WO 2010106922 A1 WO2010106922 A1 WO 2010106922A1 JP 2010053572 W JP2010053572 W JP 2010053572W WO 2010106922 A1 WO2010106922 A1 WO 2010106922A1
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Prior art keywords
insulating film
film
charge storage
hafnium
semiconductor device
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PCT/JP2010/053572
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English (en)
Japanese (ja)
Inventor
恒洋 井野
昌生 新宮
章輔 藤井
章 高島
大介 松下
潤 藤木
直樹 安田
靖 中崎
浩一 村岡
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株式会社 東芝
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Priority to JP2011504808A priority Critical patent/JP5531259B2/ja
Publication of WO2010106922A1 publication Critical patent/WO2010106922A1/fr
Priority to US13/235,970 priority patent/US8569823B2/en

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/511—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures
    • H01L29/513—Insulating materials associated therewith with a compositional variation, e.g. multilayer structures the variation being perpendicular to the channel plane
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/401—Multistep manufacturing processes
    • H01L29/4011—Multistep manufacturing processes for data storage electrodes
    • H01L29/40117—Multistep manufacturing processes for data storage electrodes the electrodes comprising a charge-trapping insulator
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/51—Insulating materials associated therewith
    • H01L29/517—Insulating materials associated therewith the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region

Definitions

  • the present invention relates to a semiconductor device and a manufacturing method thereof.
  • An object of the present invention is to provide a semiconductor device excellent in both write / erase characteristics and charge retention characteristics and a method for manufacturing the same.
  • a semiconductor device includes a semiconductor region, a tunnel insulating film provided on a surface of the semiconductor region, and a hafnium oxide including a cubic region provided on the surface of the tunnel insulating film.
  • a method of manufacturing a semiconductor device includes a semiconductor region, a tunnel insulating film provided on a surface of the semiconductor region, a charge storage insulating film provided on a surface of the tunnel insulating film,
  • a method for manufacturing a semiconductor device comprising: a block insulating film provided on a surface of the charge storage insulating film; and a control gate electrode provided on the surface of the block insulating film, wherein the charge storage insulating film is formed
  • Doing includes forming hafnium oxide including a cubic region.
  • FIG. 1 is a cross-sectional view schematically showing a basic configuration of a semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view schematically showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 3 is a cross-sectional view schematically showing a part of the manufacturing process of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 4 is a diagram schematically showing the crystal structure of the hafnium oxide according to the first embodiment of the present invention.
  • FIG. 5 is a diagram schematically showing the energy band structure of the hafnium oxide film according to the first embodiment of the present invention.
  • FIG. 6 is a diagram showing the write characteristics of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 1 is a cross-sectional view schematically showing a basic configuration of a semiconductor device according to the first embodiment of the present invention.
  • FIG. 2 is a cross-sectional view schematically showing a part
  • FIG. 7 is a diagram showing the write characteristics of the semiconductor device according to the comparative example of the first embodiment of the present invention.
  • FIG. 8 is a diagram showing erase characteristics of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 9 is a diagram showing erase characteristics of the semiconductor device according to the comparative example of the first embodiment of the present invention.
  • FIG. 10 is a diagram showing charge retention characteristics of the semiconductor device according to the first embodiment of the present invention.
  • FIG. 11 is a diagram showing charge retention characteristics of the semiconductor device according to the comparative example of the first embodiment of the present invention.
  • FIG. 12 is a graph showing the rate of change of the flat band voltage Vfb for the first embodiment of the present invention and the comparative example.
  • FIG. 13 is a diagram showing X-ray diffraction results for the hafnium oxide films of the first embodiment and the comparative example of the present invention.
  • FIG. 14 is a diagram showing measurement results by GIXA for the hafnium oxide film of the first embodiment of the present invention.
  • FIG. 15 is a diagram showing a measurement result by GIXA for a hafnium oxide film of a comparative example of the first embodiment of the present invention.
  • FIG. 16 is a diagram showing XPS measurement results for the hafnium oxide film of the first embodiment of the present invention.
  • FIG. 17 is a cross-sectional view schematically showing a basic configuration of a semiconductor device according to the second to fifth embodiments of the present invention.
  • FIG. 18 is a cross-sectional view schematically showing a basic configuration of a semiconductor device according to the second to fifth embodiments of the present invention.
  • FIG. 19 is a diagram showing an X-ray diffraction profile of the charge storage insulating film.
  • FIG. 20 is a cross-sectional view schematically showing a basic configuration of a semiconductor device according to modifications of the second to fifth embodiments of the present invention.
  • FIG. 21 is a cross-sectional view schematically showing a basic configuration of a semiconductor device according to modifications of the second to fifth embodiments of the present invention.
  • FIG. 22 is a cross-sectional view schematically showing the basic configuration of the semiconductor device according to the sixth embodiment of the present invention.
  • FIG. 1 is a cross-sectional view schematically showing a basic configuration of a semiconductor device (charge trap type nonvolatile semiconductor memory device) according to a first embodiment of the present invention.
  • a tunnel insulating film 12 is formed on the surface of a silicon substrate (semiconductor substrate, semiconductor region) 11.
  • a silicon oxide film SiO 2 film
  • a silicon oxynitride film SiON film
  • a charge storage insulating film 13 is formed on the surface of the tunnel insulating film 12.
  • This charge storage insulating film is formed of a hafnium oxide film (HfO 2 film) including a cubic region, and this hafnium oxide film has oxygen vacancies.
  • the entire hafnium oxide film 13 may be a cubic region, or an amorphous region may be included in a part of the hafnium oxide film 13.
  • the hafnium oxide film may contain zirconium (Zr).
  • a block insulating film 14 is formed on the surface of the charge storage insulating film 13.
  • the block insulating film 14 is an insulating film having a function of blocking the flow of electrons and holes between the charge storage layer and the control gate, and is an aluminum oxide film (Al 2 O 3 film) or a silicon oxide film (SiO 2 ). 2 film) or the like.
  • a control gate electrode 15 is formed on the surface of the block insulating film 14.
  • a gold film Au film
  • a tantalum film Ta film
  • a tantalum compound film or the like is used.
  • a source region 16a and a drain region 16b are formed in the surface region of the silicon substrate 11, and a region between the source region 16a and the drain region 16b becomes a channel region of the transistor.
  • the natural oxide film formed on the (100) surface of the silicon substrate (semiconductor substrate) 11 is removed with a diluted hydrofluoric acid solution. Subsequently, for example, a 5 nm silicon oxide film (SiO 2 film) is formed as the tunnel insulating film 12 on the silicon substrate 11 by thermal oxidation.
  • a preliminary hafnium oxide film (HfO 2 film) 13a having a thickness of about 5 nm to be a charge storage insulating film is formed on the tunnel insulating film 12 by chemical sputtering (reactive sputtering). Specifically, the hafnium oxide film 13a is formed by sputtering an Hf target in an oxygen gas atmosphere diluted with Ar gas. At this stage, the hafnium oxide film 13a is an amorphous film. The hafnium oxide film 13a has an oxygen deficiency ratio of about 3 to 5 percent, for example.
  • the formation of the hafnium oxide film 13a is not limited to chemical sputtering, but a sputtering method from an HfO 2 target, a CVD (chemical vapor deposition) method, an ALD (atomic layer deposition) method, an EB (electron beam) evaporation method. Etc. can also be used.
  • an aluminum oxide film (Al 2 O 3 film) having a thickness of about 10 nm is formed as the block insulating film 14 on the hafnium oxide film 13a by MBE (molecular beam epitaxy).
  • MBE molecular beam epitaxy
  • the formation of the block insulating film 14 is not limited to the MBE method, and a CVD method or the like can also be used.
  • heat treatment is performed at 1050 ° C. for 30 seconds in a nitrogen gas atmosphere.
  • oxygen contained in the hafnium oxide film 13a moves to the block insulating film 14, and oxygen vacancies in the hafnium oxide film 13a increase.
  • the amorphous hafnium oxide film 13a is converted into a hafnium oxide film 13 including a cubic region.
  • the entire hafnium oxide film 13 may be converted into a cubic region, or an amorphous region may remain in a part of the hafnium oxide film 13.
  • a conductive film such as a gold (Au) film is formed as the control gate electrode film 15 on the block insulating film 14 by resistance heating vapor deposition.
  • the tunnel insulating film 12, the charge storage insulating film 13, the block insulating film 14, and the control gate electrode film 15 are patterned to form a gate structure.
  • an impurity element is ion-implanted into the surface region of the silicon substrate using the gate structure as a mask to form a source region 16a and a drain region 16b. In this way, a memory cell transistor as shown in FIG. 1 is formed.
  • hafnium oxide (HfO 2 ) at room temperature and normal pressure is monoclinic, and hafnium oxide having a cubic crystal structure is not inherently stable.
  • This can be explained mainly by a geometrically simplified model in crystallography that uses only elements such as ionic radius and atomic position. That is, since the ion radius of O 2 ⁇ is too large, eight O 2 ⁇ cannot exist in the closest state around Hf 4+ . Therefore, a state where seven O 2 ⁇ exist around Hf 4+ is stable.
  • Such a state is a monoclinic crystal, and usually a stable crystal structure of hafnium oxide is a monoclinic crystal.
  • the hafnium oxide having a cubic crystal structure can exist stably. That is, as shown in FIG. 4, oxygen deficiency when occurred, in the cubic crystal structure, eight in all O 2- site O 2- is not present. Therefore, the above-described geometrical constraints are relaxed, and the hafnium oxide having a cubic crystal structure can exist stably.
  • FIG. 5 is a diagram schematically showing the energy band structure of the charge storage insulating film (hafnium oxide film) 13 of the present embodiment.
  • the hafnium oxide film of this embodiment has a cubic crystal structure including oxygen vacancies, and therefore has trap levels (localized levels) as shown in FIG. Have. That is, the trap level exists at an appropriate depth between the valence band and the conduction band. If the trap level is too deep, high-speed write / erase characteristics are difficult to obtain, and if the trap level is too shallow, good charge retention characteristics are difficult to obtain. Since the hafnium oxide film of this embodiment has a trap level at an appropriate depth, high-speed write / erase characteristics can be obtained and excellent charge retention characteristics can be realized. Therefore, it is possible to realize a high-performance nonvolatile semiconductor memory having excellent characteristics and reliability.
  • FIG. 6 is a diagram showing the measurement results of the CV characteristics of the sample manufactured by the method of the present embodiment.
  • FIG. 7 is a diagram showing the measurement results of the CV characteristics of the sample of the comparative example.
  • the horizontal axis is writing time (writing time), and the vertical axis is flat band voltage (Vfb).
  • a hafnium oxide film (thickness 5 nm) is used as the charge storage insulating film
  • a silicon nitride film is used as the charge storage insulating film.
  • an aluminum oxide film (thickness 10 nm) is used for all samples.
  • CV characteristics were measured as follows. First, an erasing voltage of ⁇ 20 V is applied to both samples for 1 msec. Thereafter, for the sample of this embodiment, a writing voltage is applied from 10 V to 20 V in increments of 2 V. At this time, the writing time is changed from 1 ⁇ sec to 30 sec. For the sample of the comparative example, a writing voltage is applied from 16V to 24V in increments of 2V. The writing time is changed from 0.1 ⁇ sec to 10 sec. Then, capacitance characteristics (CV characteristics) are measured at each writing voltage and each writing time.
  • the equivalent oxide thickness (EOT: effective oxide thickness) of the hafnium oxide film is 1.2 nm.
  • EOT of the silicon nitride film is 2.5 nm. The reason why the writing voltage and the writing time are changed between the sample of this embodiment and the sample of the comparative example is that a range in which the characteristics of each sample are most easily understood is selected.
  • the following can be understood.
  • the writing time of the sample of this embodiment is shorter than that of the sample of the comparative example. Accordingly, the sample of this embodiment can perform writing at a higher speed. Further, when comparing values at which the Vfb shift is saturated, the sample of this embodiment has a higher saturation value than the sample of the comparative example. Therefore, the sample of this embodiment can accumulate more effective charges.
  • FIG. 8 is a diagram showing the measurement results of the CV characteristics of the sample manufactured by the method of the present embodiment.
  • FIG. 9 is a diagram showing measurement results of CV characteristics of the sample of the comparative example.
  • the horizontal axis is the erasing time (erasing time), and the vertical axis is the flat band voltage (Vfb).
  • a hafnium oxide film (thickness 5 nm) is used as the charge storage insulating film
  • a silicon nitride film is used as the charge storage insulating film.
  • an aluminum oxide film (thickness 10 nm) is used for all samples.
  • CV characteristics were measured as follows. First, a writing voltage of 20 V is applied to both samples for a time of 1 msec. Thereafter, with respect to the sample of this embodiment, each erase voltage from ⁇ 10 V to ⁇ 20 V in steps of 2 V is applied. At this time, the erase time is changed from 1 ⁇ sec to 30 sec. For the sample of the comparative example, each erase voltage from -16V to -24V in steps of 2V is applied. The erase time is changed from 0.1 ⁇ sec to 10 sec. Then, capacitance characteristics (CV characteristics) are measured at each erase voltage and each erase time.
  • the sample of this embodiment has a shorter erase time than the sample of the comparative example. Therefore, the sample of this embodiment can perform erasure at a higher speed. Note that in the region where Vfb is about 0.8 V or more, the sample of the present embodiment appears to be slow in the erase operation. This is because correct erase characteristics cannot be measured due to restrictions on sample measurement due to differences in the sample structure, such as differences in the storage film itself, such as differences in the Vfb initialization level depending on the presence or absence of the diffusion layer. It is.
  • the sample of this embodiment has a shorter erase time. Therefore, if the characteristics of the region where Vfb is lower than 0.8V are extrapolated to the region where 0.8V or more, the erasing time is considered to be actually shorter in the sample of this embodiment even in the region where Vfb is 0.8V or more. It is done. Further, comparing the values at which the Vfb shift is saturated, the saturation value in the negative direction is larger in the sample of the present embodiment than in the sample of the comparative example. Therefore, the sample of this embodiment can erase more effective charges.
  • FIG. 10 is a diagram showing measurement results of charge retention characteristics of a sample manufactured by the method of the present embodiment.
  • FIG. 11 is a diagram showing the measurement results of the charge retention characteristics of the sample of the comparative example.
  • the horizontal axis is retention time (retention time), and the vertical axis is flat band voltage (Vfb).
  • a hafnium oxide film (thickness 5 nm) is used as the charge storage insulating film
  • a silicon nitride film is used as the charge storage insulating film.
  • an aluminum oxide film (thickness 10 nm) is used for all samples.
  • the charge retention characteristics were measured as follows.
  • the temperature is raised to 125 ° C., and an erasing voltage of ⁇ 20 V is applied to the sample for a time of 1 msec. Thereafter, the flat band voltage is shifted to 2.8 V by applying a write voltage. Then, the flat band voltage Vfb is measured until 8000 sec elapses after 20 sec elapses.
  • the flat band voltage is shifted from 3.5 V to 6.5 V by raising the temperature to 85 ° C. and applying the write voltage. Then, the flat band voltage Vfb is measured until 8000 sec elapses after 20 sec elapses.
  • the flat band voltage Vfb is hardly shifted in the sample of this embodiment as in the sample of the comparative example.
  • FIG. 12 is a diagram showing the change rate of the flat band voltage Vfb for the sample of this embodiment and the sample of the comparative example.
  • A is a measurement result of the sample of this embodiment
  • b is a measurement result of the sample of a comparative example.
  • C shows the upper limit of the specification value. It can be seen that the sample of this embodiment also has good performance, similar to the sample of the comparative example.
  • the semiconductor device according to the present embodiment can achieve high-speed write / erase characteristics and can realize excellent charge retention characteristics. Therefore, it is possible to realize a high-performance nonvolatile semiconductor memory having excellent characteristics and reliability.
  • FIG. 13 is a diagram showing an X-ray diffraction result of the charge storage insulating film using the hafnium oxide film.
  • A1 is the measurement result of the sample of this embodiment, and (a2) is the theoretical calculation result for the hafnium oxide having a cubic crystal structure.
  • B1 is the measurement result of the sample of the comparative example, and (b2) is the theoretical calculation result for the hafnium oxide having a monoclinic crystal structure.
  • the sample of this embodiment As shown in FIG. 13, in the sample of this embodiment, a hafnium oxide film having a cubic crystal structure is obtained.
  • the sample of the comparative example is a hafnium oxide film having a monoclinic crystal structure. Since the charge storage insulating film is formed of hafnium oxide having a cubic crystal structure, the sample of this embodiment has excellent electrical characteristics as can be seen from the measurement results described above. On the other hand, when the charge storage insulating film is formed of hafnium oxide having a monoclinic crystal structure, excellent electrical characteristics cannot be obtained.
  • FIG. 14 is a diagram showing the measurement results by GIXA (glancing incidence X-ray analysis) of the charge storage insulating film (hafnium oxide film) of the sample of this embodiment.
  • GIXA luminancing incidence X-ray analysis
  • the film density of the hafnium oxide film is 10.7 g / cm 3
  • FIG. 15 is a diagram showing a measurement result by GIXA for the charge storage insulating film (hafnium oxide film) of the sample of the comparative example.
  • the film density of the hafnium oxide film of the comparative example is 8.9 g / cm 3, which is about 89 percent of the theoretical film density (10.0 g / cm 3 ) of the hafnium oxide having a monoclinic crystal structure. is there. That is, in the hafnium oxide having the monoclinic crystal structure of the comparative example, there are about 11% of defects such as crystal grain boundary voids. Such defects are inactive with respect to charge accumulation. Thus, it is understood that the charge accumulation characteristic is not improved.
  • the charge storage action of the charge storage insulating film using hafnium oxide is not due to defects such as voids in grain boundaries but oxygen vacancies existing in the cubic crystal structure. Is considered important.
  • FIG. 16 is a diagram showing the XPS (X-ray photoemission spectroscopy) measurement results for the hafnium oxide film having the cubic crystal structure of the present embodiment.
  • XPS X-ray photoemission spectroscopy
  • zirconium may be contained in the hafnium oxide film serving as the charge storage insulating film.
  • the hafnium oxide film may contain about 2 atomic percent or less of zirconium.
  • Hf and Zr have similar chemical properties and are expensive to separate from each other. Therefore, Hf raw material that can be obtained at a realistic cost necessary for the manufacturing method as shown in this embodiment. This is because Zr is contained in about 1 atomic percent. In the sample whose characteristics have been confirmed in the present application, such a raw material of Hf is used. A change in device characteristics due to a physical difference between Hf and Zr does not appear within the range of experimental accuracy when the amount of Zr mixed is 2 atomic percent or less. Thus, even if zirconium is contained, it is possible to obtain the same effect as that of the above-described embodiment.
  • the heat treatment for converting the hafnium oxide film 13a to the hafnium oxide film 13 having a cubic crystal structure is performed before the control gate electrode film 15 is formed. It may be performed after the gate electrode film 15 is formed.
  • a hafnium oxide film having a cubic crystal structure is obtained even when a certain amount or more of impurity elements (for example, yttrium (Y) or lanthanum (La) -based elements) are included in the hafnium oxide film. It is possible. However, a hafnium oxide film containing such an impurity element does not have a trap level at an appropriate position, so that a semiconductor device having excellent writing / erasing characteristics and charge retention characteristics cannot be obtained. In addition, the presence of an impurity element as described above in a semiconductor device is a major factor that causes deterioration of characteristics and reliability. Therefore, it is not preferable that the above-described impurity element is contained in the hafnium oxide film. In this embodiment, a hafnium oxide film having a cubic crystal structure is formed by oxygen vacancies. Therefore, there is no problem as described above, and a semiconductor device having excellent characteristics can be obtained.
  • impurity elements for example, yttrium (Y) or lanthan
  • the hafnium oxide film of this embodiment is substantially formed only of hafnium, zirconium, and oxygen. Therefore, in the hafnium oxide film of this embodiment, the ratio of the total number of atoms of hafnium, zirconium and oxygen is preferably higher than 99 atomic percent with respect to the total number of atoms in the hafnium oxide film.
  • control electrode 15 In the above embodiment, an example in which gold is used as the control electrode 15 has been described. However, TaC may be used instead of gold. Portions other than the control electrode 15 are the same as in the above embodiment.
  • a TaC electrode As the control electrode 15, there is an advantage that the control electrode 15 becomes stable even if a high-temperature heat treatment is used in the process after the formation of the control electrode 15.
  • a metal electrode composed of a plurality of constituent elements is used as the control electrode 15 as in this modification, there is an advantage that the electrode work function can be designed by modulating the composition.
  • control electrode 15 It is also possible to use highly doped polycrystalline silicon as the control electrode 15. Portions other than the control electrode 15 are the same as in the above embodiment. In this case, there is an advantage that consistency with a semiconductor integrated circuit process using conventional silicon is good.
  • control electrode 15 It is also possible to use highly doped amorphous silicon as the control electrode 15. Portions other than the control electrode 15 are the same as in the above embodiment. In this case, there is an advantage that consistency with a semiconductor integrated circuit process using conventional silicon is good. In particular, when it is amorphous, there is an advantage that it is possible to suppress diffusion of other elements in the vicinity of the control electrode.
  • control electrode 15 a semiconductor material such as highly doped silicon germanium or indium phosphide can be used as the control electrode 15. Portions other than the control electrode 15 are the same as in the above embodiment. In the subsequent processes, when it is not necessary to perform high heat treatment, problems such as mutual diffusion can be suppressed by selecting these materials depending on the material of the block insulating film.
  • an aluminum oxide film is used as the block insulating film 14, but a high dielectric constant film such as a LaHfO film, a LaTiO film, a PrSiO film, a LaAlO film, or a LaAlSiO film can also be used. . Except for the block insulating film 14, it is the same as the above embodiment. By using these high dielectric constant films, the oxide equivalent film thickness of the entire device can be reduced, which contributes to miniaturization of the device and can reduce the drive voltage of the device.
  • an SiO 2 film having a wide band gap can be used as the block insulating film 14.
  • the SiO 2 film is used as the tunnel insulating film 12, but a SiON film may be used. Except for the tunnel insulating film 12, it is the same as the above embodiment.
  • the SiON tunnel insulating film there is an advantage that the reliability of the tunnel insulating film can be improved.
  • the tunnel insulating film 12 various insulating films such as a Ge-added SiO 2 film having SiO 2 as a base material may be used. Except for the tunnel insulating film 12, it is the same as the above embodiment. By using various tunnel insulating films based on SiO 2 , there is an advantage that the high voltage characteristics of the tunnel insulating film can be improved.
  • the tunnel insulating film 12 an insulating film including a portion which is SiO 2, for example, it may be used various insulating film such as a multilayer film of SiO 2 and other materials. Except for the tunnel insulating film 12, it is the same as the above embodiment.
  • various tunnel insulating films such as a multilayer film of SiO 2 and other materials, there is an advantage that the high voltage characteristics of the tunnel film can be improved.
  • the heat treatment is performed at 1050 ° C. for 30 seconds in a nitrogen gas atmosphere, but the heat treatment is not limited to this condition. There is no need to perform any heat treatment. Actually, a sample in which only heat treatment inevitably occurs in other steps was also prepared and the characteristics were confirmed. However, there was a portion that exhibited superior characteristics rather than the above embodiment. Portions other than the heat treatment are the same as in the above embodiment.
  • the tunnel insulating film thickness is 5 nm, but the tunnel insulating film thickness may be 3 nm or more and 9 nm or less. If the thickness is less than 3 nm, the charge stored in the storage film leaks from the tunnel insulating film side. If it is thicker than 9 nm, it becomes impossible to inject charges from the tunnel insulating film side to the charge storage film. Except for the thickness of the tunnel insulating film, it is the same as the above embodiment.
  • the block insulating film thickness may be 5 nm or more and 20 nm or less. If the thickness is less than 5 nm, the charge stored in the storage film leaks from the block insulating film side. If it is thicker than 20 nm, most of the electric field is applied to the block insulating film during the charge storage operation, and it becomes impossible to inject charges from the tunnel insulating film side to the charge storage film. Except for the thickness of the block insulating film, it is the same as the above embodiment.
  • the film thickness of the charge storage film made of hafnium oxide was shown as the film thickness of the charge storage film made of hafnium oxide, but the charge storage film thickness may be 3 nm or more and 6 nm or less. If the thickness is less than 3 nm, the hafnium oxide cannot maintain the film structure through the steps after the deposition of the charge storage film, and the stored charge is rapidly reduced. If it is thicker than 6 nm, most of the electric field is applied to the charge storage film during the charge storage operation, and charge cannot be injected from the tunnel insulating film side to the charge storage film. Except for the thickness of the charge storage film, it is the same as the above embodiment.
  • the ratio of the total number of atoms of hafnium, zirconium and oxygen is higher than 99%.
  • the contained element is silicon, as will be described later, hafnium, zirconium and oxygen
  • the total number of atoms may be 99% or less.
  • FIG. 17 is a cross-sectional view schematically showing a basic configuration of a semiconductor device (charge trap type nonvolatile semiconductor memory device) according to the second embodiment of the present invention.
  • 18 is a cross-sectional view taken along line AA in FIG.
  • a substrate insulating film 22 is formed on the silicon substrate (semiconductor substrate) 21.
  • control gate electrodes 23 and control electrode insulating films 24 are alternately stacked.
  • a block insulating film 25 Inside the laminated structure of the control gate electrode 23 and the control electrode insulating film 24, a block insulating film 25, a charge storage insulating film 26, a tunnel insulating film 27, and a columnar semiconductor region 28 serving as a channel are formed. That is, the laminated structure of the control gate electrode 23 and the control electrode insulating film 24, the block insulating film 25, the charge storage insulating film 26 and the tunnel insulating film 27 surround the side surface of the semiconductor region 28.
  • the tunnel insulating film 27 is formed on the surface of the semiconductor region 28, the charge storage insulating film 26 is formed on the surface of the tunnel insulating film 27, and the block insulating film 25 is formed on the surface of the charge storage insulating film 26.
  • the control gate electrode 23 is formed on the surface of the block insulating film 25.
  • the nonvolatile semiconductor memory device of this embodiment has a structure in which a plurality of memory cells are stacked in the vertical direction.
  • a single crystal silicon (Si) substrate with an exposed (100) plane is used as the silicon substrate 21.
  • the substrate insulating film 22 is formed by thermally oxidizing the silicon substrate 21 by, for example, a thermal oxidation method.
  • a CVD (chemical vapor deposition) method, a sputtering method, or the like can be used for the formation of the substrate insulating film 22 .
  • various insulating materials such as SiN, Al 2 O 3 , and HfSiO can be used as the material for the substrate insulating film 22.
  • control gate electrode 23 for example, polycrystalline silicon formed by a CVD method can be used.
  • the formation of the control gate electrode 23 is not limited to the CVD method, and a sputtering method or the like can also be used.
  • the material of the control gate electrode 23 is not limited to polycrystalline silicon, and other materials may be used as long as they have excellent electrical conductivity.
  • the material of the control gate electrode 23 should be excellent in heat resistance.
  • the work function may be adjusted to an appropriate value. For example, Ta or a Ta compound may be used.
  • control electrode insulating film 24 for example, a SiO 2 film formed by a CVD method can be used.
  • the formation of the control electrode insulating film 24 is not limited to the CVD method, and various methods such as a sputtering method and an MBE method can be used.
  • the material of the control electrode insulating film 24 is not limited to SiO 2 , and various insulating films such as SiN, Al 2 O 3 , and HfSiO can be used.
  • the number of stacked control gate electrodes 23 and control electrode insulating films 24 is, for example, 32 layers. However, the number of stacked layers is not particularly limited, and any number of stacked layers can be used.
  • the hole may be formed in multiple times. For example, after four layers of the control gate electrode film 23 and the control electrode insulating film 24 are laminated, the lower part of the hole is formed, and further, the control gate electrode film 23 and the control electrode insulating film 24 are formed in four layers. Thereafter, the upper part of the hole may be formed. If the number of layers is too large, the etching conditions for forming the hole so that the cross-sectional areas of the upper part and the lower part are within an allowable error range become difficult. If the number of layers is too small, there is a problem in that the number of time-consuming lithography, such as forming the upper part of the hole so as to overlap the lower part of the previously opened hole, is increased. The number of holes formed may be three or more.
  • the block insulating film 25 is formed of SiO 2 by, for example, the CVD method along the inner wall of the hole.
  • the method for forming the block insulating film is not limited to the CVD method, but it needs to be a film forming method with excellent step coverage. Therefore, a film forming method classified as a broad CVD method is desirable. For example, it is not impossible to use the sputtering method, but it is necessary to use a special method such as film formation in a high gas pressure atmosphere near the transition region from the glow region to the arc region.
  • a charge storage insulating film 26 containing hafnium oxide containing silicon (Si) and including a cubic region is formed on the surface of the block insulating film 25.
  • the charge storage insulating film 26 is formed by, for example, an ALD method (Atomic layer deposition).
  • ALD method Atomic layer deposition
  • various film formation methods included in the category of the CVD method can be used. For example, the following method can be used.
  • Hot-wall thermal CVD method hot-wall thermal CVD
  • APCVD method Atmospheric pressure CVD
  • LPCVD method Low-pressure CVD
  • UHVCVD method Ultrahigh vacuum CVD
  • AACVD method Aerosol CVD method
  • MPCVD method Microwave plasma-assisted CVD
  • PECVD method Plasma-Enhanced CVD
  • RPECVD method Remote plasma-enhanced CVD
  • ALCVD method AtomicallyCVD
  • Cat-CVD method catalytic CVD
  • HFCVD method hot filament CVD
  • MOCVD method Metalorganic chemical vapor deposition
  • HPCVD method Hybrid Physical-Chem CVD method
  • HDPCVD method high density plasma chemical deposition
  • MCVD method Modified pore) n
  • the following can be used as the molecule containing Hf atoms for forming the charge storage insulating film 26.
  • Alkyl hafnium compounds such as tetramethyl hafnium, tetraethyl hafnium, tetrapropyl hafnium, tetraisopropyl hafnium, tetrabutyl hafnium, tetraisobutyl hafnium, tetra sec-butyl hafnium, tetra-tert-butyl hafnium, hafnium formate, hafnium acetate, hafnium propionate, Hafnium butyrate, hafnium isobutyrate, hafnium valerate, hafnium caproate, hafnium caprylate, hafnium 2-ethylhexanoate, hafnium caprate, hafnium neodecanoate, hafnium rosinate, hafnium naphthenate, hafnyl formate, hafnyl acetate, propionic acid
  • the molecules containing Si atoms for growing the charge storage insulating film 26 the following can be used.
  • a mixed gas of the molecule containing Hf and the molecule containing Si is used.
  • molecules containing oxygen for example, O 2 , O 3 , H 2 O, H 2 O 2 , NO, NO 2 , N 2 O, CO, CO 2 , alcohols, etc.
  • Hf hafnium
  • Si silicon
  • O oxygen
  • the mixing ratio of Hf and Si in the charge storage insulating film 26 is preferably such that the ratio of Si to Hf and Si as cation components is 4% or more and 50% or less. If the Si ratio is less than 4% or more than 50%, it becomes difficult to form cubic HfO 2 . Preferably, the Si ratio is preferably 12% or more and 15% or less. This is because when the Si ratio is less than 12% or more than 15%, the cubic HfO 2 ratio decreases and the relative dielectric constant of HfO 2 falls below the maximum value.
  • the charge storage insulating film 26 may be modified by heat treatment or the like after or during the formation of the charge storage insulating film 26.
  • the charge storage film can be modified by a method using plasma, a method of colliding ions or particles, a method using a highly reactive gas such as ozone, or a state in which internal energy such as radicals is higher than the ground state. It is possible to use various modification methods such as a method using particles in the above and a method combining these methods.
  • the purpose of the modification here is to first remove an undesired composition component contained in the charge storage insulating film 26, and secondly, a composition desired to be contained in the charge storage insulating film 26.
  • a tunnel insulating film 27 is formed on the surface of the charge storage insulating film 26.
  • a material of the tunnel insulating film 27 SiO 2 , SiON, or the like can be used.
  • various film forming methods included in the category of CVD can be used.
  • a semiconductor region (channel region) 28 is formed on the surface of the tunnel insulating film 27.
  • silicon such as polycrystalline silicon is preferably used, but amorphous or polycrystalline semiconductor materials such as IGZO (InGaZnO), various semiconductor nanotubes, various semiconductor nanowires, and the like can also be used.
  • the channel region 28 is preferably formed so as to fill all the holes.
  • a stacked nonvolatile memory is formed using, for example, a method described in Japanese Patent Application Laid-Open No. 2007-266143. Further, it is possible to use the method described in Japanese Patent Application Laid-Open No. 2007-266143 before the process described in this embodiment.
  • a charge storage insulating film having hafnium oxide including a cubic region can be formed.
  • high-speed write / erase characteristics can be obtained, excellent charge retention characteristics can be realized, and a high-performance nonvolatile semiconductor memory excellent in characteristics and reliability can be realized.
  • the block insulating film 25 is formed. Thereafter, a charge storage insulating film 26 is formed on the surface of the block insulating film 25.
  • a method for forming the charge storage insulating film 26 of the present embodiment will be described.
  • a film containing silicon (Si) and oxygen (O) is formed on the surface of the block insulating film 25.
  • This film is formed by, for example, the ALD method.
  • various film forming methods included in the category of the CVD method can be used. Specifically, various film forming methods (hot wall thermal CVD method, APCVD method, LPCVD method,..., Etc.) included in the category of the CVD method shown in the second embodiment can be used.
  • the molecules containing various Si atoms shown in the second embodiment are used. Can be used. One or more of these molecules can be used. Molecules constituting these materials can be easily vaporized, and a thin film containing silicon can be formed by introducing vaporized molecules in the vicinity of the substrate.
  • the molecule containing oxygen those shown in the second embodiment can be used.
  • the film may contain an element derived from a molecule containing Si atoms such as carbon. It is also possible to employ a technique for removing impurities such as carbon by performing post-treatment such as heat treatment or plasma treatment on a film containing an element derived from a molecule containing Si atoms.
  • a film containing hafnium (Hf) and oxygen (O) is formed by, for example, an ALD method.
  • various film forming methods included in the category of the CVD method can be used. Specifically, various film forming methods (hot wall thermal CVD method, APCVD method, LPCVD method,..., Etc.) included in the category of the CVD method shown in the second embodiment can be used.
  • the molecules containing various Hf atoms shown in the second embodiment can be used.
  • One or more of these molecules can be used.
  • the molecules constituting these materials can be easily vaporized, and a thin film containing hafnium can be formed by introducing vaporized molecules in the vicinity of the substrate.
  • the molecule containing oxygen those shown in the second embodiment can be used.
  • heat treatment is performed at a temperature of 800 ° C. to 1300 ° C.
  • a part or all of the film containing Si and O and the film containing Hf and O are mixed.
  • short-time annealing that is not in a thermal equilibrium state, such as flash lamp annealing or laser annealing, of about milliseconds to nanoseconds may be performed.
  • the mixing process is not limited to the heat treatment, and includes a case where the mixing process is performed due to an impact caused by deposited particles during deposition.
  • the mixing treatment can be performed a plurality of times at an arbitrary stage after the film containing Si and O and the film containing Hf and O are each deposited once or more.
  • the Si concentration is high and the Hf concentration is low on the side close to the block insulating film 25, and the Si concentration is low on the side far from the block insulating film 25.
  • a compositional gradient with a high Hf concentration occurs.
  • the concentration of Si or SiO 2 is 100% or the concentration of Hf or HfO 2 is 0% does not remain. If such a portion remains, the storage capability as a storage film will deteriorate.
  • the maximum value of Si concentration relative to Hf and Si is preferably 50% or less. This is because if the concentration of Si with respect to Hf and Si exceeds 50%, it becomes difficult to produce a cubic crystal structure of HfO 2 .
  • the minimum value of the Si concentration relative to Hf and Si is preferably 4% or more. This is because when the Si concentration relative to Hf and Si is less than 4%, it becomes difficult to produce a cubic crystal structure of HfO 2 .
  • the heat treatment for mixing the film containing Si and O and the film containing Hf and O removes impurities such as carbon contained in the film containing Si and O and the film containing Hf and O. It may also serve as a heat treatment for the purpose.
  • the heat treatment for mixing the film containing Si and O and the film containing Hf and O is performed by forming a tunnel film or the like after forming the film containing Si and O or the film containing Hf and O. It can also be performed at an appropriate stage in the subsequent process, such as after film formation.
  • Subsequent processes (such as a process of forming the charge storage insulating film 26 and the tunnel insulating film 27) are the same as those in the second embodiment, and thus description thereof is omitted.
  • FIG. 19 shows an X-ray diffraction profile of the charge storage insulating film 26 manufactured in this way. Both a peak attributed to the monoclinic hafnium oxide and a peak attributed to the cubic hafnium oxide were observed, and good accumulation characteristics were obtained.
  • the charge storage insulating film obtained in the present embodiment has less cubic HfO 2 component than the charge storage film manufactured as in the second embodiment.
  • the charge center position can be shifted to the block absolute film side. Therefore, the leakage current to the tunnel insulating film side can be reduced, and the retention characteristics can be improved.
  • the region rich in cubic HfO 2 and the region rich in monoclinic HfO 2 in the film thickness direction there is an advantage that a region rich in cubic HfO 2 can be set at a position where the charge center should be guided. is there.
  • the block insulating film 25 is formed. Thereafter, a charge storage insulating film 26 is formed on the surface of the block insulating film 25.
  • a method for forming the charge storage insulating film 26 of the present embodiment will be described.
  • a film containing hafnium (Si) and oxygen (O) is formed on the surface of the block insulating film 25.
  • This film is formed by, for example, the ALD method.
  • various film forming methods included in the category of the CVD method can be used. Specifically, various film forming methods (hot wall thermal CVD method, APCVD method, LPCVD method,..., Etc.) included in the category of the CVD method shown in the second embodiment can be used.
  • the molecules containing various Hf atoms shown in the second embodiment can be used.
  • One or more of these molecules can be used.
  • the molecules constituting these materials can be easily vaporized, and a thin film containing hafnium can be formed by introducing vaporized molecules in the vicinity of the substrate.
  • the molecule containing oxygen those shown in the second embodiment can be used.
  • the film may contain a molecule-derived element containing Hf atoms such as carbon. It is also possible to employ a technique for removing impurities such as carbon by performing post-treatment such as heat treatment or plasma treatment on a film containing an element derived from a molecule containing Hf atoms.
  • the ratio of oxygen to Hf is preferably smaller than the stoichiometric ratio.
  • a process in which oxygen becomes a stoichiometric ratio is generally controlled. Excellent. Therefore, oxygen relative to Hf may have a stoichiometric ratio.
  • a film containing silicon (Si) and oxygen (O) is formed by, for example, an ALD method.
  • various film forming methods included in the category of the CVD method can be used. Specifically, various film forming methods (hot wall thermal CVD method, APCVD method, LPCVD method,..., Etc.) included in the category of the CVD method shown in the second embodiment can be used.
  • the molecules containing various Si atoms shown in the second embodiment are used. Can be used. One or more of these molecules can be used. Molecules constituting these materials can be easily vaporized, and a thin film containing silicon can be formed by introducing vaporized molecules in the vicinity of the substrate.
  • the molecule containing oxygen those shown in the second embodiment can be used.
  • the film may contain an element derived from a molecule containing Si atoms such as carbon. It is also possible to employ a technique for removing impurities such as carbon by performing post-treatment such as heat treatment or plasma treatment on a film containing an element derived from a molecule containing Si atoms.
  • heat treatment is performed at a temperature of 800 ° C. to 1300 ° C.
  • a part or all of the film containing Hf and O and the film containing Si and O are mixed.
  • short-time annealing that is not in a thermal equilibrium state, such as flash lamp annealing or laser annealing, of about milliseconds to nanoseconds may be performed.
  • the mixing process is not limited to the heat treatment, and includes a case where the mixing process is performed due to an impact caused by deposited particles during deposition.
  • the mixing treatment can be performed a plurality of times at an arbitrary stage after the film containing Hf and O and the film containing Si and O are each deposited once or more.
  • the Hf concentration is high and the Si concentration is low on the side close to the block insulating film 25, and the Hf concentration is low on the side far from the block insulating film 25.
  • a compositional gradient with a high Si concentration occurs.
  • the concentration of Si or SiO 2 is 100% or the concentration of Hf or HfO 2 is 0% does not remain. If such a portion remains, the storage capability as a storage film will deteriorate.
  • the maximum value of Si concentration relative to Hf and Si is preferably 50% or less. This is because if the concentration of Si with respect to Hf and Si exceeds 50%, it becomes difficult to produce a cubic crystal structure of HfO 2 .
  • the minimum value of the Si concentration relative to Hf and Si is preferably 4% or more. This is because when the Si concentration relative to Hf and Si is less than 4%, it becomes difficult to produce a cubic crystal structure of HfO 2 .
  • the heat treatment for mixing the film containing Si and O and the film containing Hf and O removes impurities such as carbon contained in the film containing Si and O and the film containing Hf and O. It may also serve as a heat treatment for the purpose.
  • the heat treatment for mixing the film containing Si and O and the film containing Hf and O is performed by forming a tunnel film or the like after forming the film containing Si and O or the film containing Hf and O. It can also be performed at an appropriate stage in the subsequent process, such as after film formation.
  • Subsequent processes (such as a process of forming the charge storage insulating film 26 and the tunnel insulating film 27) are the same as those in the second embodiment, and thus description thereof is omitted.
  • the cubic HfO 2 component is small as compared with the charge storage film manufactured by the method of the second embodiment.
  • deterioration of the film can be suppressed.
  • a region rich in cubic HfO 2 can be set at a position where the charge center should be guided. is there.
  • a film containing Si and O is formed.
  • a film containing Si and O instead of a film containing Si and O, a film containing Si and not containing O may be formed.
  • the block insulating film 25 is formed. Thereafter, a charge storage insulating film 26 is formed on the surface of the block insulating film 25.
  • a method for forming the charge storage insulating film 26 of the present embodiment will be described.
  • a film containing silicon (Si) and oxygen (O) is formed on the surface of the block insulating film 25.
  • This film is formed by, for example, the ALD method.
  • various film forming methods included in the category of the CVD method can be used. Specifically, various film forming methods (hot wall thermal CVD method, APCVD method, LPCVD method,..., Etc.) included in the category of the CVD method shown in the second embodiment can be used.
  • the molecules containing various Si atoms shown in the second embodiment are used. Can be used. One or more of these molecules can be used. Molecules constituting these materials can be easily vaporized, and a thin film containing silicon can be formed by introducing vaporized molecules in the vicinity of the substrate.
  • the molecule containing oxygen those shown in the second embodiment can be used.
  • the film may contain an element derived from a molecule containing Si atoms such as carbon. It is also possible to employ a technique for removing impurities such as carbon by performing post-treatment such as heat treatment or plasma treatment on a film containing an element derived from a molecule containing Si atoms.
  • a film containing hafnium (Hf) and oxygen (O) is formed by, for example, an ALD method.
  • various film forming methods included in the category of the CVD method can be used. Specifically, various film forming methods (hot wall thermal CVD method, APCVD method, LPCVD method,..., Etc.) included in the category of the CVD method shown in the second embodiment can be used.
  • the molecules containing various Hf atoms shown in the second embodiment can be used.
  • One or more of these molecules can be used.
  • the molecules constituting these materials can be easily vaporized, and a thin film containing hafnium can be formed by introducing vaporized molecules in the vicinity of the substrate.
  • the molecule containing oxygen those shown in the second embodiment can be used.
  • the film may contain a molecule-derived element containing Hf atoms such as carbon. It is also possible to employ a technique for removing impurities such as carbon by performing post-treatment such as heat treatment or plasma treatment on a film containing an element derived from a molecule containing Hf atoms.
  • the ratio of oxygen to Hf is preferably smaller than the stoichiometric ratio.
  • a process in which oxygen becomes a stoichiometric ratio is generally controlled. Excellent. Therefore, oxygen relative to Hf may have a stoichiometric ratio.
  • a film containing silicon (Si) and oxygen (O) is formed by, for example, an ALD method.
  • various film forming methods included in the category of the CVD method can be used. Specifically, various film forming methods (hot wall thermal CVD method, APCVD method, LPCVD method,..., Etc.) included in the category of the CVD method shown in the second embodiment can be used.
  • the molecules containing various Si atoms shown in the second embodiment are used. Can be used. One or more of these molecules can be used. Molecules constituting these materials can be easily vaporized, and a thin film containing silicon can be formed by introducing vaporized molecules in the vicinity of the substrate.
  • the molecule containing oxygen those shown in the second embodiment can be used.
  • the film may contain an element derived from a molecule containing Si atoms such as carbon. It is also possible to employ a technique for removing impurities such as carbon by performing post-treatment such as heat treatment or plasma treatment on a film containing an element derived from a molecule containing Si atoms.
  • heat treatment is performed at a temperature of 800 ° C. to 1300 ° C.
  • a part or all of the film containing Hf and O and the film containing Si and O are mixed.
  • short-time annealing that is not in a thermal equilibrium state, such as flash lamp annealing or laser annealing, of about milliseconds to nanoseconds may be performed.
  • the mixing process is not limited to the heat treatment, and includes a case where the mixing process is performed due to an impact caused by deposited particles during deposition.
  • the mixing treatment can be performed a plurality of times at an arbitrary stage after the film containing Hf and O and the film containing Si and O are each deposited once or more.
  • the Si concentration is high and the Hf concentration is low on both the side close to the block insulating film 25 and the side close to the tunnel insulating film 27 in the film thickness direction.
  • a compositional gradient occurs in the center such that the Hf concentration is high and the Si concentration is low.
  • the concentration of Si or SiO 2 is 100% or the concentration of Hf or HfO 2 is 0% does not remain. If such a portion remains, the storage capability as a storage film will deteriorate.
  • the maximum value of Si concentration relative to Hf and Si is preferably 50% or less. This is because if the concentration of Si with respect to Hf and Si exceeds 50%, it becomes difficult to produce a cubic crystal structure of HfO 2 .
  • the minimum value of the Si concentration relative to Hf and Si is preferably 4% or more. This is because when the Si concentration relative to Hf and Si is less than 4%, it becomes difficult to produce a cubic crystal structure of HfO 2 .
  • the heat treatment for mixing the film containing Si and O and the film containing Hf and O removes impurities such as carbon contained in the film containing Si and O and the film containing Hf and O. It may also serve as a heat treatment for the purpose.
  • the heat treatment for mixing the film containing Si and O and the film containing Hf and O is performed by forming a tunnel film or the like after forming the film containing Si and O or the film containing Hf and O. It can also be performed at an appropriate stage in the subsequent process, such as after film formation.
  • Subsequent processes (such as a process of forming the charge storage insulating film 26 and the tunnel insulating film 27) are the same as those in the second embodiment, and thus description thereof is omitted.
  • the charge storage insulating film manufactured in this way has a small amount of cubic HfO 2 component compared to the charge storage film manufactured by the method of the second embodiment, but the charge center because of the large amount of Si on the block insulating film side.
  • the holding characteristic can be improved by the position shift, and an advantage that deterioration of the tunnel insulating film can be suppressed because there is much Si on the tunnel insulating film side.
  • a film containing Si and O is formed.
  • a film containing Si and O instead of a film containing Si and O, a film containing Si and not containing O may be formed.
  • a film containing Si and O and a film containing Hf and O may be deposited twice or more, and then mixed by heat treatment or the like.
  • the mixing process is not limited to the heat treatment, and includes a case where the mixing process is performed due to an impact caused by deposited particles during deposition.
  • the mixing treatment can be performed a plurality of times at an arbitrary stage after the film containing Si and O and the film containing Hf and O are each deposited at least once.
  • the charge storage insulating film manufactured in this way may have a problem that the film formation takes time and costs increase compared to the charge storage insulating film manufactured as in the first embodiment.
  • the optimum film forming conditions for each component can be adopted instead of the film forming conditions at the compromise between the optimum conditions for the deposition of the Hf component and the optimum conditions for the deposition of the Si component.
  • a film containing Si and O and a film containing Hf, Si and O and containing Hf as a main component are each deposited at least once, and then mixed by heat treatment or the like. You may go.
  • the mixing process is not limited to the heat treatment, and includes a case where the mixing process is performed due to an impact caused by deposited particles during deposition.
  • the mixing process is performed after depositing a film containing Si and O and a film containing Hf, Si, and O and mainly containing Hf at least once to deposit the charge storage insulating film 26. It is also possible to carry out a plurality of times at an arbitrary stage.
  • the charge storage insulating film manufactured in this way may have a problem that the film formation takes time and costs increase compared to the charge storage insulating film manufactured as in the first embodiment.
  • a method of adjusting the Si concentration in the film containing Hf as a main component can be obtained as a mixing condition of the Hf component and the Si component.
  • a film containing Si, Hf and O and containing Si as a main component and a film containing Hf and O are deposited at least once, and then mixed by heat treatment or the like. You may go.
  • the mixing process is not limited to the heat treatment, and includes a case where the mixing process is performed due to an impact caused by deposited particles during deposition. Further, the mixing process is performed after depositing a film containing Si, Hf and O and containing Si as a main component and a film containing Hf and O at least once each for depositing the charge storage insulating film 26. It is also possible to carry out a plurality of times at an arbitrary stage.
  • the charge storage film manufactured in this way may have a problem that the film formation takes time and costs increase compared to the charge storage insulating film manufactured as in the first embodiment.
  • As a mixing condition of the Hf component and the Si component there is an advantage that a method of adjusting the Hf concentration in the film containing Si as a main component can be obtained.
  • the oxygen composition is the stoichiometric ratio or smaller than the stoichiometric ratio, but the oxygen composition is the stoichiometric ratio.
  • the ratio may be exceeded.
  • an oxidation method using plasma an oxygen implantation method using an ion implantation method, a method using oxygen atoms or atomic groups that are chemically active from O 2 molecules, a block insulating film is prepared in a peroxidized state, Various methods are possible, such as a method of oxidizing the charge storage insulating film by heat treatment.
  • the hafnium oxide included in the charge storage insulating film 26 may include a monoclinic region to some extent in addition to the cubic region.
  • various semiconductor substrates such as a substrate made of polycrystalline silicon, a SiGe substrate, and an InP substrate can be used. Since it is necessary to form a peripheral integrated circuit for driving the nonvolatile semiconductor memory device on the substrate, it is preferable to use a semiconductor. However, a method of externally attaching a peripheral circuit without forming a peripheral integrated circuit on the substrate is also possible. Further, it is possible to form the peripheral circuit on a semiconductor portion formed separately from the substrate without forming the peripheral integrated circuit on the substrate.
  • the holes may be formed so as not to reach the substrate insulating film 22 as shown in FIG. 17, or the holes may reach the substrate insulating film 22 as shown in FIG. You may form so that it may reach. Further, as shown in FIG. 21, the holes may be formed so as to penetrate the substrate insulating film 22 and reach the substrate 21.
  • FIG. 22 is a cross-sectional view schematically showing a basic configuration of a semiconductor device (charge trap type nonvolatile semiconductor memory device) according to the sixth embodiment of the present invention.
  • An insulating film 31 and a semiconductor channel layer 32 are each formed a plurality of times on the semiconductor substrate. For example, after forming an insulating film on a semiconductor substrate by a method such as thermal oxidation, a polycrystalline or amorphous Si layer is formed. Thereafter, an insulating film such as SiO 2 is formed by a method such as CVD. Further, a process of forming a polycrystalline or amorphous Si layer and a process of forming an insulating film such as SiO 2 by a method such as CVD are repeated a plurality of times.
  • the stacked structure of the insulating film 31 and the semiconductor channel layer 32 is etched to form a structure in which the stacked structure of the insulating film 31 and the semiconductor channel layer 32 remains in a strip shape on the substrate.
  • a tunnel insulating film 33 is formed on the side surface of the strip-shaped laminated structure.
  • a charge storage insulating film 34 is formed, and a block insulating film 35 is formed.
  • the charge storage insulating film 34 the same material as in the second to fifth embodiments can be used.
  • a nonvolatile semiconductor memory in which a plurality of nonvolatile semiconductor memory elements are stacked on a substrate and has a high-performance charge storage insulating film similar to those in the second to fifth embodiments. It becomes possible to form.

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  • Semiconductor Memories (AREA)

Abstract

L'invention concerne un dispositif semiconducteur présentant d'excellentes propriétés d'écriture et d'effacement ainsi que d'excellentes propriétés de stockage de charge. Le dispositif semiconducteur met en œuvre une zone semiconductrice (11); une membrane isolante en tunnel (12) disposée sur une surface de la zone semiconductrice; une membrane isolante d'accumulation de charge (13) disposée sur une surface de la membrane isolante en tunnel et possédant un oxyde d'hafnium comprenant une zone cristalline cubique; une membrane isolante en bloc (14) disposée sur une surface de la membrane isolante d'accumulation de charge; et une électrode de grille de commande (15) disposée sur une surface de la membrane isolante en bloc.
PCT/JP2010/053572 2009-03-19 2010-03-04 Dispositif semiconducteur et son procédé de fabrication WO2010106922A1 (fr)

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JP2017059607A (ja) * 2015-09-15 2017-03-23 株式会社東芝 半導体装置
JP2022533516A (ja) * 2019-05-09 2022-07-25 インテル・コーポレーション コンタクトの高さの差が大きいメモリ用途のための非導電性エッチングストップ構造
WO2021099885A1 (fr) * 2019-11-21 2021-05-27 株式会社半導体エネルギー研究所 Dispositif à semi-conducteur et appareil électronique
WO2021144661A1 (fr) * 2020-01-17 2021-07-22 株式会社半導体エネルギー研究所 Appareil à semi-conducteurs, procédé de commande d'appareil à semi-conducteurs et dispositif électronique
US11985827B2 (en) 2020-01-17 2024-05-14 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, driving method of semiconductor device, and electronic device
WO2021181455A1 (fr) * 2020-03-09 2021-09-16 キオクシア株式会社 Dispositif de stockage à semi-conducteurs et procédé de fabrication de dispositif de stockage à semi-conducteurs
US11355511B2 (en) 2020-03-19 2022-06-07 Kioxia Corporation Semiconductor memory device

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