JP2017059607A - 半導体装置 - Google Patents
半導体装置 Download PDFInfo
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- JP2017059607A JP2017059607A JP2015181381A JP2015181381A JP2017059607A JP 2017059607 A JP2017059607 A JP 2017059607A JP 2015181381 A JP2015181381 A JP 2015181381A JP 2015181381 A JP2015181381 A JP 2015181381A JP 2017059607 A JP2017059607 A JP 2017059607A
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 99
- 239000000758 substrate Substances 0.000 claims abstract description 38
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- 238000010586 diagram Methods 0.000 description 15
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- 229910004298 SiO 2 Inorganic materials 0.000 description 2
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 2
- 229910000577 Silicon-germanium Inorganic materials 0.000 description 2
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- 229910021193 La 2 O 3 Inorganic materials 0.000 description 1
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- 229910005889 NiSix Inorganic materials 0.000 description 1
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- 229910052759 nickel Inorganic materials 0.000 description 1
- 229910021334 nickel silicide Inorganic materials 0.000 description 1
- RUFLMLWJRZAWLJ-UHFFFAOYSA-N nickel silicide Chemical compound [Ni]=[Si]=[Ni] RUFLMLWJRZAWLJ-UHFFFAOYSA-N 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
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- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 1
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- H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
- H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
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- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42384—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
- H01L29/42392—Gate electrodes for field effect devices for field-effect transistors with insulated gate for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor fully surrounding the channel, e.g. gate-all-around
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- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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Abstract
Description
図1は、第1の実施の形態の不揮発性半導体記憶装置100の構造の一例を模式的に示す斜視図である。不揮発性半導体記憶装置100は、メモリセルアレイMR、ワード線駆動回路12、ソース側選択ゲート線駆動回路13、ドレイン側選択ゲート線駆動回路14、センスアンプ15、ワード線WL、ソース側選択ゲート線SGS、ドレイン側選択ゲート線SGD、ビット線BLを有している。
なお、メモリセルアレイMR内の層間絶縁層21と導電層22との積層体は、データ消去の最小単位であるブロック毎に分断されている。分断の境界においてはトレンチTbが形成されており、このトレンチTbには、図示しない層間絶縁層が埋め込まれ、更にその層間絶縁層を貫通して前述したソースコンタクトLIが形成されている。このソースコンタクトLIは、その下端が半導体基板SBに接続される一方、その上端がソース線SLに接続されている。
このフランジ部203Fは、トランジスタTrがY方向に沿って配列されている場合、X方向に延びるように形成されるのが好適である(図8参照)。ただし、フランジ部203Fの長手方向はX方向に限定されるものではなく、上層配線17の向きやトランジスタTrの配列に応じて適宜変更することは可能である。
なお、階段状配線部CRは、前述したように、メモリセルアレイMRのX方向の側部だけでなく、Y方向の側部にも形成することができる。
最初に、図10Aに示すように、階段状配線部CRの端部(最下層の導電層22の端部付近)に、トランジスタTrを形成するためのトレンチT1を、マスクM1を用いた反応性イオンエッチング(RIE)により形成する。図10Aの紙面垂直方向沿って多数のトレンチT1が形成される。ただし、トレンチT1は、その底部が半導体基板SBに到達しない程度の高さまで掘り込まれる。なお、このトレンチT1と、コンタクトプラグ16を埋め込むためのトレンチとを同時に形成することも可能である。
次に、第2の実施の形態に係る半導体記憶装置を、図11を参照して説明する。図11は、この第2の実施の形態の半導体装置のメモリセルアレイMR及び階段状配線部CRの断面図を示す。装置の概略構成は第1の実施の形態のそれと略同一であるので、重複する説明は省略する。
この第2の実施の形態では、第1の実施の形態のトランジスタTrと略同一の構造を有するトランジスタTr2が、上層配線17と導電層22との間に接続されている。この点、第1の実施の形態のトランジスタTrは、その下端が基板SBに接続されているのと異なっている。この実施の形態によっても、第1の実施の形態と略同一の効果を奏することができる。なお、第1の実施の形態のトランジスタTrと、第2の実施の形態のトランジスタTr2とを1つの装置中で併存させることも可能である。
以上、本発明のいくつかの実施の形態を説明したが、これらの実施の形態は、例として提示したものであり、発明の範囲を限定することは意図していない。これら新規な実施の形態は、その他の様々な形態で実施されることが可能であり、発明の要旨を逸脱しない範囲で、種々の省略、置き換え、変更を行うことができる。これら実施の形態やその変形は、発明の範囲や要旨に含まれるとともに、特許請求の範囲に記載された発明とその均等の範囲に含まれる。
Claims (10)
- 基板上に前記基板の上面と交差する第1の方向に配列された複数の第1導電層と、
前記第1導電層の端部の位置を互いに異ならせて構成された階段状配線部と、
前記階段状配線部に電気的に接続されるトランジスタと
を備え、
前記トランジスタは、
前記第1の方向を長手方向として延びるチャネル層と、
前記チャネル層の周囲に配置されたゲート絶縁膜と、
前記ゲート絶縁膜の周囲に配置されたゲート電極層と
を備えたことを特徴とする、半導体装置。 - 前記チャネル層は、酸化物半導体を含む、請求項1記載の半導体装置。
- 前記ゲート電極層は前記基板の上面に水平な方向に沿って延びる接続部を備える、請求項1記載の半導体装置。
- 前記チャネル層の下端部は、前記基板に接続される、請求項1記載の半導体装置。
- 前記チャネル層の下端部は、対応する前記ゲート電極層の下端部よりも前記基板側に位置する、請求項1記載の半導体装置。
- 前記チャネル層の下端部は、前記階段状配線部に接続される、請求項1記載の半導体装置。
- 3次元状に配列されたメモリセルを含むメモリセルアレイを更に備え、
前記第1の方向に配列された前記メモリセルの各々は、前記第1の方向に配列された複数の前記第1導電層のいずれかに接続される、請求項1記載の半導体装置。 - 前記階段状配線部から前記第1の方向に延びる第2導電層と、
前記第2導電層の上端に接続される上層配線と
を更に備え、
前記チャネル層は、前記第2導電層及び前記上層配線を介して前記階段状配線部と電気的に接続される、請求項1記載の半導体装置。 - 前記チャネル層は、酸化物半導体を含む、請求項8記載の半導体装置。
- 前記ゲート電極層は前記基板に水平な方向に沿って延びる接続部を備える、請求項8記載の半導体装置。
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