WO2010047063A1 - Transistor à couches minces comportant un film semi-conducteur d’oxyde d’indium cristallin haute pureté, et procédé de fabrication du transistor à couches minces - Google Patents

Transistor à couches minces comportant un film semi-conducteur d’oxyde d’indium cristallin haute pureté, et procédé de fabrication du transistor à couches minces Download PDF

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WO2010047063A1
WO2010047063A1 PCT/JP2009/005384 JP2009005384W WO2010047063A1 WO 2010047063 A1 WO2010047063 A1 WO 2010047063A1 JP 2009005384 W JP2009005384 W JP 2009005384W WO 2010047063 A1 WO2010047063 A1 WO 2010047063A1
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thin film
film transistor
semiconductor film
indium oxide
oxide
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PCT/JP2009/005384
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English (en)
Japanese (ja)
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井上一吉
笠見雅司
矢野公規
笘井重和
川嶋浩和
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出光興産株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes

Definitions

  • the present invention relates to a thin film transistor having a semiconductor film made of high-purity crystalline indium oxide and a method for manufacturing the same.
  • silicon-based semiconductor films are mainly used as switching elements such as thin film transistors (TFTs) for driving the above display devices. This is because, in addition to the stability and workability of the silicon-based thin film, the switching speed is fast.
  • This silicon-based thin film is generally produced by a chemical vapor deposition method (CVD) method.
  • the switching speed is relatively slow, and there is a problem that an image cannot be displayed when displaying a high-speed moving image or the like.
  • the switching speed is relatively fast, but a high temperature of 800 ° C. or higher, heating with a laser, etc. are necessary for crystallization. Cost.
  • the silicon-based thin film has excellent performance as a voltage element, a change in the characteristics with time is a problem when a current is passed.
  • Sputtering targets composed of indium oxide, gallium oxide, and zinc oxide, as well as zinc oxide and oxide as materials for obtaining a transparent semiconductor film that is more stable than a silicon-based thin film and has a light transmittance equivalent to that of an ITO film.
  • a transparent semiconductor thin film made of magnesium has been proposed (for example, Patent Document 1).
  • a transparent semiconductor film made of indium oxide, gallium oxide and zinc oxide, or zinc oxide and magnesium oxide has a very fast etching property with a weak acid.
  • the metal thin film on the transparent semiconductor film may be etched at the same time. It was inappropriate.
  • Patent Document 2 describes an indium oxide semiconductor film having a bixbyite structure in which a positive divalent metal oxide is contained in indium oxide. Attempts have been made to reduce the carrier concentration by including a positive divalent metal oxide. However, in the case of a positive divalent metal oxide, an impurity order may be formed in the band gap of the energy band structure of the bixbite structure, which may reduce the mobility.
  • Patent Document 3 describes a thin film transistor using a crystalline indium oxide thin film.
  • the trap density in the channel portion may increase. For this reason, there are problems that the S value cannot be reduced sufficiently and that a normally-on transistor is formed. Further, when the trap density in the thin film is high, there is a problem that the off-current value cannot be sufficiently reduced by the trap.
  • Patent Document 3 describes that the off-current value can be reduced by setting the thickness of the indium oxide thin film to 20 nm. However, it is technically difficult to control the film thickness to 20 nm to form a film uniformly and in a large area. For this reason, there is a possibility that the characteristics of the thin film transistor vary.
  • An object of the present invention is to provide a thin film transistor using a semiconductor film made of crystalline indium oxide and having a high performance by reducing the trap density of the semiconductor film.
  • the present inventors have found that impurities in a semiconductor film made of crystalline indium oxide, specifically, a metal element having a positive tetravalence or more affects the trap density of the semiconductor film.
  • the inventors have found that a high-performance thin film transistor can be obtained by setting the content of the metal element to a predetermined value or less, thereby completing the present invention.
  • a thin film transistor having a crystalline indium oxide semiconductor film, wherein the content of a metal element having a positive tetravalent or higher valence relative to all metal elements contained in the semiconductor film is 0.1 atomic ppm or less. 4). 4.
  • 9. The method for producing a thin film transistor according to 8, wherein the indium oxide target has a purity of 99.995 atomic% or more.
  • 10. The method for producing a thin film transistor according to 8 or 9, wherein the film forming step is performed by sputtering, and an oxygen concentration in an atmosphere during sputtering is 5 to 20% by volume.
  • 11. The method for producing a thin film transistor according to any one of 8 to 10, wherein the semiconductor film is heat-treated at 150 to 450 ° C. for 0.1 to 1200 minutes in the presence of oxygen.
  • the impurity concentration of the crystalline indium oxide thin film is low, the trap density in the thin film, particularly the channel portion, can be reduced. As a result, the S value can be sufficiently reduced.
  • FIG. 6 is a diagram showing an output curve of a thin film transistor manufactured in Example 1.
  • FIG. 6 is a diagram showing a transfer curve of a thin film transistor manufactured in Example 1.
  • FIG. 6 is a schematic cross-sectional view of an etch stopper type thin film transistor fabricated in Example 3.
  • FIG. 10 is a diagram showing a transfer curve of a thin film transistor manufactured in Example 5.
  • the thin film transistor (TFT) of the present invention has a crystalline indium oxide semiconductor film, and the content of positive tetravalent or higher metal elements with respect to all metal elements contained in the semiconductor film is 10 atomic ppm or less. .
  • FIG. 1 is a schematic cross-sectional view showing an embodiment of a thin film transistor of the present invention.
  • the thin film transistor 1 has a gate electrode 20 sandwiched between a substrate 10 and an insulating film 30, and a semiconductor film 40 is stacked on the gate insulating film 30 as an active layer. Further, a source electrode 50 and a drain electrode 52 are provided so as to cover the vicinity of the end of the semiconductor film 40. A channel portion 60 is formed in a portion surrounded by the semiconductor film 40, the source electrode 50 and the drain electrode 52. 1 is a so-called channel etch type thin film transistor.
  • the thin film transistor of the present invention is not limited to a channel etch type thin film transistor, and an element configuration known in this technical field can be adopted.
  • FIG. 2 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention.
  • the thin film transistor 2 is an etch stopper type thin film transistor.
  • the thin film transistor 2 has the same configuration as the thin film transistor 1 described above except that an etch stopper 70 is formed so as to cover the channel portion 60.
  • a source electrode 50 and a drain electrode 52 are provided so as to cover the vicinity of the end of the semiconductor film 40 and the vicinity of the end of the etch stopper 70.
  • a thin film made of high-purity crystalline indium oxide is used for the semiconductor film 40.
  • high purity means that the crystalline indium oxide thin film contains substantially no positive tetravalent or higher-valent metal element as an impurity.
  • the content of positive tetravalent or higher metal elements in all metal elements forming the semiconductor film is 10 atomic ppm or less.
  • Impurities in the thin film contribute to electron scattering and cause a decrease in mobility. If the impurity concentration is low, scattering can be suppressed and high mobility inherent in indium oxide can be maintained. In addition, the crystal structure may be disturbed by impurities, so that oxygen vacancies cannot be sufficiently reduced, and a thin film transistor exhibiting a normally-on operation may be obtained.
  • a crystalline indium oxide semiconductor film having an extremely low impurity concentration is used, a high-performance thin film transistor that is normally off, has high mobility, low off-current value, and low S value and high operational stability. Is obtained.
  • normally-off is defined as a case where the threshold voltage value is negative (positive). The threshold voltage is determined from the X-intercept of the transfer curve (Id-Vg) graph.
  • the carrier density of the semiconductor film near room temperature can be kept below 2 ⁇ 10 +17 cm ⁇ 3 .
  • the carrier density of the semiconductor film is preferably less than 2 ⁇ 10 +17 cm ⁇ 3 near room temperature. If the carrier density is 2 ⁇ 10 +17 cm ⁇ 3 or more, the TFT may not be driven. Even when the TFT is driven, the threshold voltage may be negatively large and normally on, or the On / Off ratio may be small.
  • a metal element having a positive tetravalence or more and a metal element having a positive divalent or less are present as metal oxides in the thin film.
  • the positive tetravalent or higher metal oxide contained in the semiconductor film include positive oxides such as titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and manganese oxide.
  • Examples of the metal oxide having a positive or lower valence included in the semiconductor film include a positive or lower valent metal such as lithium oxide, sodium oxide, potassium oxide, rubidium oxide, cesium oxide, magnesium oxide, calcium oxide, strontium oxide, and barium oxide.
  • a positive or lower valent metal such as lithium oxide, sodium oxide, potassium oxide, rubidium oxide, cesium oxide, magnesium oxide, calcium oxide, strontium oxide, and barium oxide.
  • sodium oxide, potassium oxide, magnesium oxide, calcium oxide, and zinc oxide are preferably strictly controlled.
  • the content of the metal element (M4) of the metal oxide of positive tetravalent or higher with respect to all the metal elements of the semiconductor film is 10 atomic ppm or less, preferably 5 atomic ppm or less, more preferably 1 It is atomic ppm or less, more preferably 0.5 atomic ppm or less, and particularly preferably 0.1 atomic ppm or less.
  • the carrier density may be 2 ⁇ 10 +17 cm ⁇ 3 or more, and the TFT characteristics may not be operated. Even if the TFT is driven, the threshold voltage may increase negatively, indicating normally-on, or the off-current value may increase and the On / Off ratio may decrease. Further, the trap density in the thin film and / or the interface between the insulating film and the semiconductor film may increase, and the S value may increase.
  • the Sn content is particularly high, the oxidizing power of the element is strong, so the carrier density increases, and even when driven as a TFT, the threshold voltage increases negatively, indicating normally-on, or off-current value May increase and the On / Off ratio may decrease. Further, the trap density in the thin film and / or the interface between the insulating film and the semiconductor film may increase, and the S value may increase.
  • the Sn content is preferably 1 atom ppm or less, more preferably 0.5 atom ppm or less, and particularly preferably 0.1 atom ppm or less.
  • the content rate of the metal element (M2) of the metal oxide of a positive bivalent or less with respect to all the metal elements of a semiconductor film is 50 atomic ppm or less. If the atomic ratio exceeds 50 atomic ppm, the mobility may be low, and the TFT characteristics may not work. Further, the trap density in the thin film and / or the interface between the insulating film and the semiconductor film may increase, and the S value may increase.
  • the ratio of the metal element (M2) is more preferably 10 atomic ppm or less, further preferably 5 atomic ppm or less, and particularly preferably 1 atomic ppm or less.
  • the ratio of the metal element (M) can be obtained by measuring the abundance of each element by ICP-Mass (Inductively Coupled Plasma Mass) measurement.
  • the metal element (M) ratio can be implemented, for example, by adjusting the amount of each element in the sputtering target used when forming the semiconductor film.
  • the composition of the semiconductor film substantially matches the composition of the sputtering target.
  • the use of the crystalline indium oxide semiconductor film can suppress the etching of the semiconductor film when the source electrode 50 and the drain electrode 52 are etched. Further, the durability of the TFT can be increased.
  • the “crystalline film” is a film that can be confirmed by confirming a crystal peak by X-ray diffraction.
  • the crystalline film may be any of a single crystal film, an epitaxial film, and a polycrystalline film, and is preferably an epitaxial film and a polycrystalline film because industrial production is easy and the area can be increased. A polycrystalline film is preferred.
  • the polycrystalline film is preferably made of nanocrystals.
  • the average crystal grain size determined by using Scherrer's equation from X-ray diffraction is usually 500 nm or less, preferably 300 nm or less, more preferably 150 nm or less, and even more preferably 80 nm or less. If it is larger than 500 nm, there is a possibility that variation when the transistor is miniaturized becomes large.
  • the substrate can be used for the substrate, gate electrode, gate insulating film, source / drain electrode, and the like, and are not particularly limited.
  • a metal thin film such as Al, Cu, or Au can be used for each electrode, and an oxide thin film such as a silicon oxide film or a hafnium oxide film can be used for the gate insulating film.
  • the manufacturing method of the present invention includes a film forming step of forming an indium oxide semiconductor film, a step of oxidizing the semiconductor film, and / or a step of crystallizing. Note that components such as a gate electrode, a gate insulating film, and a source / drain electrode can be formed by a known method.
  • a gate electrode made of a metal thin film such as Al, Cu, or Au is formed on a substrate, and an oxide thin film made of a silicon oxide film, a hafnium oxide film, or the like is formed thereon as a gate insulating film.
  • a metal mask is attached to form a semiconductor film made of an indium oxide film only in necessary portions.
  • a source / drain electrode is formed in a necessary portion using a metal mask, whereby a thin film transistor can be manufactured.
  • the semiconductor film can be formed by sputtering, ion plating, vapor deposition, or the like. Of these, the sputtering method is preferable. In sputtering, a method using a sintered target is preferable. Specifically, a high-purity indium oxide sintered target of 99.99 atomic% or more, or 99.995 atomic% (4N) or more is preferable. A sintered target can be manufactured by a well-known method in this technical field. By using a high-purity indium oxide sintered compact target, a crystalline indium oxide thin film having an extremely low impurity concentration can be obtained.
  • the sputtering conditions can be appropriately adjusted according to the target to be used, the thickness of the semiconductor film, and the like.
  • As the sputtering method an RF sputtering method, a DC sputtering method, or an AC sputtering method can be used.
  • the DC sputtering method and the AC sputtering method are preferable because the film forming speed is high.
  • Oxygen is preferably present during film formation. By allowing oxygen to be present during sputtering, it can be effectively oxidized in the oxidation process of the next step.
  • the oxygen concentration in the atmosphere during sputtering is preferably 5 to 20% by volume, more preferably 7 to 17%, and particularly preferably 8 to 14% by volume.
  • a step of oxidizing the thin film and / or a step of crystallizing the thin film are performed.
  • a lamp annealing device, a laser annealing device, a hot air heating device, a contact heating device, or the like can be used in the presence of oxygen.
  • the semiconductor film is preferably heat-treated in the presence of oxygen at 150 to 450 ° C. for 0.1 to 1200 minutes. If it is less than 150 ° C., the semiconductor film may not be sufficiently crystallized, and if it exceeds 450 ° C., the substrate and the semiconductor film may be damaged.
  • the heat treatment temperature is more preferably 180 ° C. to 350 ° C., and particularly preferably 200 ° C. to 300 ° C. If the heat treatment time is less than 0.1 minutes, the heat treatment time may be too short and the crystallization of the film may be insufficient. If it exceeds 1200 minutes, it takes too much time and is not productive.
  • the heat treatment time is more preferably 1 minute to 600 minutes, and particularly preferably 5 minutes to 60 minutes.
  • the crystallization and / or oxidation treatment of the semiconductor film may be performed immediately after the formation of the semiconductor film, or may be performed after the formation of other components such as source / drain electrodes.
  • the manufacturing method of the present invention is particularly suitable for a manufacturing method of a channel etch type thin film transistor. Since the semiconductor film of the present invention is crystalline, an etching process using photolithography can be adopted as a method for forming the source / drain electrodes and the channel portion from a metal thin film such as Al. That is, the etching solution for removing the metal thin film can selectively etch the metal thin film without etching the semiconductor film. An etch stopper type thin film transistor manufacturing method may also be used.
  • Example 1 (A) Production of Thin Film Transistor A channel etch type thin film transistor shown in FIG. 3 was produced. A conductive silicon substrate 10 with a thermal oxide film (SiO 2 film) having a thickness of 100 nm was used. The thermal oxide film functions as the gate insulating film 30 and the conductive silicon portion functions as the gate electrode 20.
  • SiO 2 film thermal oxide film
  • a target made of high-purity indium oxide having a purity of 4N or more manufactured by Shonan Electronics Materials Laboratory (total of positive tetravalent or more metal elements: Sn, Ti, Zr: 0.09 ppm (Sn : 0.02 ppm), and a metal element having a positive divalent value or less: total of Na, K, Mg, and Zn: 0.8 ppm) was used to form a semiconductor film 40 of 50 nm by sputtering.
  • the target impurity was measured by ICP-Mass (Inductively Coupled Plasma Mass).
  • Sputtering was performed by evacuating the back pressure to 5 ⁇ 10 ⁇ 4 Pa, then adjusting the pressure to 0.2 Pa while flowing argon 9.0 sccm and oxygen 1.0 sccm, and the distance between TS was 10 cm.
  • the substrate temperature was set to room temperature and the sputtering power was 100 W.
  • a metal mask is placed on the semiconductor film 40, and in the vicinity of both ends of the channel part 60, a channel part 60 having a gap (L) between the source and drain electrodes of 200 ⁇ m and a width (W) of 1000 ⁇ m is formed.
  • Gold was deposited to form the source electrode 50 and the drain electrode 52. Then, it heat-processed in the air at 300 degreeC for 1 hour in the hot-air heating furnace, and produced the thin-film transistor.
  • This thin film transistor has a field effect mobility of 60 cm 2 / V ⁇ sec, an On / Off ratio of 5 ⁇ 10 6 , a threshold voltage (Vth) of 7.1 V, and an S value of 1.1 V / dec. Thus, the thin film transistor exhibits normally-off characteristics. The output characteristics showed a clear pinch-off.
  • Table 1 shows the impurity amount of the target used for forming the semiconductor film, the element configuration, and the performance of the thin film transistor for the examples and comparative examples.
  • FIG. 4 shows the transfer curve between the drain voltage (Vds) and the same current (Ids) when the gate voltage (Vgs) is changed from -5V to 25V.
  • FIG. 5 shows the relationship between the gate voltage (Vgs) and the drain current (Ids).
  • the white circle line is a curve obtained by raising the drain current to the gate voltage by a power of 1/2
  • the black circle line is 4 is a curve showing a drain current with respect to a gate voltage. 4 and 5, “XE-Y” means X ⁇ 10 ⁇ Y .
  • 1.0E-05 is 1.0 ⁇ 10 ⁇ 5 .
  • Example 2 As a sputtering target, a target composed of high-purity indium oxide (a total of positive tetravalent metal elements: Sn, Ti, Zr: 0.4 ppm (Sn: 0.1 ppm), a positive divalent or lower metal element: Na, A thin film transistor was manufactured in the same manner as in Example 1 except that the total of K, Mg, and Zn: 3 ppm), manufactured by Shonan Electronic Materials Laboratory] was used. Field effect mobility of the thin film transistor is 52cm 2 / V ⁇ sec, On / Off ratio is 10 6, Vth is 5.5V, S value is 1.5V / dec. Thus, the thin film transistor exhibits normally-off characteristics. The output characteristics showed a clear pinch-off. The semiconductor film was crystalline.
  • Comparative Example 1 As a sputtering target, a target made of indium oxide with a purity of 3N (total tetravalent or higher metal elements: Sn, Ti, Zr total: 120 ppm (Sn: 30 ppm), positive divalent or lower metal elements: Na, K, Mg , Zn was used in the same manner as in Example 1 except that the total amount of Zn was 60 ppm).
  • This thin film transistor has a field effect mobility of 46 cm 2 / V ⁇ sec, an On / Off ratio of 2.5 ⁇ 10 5 , a Vth of ⁇ 1.2 V, and an S value of 2.4 V / dec. Thus, the thin film transistor exhibits normally-on characteristics. The output characteristics showed a clear pinch-off.
  • the semiconductor film was crystalline.
  • Example 3 The etch stopper type thin film transistor shown in FIG. 6 was manufactured by a photoresist method.
  • a target made of high-purity indium oxide (a total of positive tetravalent or higher metal elements: Sn, Ti, Zr) : 0.09 ppm (Sn: 0.02 ppm), and a metal element having a positive divalent value or less: Total of Na, K, Mg, Zn: 0.8 ppm) is used to form a 50 nm semiconductor film 40 by sputtering. did.
  • SiO 2 was deposited by RF sputtering at 300 nm under conditions of oxygen partial pressure of 15% and argon of 85%.
  • a resist was applied on the semiconductor film with SiO 2 and prebaked at 80 ° C. for 15 minutes. Thereafter, the resist film was irradiated with UV light (light intensity: 300 mJ / cm 2 ) through a mask, and then developed with 3 wt% tetramethylammonium hydroxide (TMAH). After washing with pure water, the resist film was post-baked at 130 ° C. for 15 minutes, and SiO 2 was etched by dry etching using CF 4 to form an etch stopper 70 having a desired shape.
  • TMAH 3 wt% tetramethylammonium hydroxide
  • a molybdenum metal film having a thickness of 300 nm was formed on the semiconductor film 40, the gate insulating film (thermal oxide film) 30, and the etch stopper 70.
  • a resist was applied to the molybdenum metal film, and prebaked at 80 ° C. for 15 minutes. Thereafter, the resist film was irradiated with UV light (light intensity: 300 mJ / cm 2 ) through a mask, and then developed with 3 wt% tetramethylammonium hydroxide (TMAH). After washing with pure water, the resist film was post-baked at 130 ° C. for 15 minutes to form a resist pattern having a desired source / drain electrode shape.
  • UV light light intensity: 300 mJ / cm 2
  • TMAH 3 wt% tetramethylammonium hydroxide
  • the substrate with a resist pattern was treated with a mixed acid of phosphoric acid / acetic acid / nitric acid to etch the molybdenum metal film, thereby forming the source electrode 50 and the drain electrode 52.
  • the portion of the semiconductor film 40 in contact with the gate insulating film 30 was also etched.
  • the resist was peeled off, washed with pure water, dried by air blowing, and a thin film transistor (a gap (L) between the source and drain electrodes of the channel portion 60 was 200 ⁇ m and a width (W) was 1000 ⁇ m) was produced. Thereafter, this thin film transistor was heat-treated at 300 ° C. for 1 hour in air in a hot air heating furnace.
  • This thin film transistor has a field effect mobility of 62 cm 2 / V ⁇ sec, an On-Off ratio of 3 ⁇ 10 7 , a Vth of 6.8 V, and an S value of 0.9 V / dec.
  • the thin film transistor exhibits normally-off characteristics.
  • the output characteristics showed a clear pinch-off.
  • the shift voltage (Vth) after applying a 20 V voltage to the gate electrode for 100 minutes was 0.25 V.
  • the semiconductor film was crystalline.
  • Example 4 A thin film transistor was manufactured in the same manner as in Example 3 except that the gap (L) between the source and drain electrodes of the channel portion 60 was 20 ⁇ m and the width (W) was 100 ⁇ m.
  • Example 5 A thin film transistor was manufactured in the same manner as in Example 4 except that the gap (L) between the source and drain electrodes of the channel portion 60 was 10 ⁇ m and the width (W) was 20 ⁇ m.
  • This thin film transistor has a field effect mobility of 36 cm 2 / V ⁇ sec, an On / Off ratio of 4.6 ⁇ 10 8 , a Vth of 3.2 V, and an S value of 0.40 V / dec.
  • the thin film transistor exhibits normally-off characteristics.
  • the output characteristics showed a clear pinch-off.
  • the shift voltage (Vth) after applying a 20V voltage to the gate electrode for 100 minutes was 0.16V.
  • the semiconductor film was crystalline.
  • a transfer curve of the thin film transistor manufactured in Example 5 is shown in FIG.
  • This thin film transistor has a field effect mobility of 27 cm 2 / V ⁇ sec, an On / Off ratio of 4 ⁇ 10 8 , a Vth of ⁇ 2.2 V, and an S value of 1.0 V / dec.
  • the thin film transistor exhibits normally-on characteristics.
  • the output characteristics showed a clear pinch-off.
  • the shift voltage (Vth) after applying 20V voltage to the gate electrode for 100 minutes was 0.38V.
  • the semiconductor film was crystalline.
  • the thin film transistor of Example 4 has the same channel length (L) and width (W) as those of the element described in Patent Document 3. Even in this case, a transistor having good transistor characteristics was obtained in the present invention.
  • the gap (L) between the source and drain electrodes of the thin film transistor of Example 5 is 10 ⁇ m, and the width (W) is 20 ⁇ m. Even when the channel width is narrowed, a transistor having good transistor characteristics is obtained in the present invention.
  • the thin film transistor of the present invention can be suitably used for sensors such as display panels, RFID tags, X-ray detector panels, fingerprint sensors, and photosensors.
  • the thin film transistor manufacturing method of the present invention is particularly suitable for a channel etch type thin film transistor manufacturing method.

Abstract

La présente invention concerne un transistor à couches minces comportant un film semi-conducteur d’oxyde d’indium cristallin, le rapport de la teneur en éléments métalliques ayant une valence supérieure ou égale à +4 aux éléments métalliques totaux contenus dans le film semi-conducteur étant inférieur ou égal à 10 ppm atm.
PCT/JP2009/005384 2008-10-23 2009-10-15 Transistor à couches minces comportant un film semi-conducteur d’oxyde d’indium cristallin haute pureté, et procédé de fabrication du transistor à couches minces WO2010047063A1 (fr)

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JPWO2013021632A1 (ja) * 2011-08-11 2015-03-05 出光興産株式会社 薄膜トランジスタ
JP2022024000A (ja) * 2011-09-29 2022-02-08 株式会社半導体エネルギー研究所 半導体装置

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JP5101719B2 (ja) 2010-11-05 2012-12-19 日東電工株式会社 透明導電性フィルム、その製造方法及びそれを備えたタッチパネル
JP5122670B2 (ja) 2010-11-05 2013-01-16 日東電工株式会社 透明導電性フィルムの製造方法
KR20200011610A (ko) 2012-11-08 2020-02-03 가부시키가이샤 한도오따이 에네루기 켄큐쇼 금속 산화물 막 및 금속 산화물 막의 형성 방법
TWI692110B (zh) * 2017-06-05 2020-04-21 日商凸版印刷股份有限公司 半導體裝置、顯示裝置、及濺鍍靶材

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007058248A1 (fr) * 2005-11-18 2007-05-24 Idemitsu Kosan Co., Ltd. Couche mince de semi-conducteur, procede de production de celle-ci et transistor a couches minces
JP2008130814A (ja) * 2006-11-21 2008-06-05 Canon Inc 薄膜トランジスタの製造方法
WO2008114588A1 (fr) * 2007-03-20 2008-09-25 Idemitsu Kosan Co., Ltd. Ice cible de pulvérisation, film semi-conducteur d'oxyde et dispositif semi-conducteur

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2007058248A1 (fr) * 2005-11-18 2007-05-24 Idemitsu Kosan Co., Ltd. Couche mince de semi-conducteur, procede de production de celle-ci et transistor a couches minces
JP2008130814A (ja) * 2006-11-21 2008-06-05 Canon Inc 薄膜トランジスタの製造方法
WO2008114588A1 (fr) * 2007-03-20 2008-09-25 Idemitsu Kosan Co., Ltd. Ice cible de pulvérisation, film semi-conducteur d'oxyde et dispositif semi-conducteur

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2013021632A1 (ja) * 2011-08-11 2015-03-05 出光興産株式会社 薄膜トランジスタ
JP2013084939A (ja) * 2011-09-29 2013-05-09 Semiconductor Energy Lab Co Ltd 半導体装置及び半導体装置の作製方法
JP2022024000A (ja) * 2011-09-29 2022-02-08 株式会社半導体エネルギー研究所 半導体装置

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