WO2010047063A1 - Thin film transistor having high-purity crystalline indium oxide semiconductor film, and method for manufacturing the thin film transistor - Google Patents

Thin film transistor having high-purity crystalline indium oxide semiconductor film, and method for manufacturing the thin film transistor Download PDF

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WO2010047063A1
WO2010047063A1 PCT/JP2009/005384 JP2009005384W WO2010047063A1 WO 2010047063 A1 WO2010047063 A1 WO 2010047063A1 JP 2009005384 W JP2009005384 W JP 2009005384W WO 2010047063 A1 WO2010047063 A1 WO 2010047063A1
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thin film
film transistor
semiconductor film
indium oxide
oxide
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PCT/JP2009/005384
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French (fr)
Japanese (ja)
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井上一吉
笠見雅司
矢野公規
笘井重和
川嶋浩和
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出光興産株式会社
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/45—Ohmic electrodes

Definitions

  • the present invention relates to a thin film transistor having a semiconductor film made of high-purity crystalline indium oxide and a method for manufacturing the same.
  • silicon-based semiconductor films are mainly used as switching elements such as thin film transistors (TFTs) for driving the above display devices. This is because, in addition to the stability and workability of the silicon-based thin film, the switching speed is fast.
  • This silicon-based thin film is generally produced by a chemical vapor deposition method (CVD) method.
  • the switching speed is relatively slow, and there is a problem that an image cannot be displayed when displaying a high-speed moving image or the like.
  • the switching speed is relatively fast, but a high temperature of 800 ° C. or higher, heating with a laser, etc. are necessary for crystallization. Cost.
  • the silicon-based thin film has excellent performance as a voltage element, a change in the characteristics with time is a problem when a current is passed.
  • Sputtering targets composed of indium oxide, gallium oxide, and zinc oxide, as well as zinc oxide and oxide as materials for obtaining a transparent semiconductor film that is more stable than a silicon-based thin film and has a light transmittance equivalent to that of an ITO film.
  • a transparent semiconductor thin film made of magnesium has been proposed (for example, Patent Document 1).
  • a transparent semiconductor film made of indium oxide, gallium oxide and zinc oxide, or zinc oxide and magnesium oxide has a very fast etching property with a weak acid.
  • the metal thin film on the transparent semiconductor film may be etched at the same time. It was inappropriate.
  • Patent Document 2 describes an indium oxide semiconductor film having a bixbyite structure in which a positive divalent metal oxide is contained in indium oxide. Attempts have been made to reduce the carrier concentration by including a positive divalent metal oxide. However, in the case of a positive divalent metal oxide, an impurity order may be formed in the band gap of the energy band structure of the bixbite structure, which may reduce the mobility.
  • Patent Document 3 describes a thin film transistor using a crystalline indium oxide thin film.
  • the trap density in the channel portion may increase. For this reason, there are problems that the S value cannot be reduced sufficiently and that a normally-on transistor is formed. Further, when the trap density in the thin film is high, there is a problem that the off-current value cannot be sufficiently reduced by the trap.
  • Patent Document 3 describes that the off-current value can be reduced by setting the thickness of the indium oxide thin film to 20 nm. However, it is technically difficult to control the film thickness to 20 nm to form a film uniformly and in a large area. For this reason, there is a possibility that the characteristics of the thin film transistor vary.
  • An object of the present invention is to provide a thin film transistor using a semiconductor film made of crystalline indium oxide and having a high performance by reducing the trap density of the semiconductor film.
  • the present inventors have found that impurities in a semiconductor film made of crystalline indium oxide, specifically, a metal element having a positive tetravalence or more affects the trap density of the semiconductor film.
  • the inventors have found that a high-performance thin film transistor can be obtained by setting the content of the metal element to a predetermined value or less, thereby completing the present invention.
  • a thin film transistor having a crystalline indium oxide semiconductor film, wherein the content of a metal element having a positive tetravalent or higher valence relative to all metal elements contained in the semiconductor film is 0.1 atomic ppm or less. 4). 4.
  • 9. The method for producing a thin film transistor according to 8, wherein the indium oxide target has a purity of 99.995 atomic% or more.
  • 10. The method for producing a thin film transistor according to 8 or 9, wherein the film forming step is performed by sputtering, and an oxygen concentration in an atmosphere during sputtering is 5 to 20% by volume.
  • 11. The method for producing a thin film transistor according to any one of 8 to 10, wherein the semiconductor film is heat-treated at 150 to 450 ° C. for 0.1 to 1200 minutes in the presence of oxygen.
  • the impurity concentration of the crystalline indium oxide thin film is low, the trap density in the thin film, particularly the channel portion, can be reduced. As a result, the S value can be sufficiently reduced.
  • FIG. 6 is a diagram showing an output curve of a thin film transistor manufactured in Example 1.
  • FIG. 6 is a diagram showing a transfer curve of a thin film transistor manufactured in Example 1.
  • FIG. 6 is a schematic cross-sectional view of an etch stopper type thin film transistor fabricated in Example 3.
  • FIG. 10 is a diagram showing a transfer curve of a thin film transistor manufactured in Example 5.
  • the thin film transistor (TFT) of the present invention has a crystalline indium oxide semiconductor film, and the content of positive tetravalent or higher metal elements with respect to all metal elements contained in the semiconductor film is 10 atomic ppm or less. .
  • FIG. 1 is a schematic cross-sectional view showing an embodiment of a thin film transistor of the present invention.
  • the thin film transistor 1 has a gate electrode 20 sandwiched between a substrate 10 and an insulating film 30, and a semiconductor film 40 is stacked on the gate insulating film 30 as an active layer. Further, a source electrode 50 and a drain electrode 52 are provided so as to cover the vicinity of the end of the semiconductor film 40. A channel portion 60 is formed in a portion surrounded by the semiconductor film 40, the source electrode 50 and the drain electrode 52. 1 is a so-called channel etch type thin film transistor.
  • the thin film transistor of the present invention is not limited to a channel etch type thin film transistor, and an element configuration known in this technical field can be adopted.
  • FIG. 2 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention.
  • the thin film transistor 2 is an etch stopper type thin film transistor.
  • the thin film transistor 2 has the same configuration as the thin film transistor 1 described above except that an etch stopper 70 is formed so as to cover the channel portion 60.
  • a source electrode 50 and a drain electrode 52 are provided so as to cover the vicinity of the end of the semiconductor film 40 and the vicinity of the end of the etch stopper 70.
  • a thin film made of high-purity crystalline indium oxide is used for the semiconductor film 40.
  • high purity means that the crystalline indium oxide thin film contains substantially no positive tetravalent or higher-valent metal element as an impurity.
  • the content of positive tetravalent or higher metal elements in all metal elements forming the semiconductor film is 10 atomic ppm or less.
  • Impurities in the thin film contribute to electron scattering and cause a decrease in mobility. If the impurity concentration is low, scattering can be suppressed and high mobility inherent in indium oxide can be maintained. In addition, the crystal structure may be disturbed by impurities, so that oxygen vacancies cannot be sufficiently reduced, and a thin film transistor exhibiting a normally-on operation may be obtained.
  • a crystalline indium oxide semiconductor film having an extremely low impurity concentration is used, a high-performance thin film transistor that is normally off, has high mobility, low off-current value, and low S value and high operational stability. Is obtained.
  • normally-off is defined as a case where the threshold voltage value is negative (positive). The threshold voltage is determined from the X-intercept of the transfer curve (Id-Vg) graph.
  • the carrier density of the semiconductor film near room temperature can be kept below 2 ⁇ 10 +17 cm ⁇ 3 .
  • the carrier density of the semiconductor film is preferably less than 2 ⁇ 10 +17 cm ⁇ 3 near room temperature. If the carrier density is 2 ⁇ 10 +17 cm ⁇ 3 or more, the TFT may not be driven. Even when the TFT is driven, the threshold voltage may be negatively large and normally on, or the On / Off ratio may be small.
  • a metal element having a positive tetravalence or more and a metal element having a positive divalent or less are present as metal oxides in the thin film.
  • the positive tetravalent or higher metal oxide contained in the semiconductor film include positive oxides such as titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and manganese oxide.
  • Examples of the metal oxide having a positive or lower valence included in the semiconductor film include a positive or lower valent metal such as lithium oxide, sodium oxide, potassium oxide, rubidium oxide, cesium oxide, magnesium oxide, calcium oxide, strontium oxide, and barium oxide.
  • a positive or lower valent metal such as lithium oxide, sodium oxide, potassium oxide, rubidium oxide, cesium oxide, magnesium oxide, calcium oxide, strontium oxide, and barium oxide.
  • sodium oxide, potassium oxide, magnesium oxide, calcium oxide, and zinc oxide are preferably strictly controlled.
  • the content of the metal element (M4) of the metal oxide of positive tetravalent or higher with respect to all the metal elements of the semiconductor film is 10 atomic ppm or less, preferably 5 atomic ppm or less, more preferably 1 It is atomic ppm or less, more preferably 0.5 atomic ppm or less, and particularly preferably 0.1 atomic ppm or less.
  • the carrier density may be 2 ⁇ 10 +17 cm ⁇ 3 or more, and the TFT characteristics may not be operated. Even if the TFT is driven, the threshold voltage may increase negatively, indicating normally-on, or the off-current value may increase and the On / Off ratio may decrease. Further, the trap density in the thin film and / or the interface between the insulating film and the semiconductor film may increase, and the S value may increase.
  • the Sn content is particularly high, the oxidizing power of the element is strong, so the carrier density increases, and even when driven as a TFT, the threshold voltage increases negatively, indicating normally-on, or off-current value May increase and the On / Off ratio may decrease. Further, the trap density in the thin film and / or the interface between the insulating film and the semiconductor film may increase, and the S value may increase.
  • the Sn content is preferably 1 atom ppm or less, more preferably 0.5 atom ppm or less, and particularly preferably 0.1 atom ppm or less.
  • the content rate of the metal element (M2) of the metal oxide of a positive bivalent or less with respect to all the metal elements of a semiconductor film is 50 atomic ppm or less. If the atomic ratio exceeds 50 atomic ppm, the mobility may be low, and the TFT characteristics may not work. Further, the trap density in the thin film and / or the interface between the insulating film and the semiconductor film may increase, and the S value may increase.
  • the ratio of the metal element (M2) is more preferably 10 atomic ppm or less, further preferably 5 atomic ppm or less, and particularly preferably 1 atomic ppm or less.
  • the ratio of the metal element (M) can be obtained by measuring the abundance of each element by ICP-Mass (Inductively Coupled Plasma Mass) measurement.
  • the metal element (M) ratio can be implemented, for example, by adjusting the amount of each element in the sputtering target used when forming the semiconductor film.
  • the composition of the semiconductor film substantially matches the composition of the sputtering target.
  • the use of the crystalline indium oxide semiconductor film can suppress the etching of the semiconductor film when the source electrode 50 and the drain electrode 52 are etched. Further, the durability of the TFT can be increased.
  • the “crystalline film” is a film that can be confirmed by confirming a crystal peak by X-ray diffraction.
  • the crystalline film may be any of a single crystal film, an epitaxial film, and a polycrystalline film, and is preferably an epitaxial film and a polycrystalline film because industrial production is easy and the area can be increased. A polycrystalline film is preferred.
  • the polycrystalline film is preferably made of nanocrystals.
  • the average crystal grain size determined by using Scherrer's equation from X-ray diffraction is usually 500 nm or less, preferably 300 nm or less, more preferably 150 nm or less, and even more preferably 80 nm or less. If it is larger than 500 nm, there is a possibility that variation when the transistor is miniaturized becomes large.
  • the substrate can be used for the substrate, gate electrode, gate insulating film, source / drain electrode, and the like, and are not particularly limited.
  • a metal thin film such as Al, Cu, or Au can be used for each electrode, and an oxide thin film such as a silicon oxide film or a hafnium oxide film can be used for the gate insulating film.
  • the manufacturing method of the present invention includes a film forming step of forming an indium oxide semiconductor film, a step of oxidizing the semiconductor film, and / or a step of crystallizing. Note that components such as a gate electrode, a gate insulating film, and a source / drain electrode can be formed by a known method.
  • a gate electrode made of a metal thin film such as Al, Cu, or Au is formed on a substrate, and an oxide thin film made of a silicon oxide film, a hafnium oxide film, or the like is formed thereon as a gate insulating film.
  • a metal mask is attached to form a semiconductor film made of an indium oxide film only in necessary portions.
  • a source / drain electrode is formed in a necessary portion using a metal mask, whereby a thin film transistor can be manufactured.
  • the semiconductor film can be formed by sputtering, ion plating, vapor deposition, or the like. Of these, the sputtering method is preferable. In sputtering, a method using a sintered target is preferable. Specifically, a high-purity indium oxide sintered target of 99.99 atomic% or more, or 99.995 atomic% (4N) or more is preferable. A sintered target can be manufactured by a well-known method in this technical field. By using a high-purity indium oxide sintered compact target, a crystalline indium oxide thin film having an extremely low impurity concentration can be obtained.
  • the sputtering conditions can be appropriately adjusted according to the target to be used, the thickness of the semiconductor film, and the like.
  • As the sputtering method an RF sputtering method, a DC sputtering method, or an AC sputtering method can be used.
  • the DC sputtering method and the AC sputtering method are preferable because the film forming speed is high.
  • Oxygen is preferably present during film formation. By allowing oxygen to be present during sputtering, it can be effectively oxidized in the oxidation process of the next step.
  • the oxygen concentration in the atmosphere during sputtering is preferably 5 to 20% by volume, more preferably 7 to 17%, and particularly preferably 8 to 14% by volume.
  • a step of oxidizing the thin film and / or a step of crystallizing the thin film are performed.
  • a lamp annealing device, a laser annealing device, a hot air heating device, a contact heating device, or the like can be used in the presence of oxygen.
  • the semiconductor film is preferably heat-treated in the presence of oxygen at 150 to 450 ° C. for 0.1 to 1200 minutes. If it is less than 150 ° C., the semiconductor film may not be sufficiently crystallized, and if it exceeds 450 ° C., the substrate and the semiconductor film may be damaged.
  • the heat treatment temperature is more preferably 180 ° C. to 350 ° C., and particularly preferably 200 ° C. to 300 ° C. If the heat treatment time is less than 0.1 minutes, the heat treatment time may be too short and the crystallization of the film may be insufficient. If it exceeds 1200 minutes, it takes too much time and is not productive.
  • the heat treatment time is more preferably 1 minute to 600 minutes, and particularly preferably 5 minutes to 60 minutes.
  • the crystallization and / or oxidation treatment of the semiconductor film may be performed immediately after the formation of the semiconductor film, or may be performed after the formation of other components such as source / drain electrodes.
  • the manufacturing method of the present invention is particularly suitable for a manufacturing method of a channel etch type thin film transistor. Since the semiconductor film of the present invention is crystalline, an etching process using photolithography can be adopted as a method for forming the source / drain electrodes and the channel portion from a metal thin film such as Al. That is, the etching solution for removing the metal thin film can selectively etch the metal thin film without etching the semiconductor film. An etch stopper type thin film transistor manufacturing method may also be used.
  • Example 1 (A) Production of Thin Film Transistor A channel etch type thin film transistor shown in FIG. 3 was produced. A conductive silicon substrate 10 with a thermal oxide film (SiO 2 film) having a thickness of 100 nm was used. The thermal oxide film functions as the gate insulating film 30 and the conductive silicon portion functions as the gate electrode 20.
  • SiO 2 film thermal oxide film
  • a target made of high-purity indium oxide having a purity of 4N or more manufactured by Shonan Electronics Materials Laboratory (total of positive tetravalent or more metal elements: Sn, Ti, Zr: 0.09 ppm (Sn : 0.02 ppm), and a metal element having a positive divalent value or less: total of Na, K, Mg, and Zn: 0.8 ppm) was used to form a semiconductor film 40 of 50 nm by sputtering.
  • the target impurity was measured by ICP-Mass (Inductively Coupled Plasma Mass).
  • Sputtering was performed by evacuating the back pressure to 5 ⁇ 10 ⁇ 4 Pa, then adjusting the pressure to 0.2 Pa while flowing argon 9.0 sccm and oxygen 1.0 sccm, and the distance between TS was 10 cm.
  • the substrate temperature was set to room temperature and the sputtering power was 100 W.
  • a metal mask is placed on the semiconductor film 40, and in the vicinity of both ends of the channel part 60, a channel part 60 having a gap (L) between the source and drain electrodes of 200 ⁇ m and a width (W) of 1000 ⁇ m is formed.
  • Gold was deposited to form the source electrode 50 and the drain electrode 52. Then, it heat-processed in the air at 300 degreeC for 1 hour in the hot-air heating furnace, and produced the thin-film transistor.
  • This thin film transistor has a field effect mobility of 60 cm 2 / V ⁇ sec, an On / Off ratio of 5 ⁇ 10 6 , a threshold voltage (Vth) of 7.1 V, and an S value of 1.1 V / dec. Thus, the thin film transistor exhibits normally-off characteristics. The output characteristics showed a clear pinch-off.
  • Table 1 shows the impurity amount of the target used for forming the semiconductor film, the element configuration, and the performance of the thin film transistor for the examples and comparative examples.
  • FIG. 4 shows the transfer curve between the drain voltage (Vds) and the same current (Ids) when the gate voltage (Vgs) is changed from -5V to 25V.
  • FIG. 5 shows the relationship between the gate voltage (Vgs) and the drain current (Ids).
  • the white circle line is a curve obtained by raising the drain current to the gate voltage by a power of 1/2
  • the black circle line is 4 is a curve showing a drain current with respect to a gate voltage. 4 and 5, “XE-Y” means X ⁇ 10 ⁇ Y .
  • 1.0E-05 is 1.0 ⁇ 10 ⁇ 5 .
  • Example 2 As a sputtering target, a target composed of high-purity indium oxide (a total of positive tetravalent metal elements: Sn, Ti, Zr: 0.4 ppm (Sn: 0.1 ppm), a positive divalent or lower metal element: Na, A thin film transistor was manufactured in the same manner as in Example 1 except that the total of K, Mg, and Zn: 3 ppm), manufactured by Shonan Electronic Materials Laboratory] was used. Field effect mobility of the thin film transistor is 52cm 2 / V ⁇ sec, On / Off ratio is 10 6, Vth is 5.5V, S value is 1.5V / dec. Thus, the thin film transistor exhibits normally-off characteristics. The output characteristics showed a clear pinch-off. The semiconductor film was crystalline.
  • Comparative Example 1 As a sputtering target, a target made of indium oxide with a purity of 3N (total tetravalent or higher metal elements: Sn, Ti, Zr total: 120 ppm (Sn: 30 ppm), positive divalent or lower metal elements: Na, K, Mg , Zn was used in the same manner as in Example 1 except that the total amount of Zn was 60 ppm).
  • This thin film transistor has a field effect mobility of 46 cm 2 / V ⁇ sec, an On / Off ratio of 2.5 ⁇ 10 5 , a Vth of ⁇ 1.2 V, and an S value of 2.4 V / dec. Thus, the thin film transistor exhibits normally-on characteristics. The output characteristics showed a clear pinch-off.
  • the semiconductor film was crystalline.
  • Example 3 The etch stopper type thin film transistor shown in FIG. 6 was manufactured by a photoresist method.
  • a target made of high-purity indium oxide (a total of positive tetravalent or higher metal elements: Sn, Ti, Zr) : 0.09 ppm (Sn: 0.02 ppm), and a metal element having a positive divalent value or less: Total of Na, K, Mg, Zn: 0.8 ppm) is used to form a 50 nm semiconductor film 40 by sputtering. did.
  • SiO 2 was deposited by RF sputtering at 300 nm under conditions of oxygen partial pressure of 15% and argon of 85%.
  • a resist was applied on the semiconductor film with SiO 2 and prebaked at 80 ° C. for 15 minutes. Thereafter, the resist film was irradiated with UV light (light intensity: 300 mJ / cm 2 ) through a mask, and then developed with 3 wt% tetramethylammonium hydroxide (TMAH). After washing with pure water, the resist film was post-baked at 130 ° C. for 15 minutes, and SiO 2 was etched by dry etching using CF 4 to form an etch stopper 70 having a desired shape.
  • TMAH 3 wt% tetramethylammonium hydroxide
  • a molybdenum metal film having a thickness of 300 nm was formed on the semiconductor film 40, the gate insulating film (thermal oxide film) 30, and the etch stopper 70.
  • a resist was applied to the molybdenum metal film, and prebaked at 80 ° C. for 15 minutes. Thereafter, the resist film was irradiated with UV light (light intensity: 300 mJ / cm 2 ) through a mask, and then developed with 3 wt% tetramethylammonium hydroxide (TMAH). After washing with pure water, the resist film was post-baked at 130 ° C. for 15 minutes to form a resist pattern having a desired source / drain electrode shape.
  • UV light light intensity: 300 mJ / cm 2
  • TMAH 3 wt% tetramethylammonium hydroxide
  • the substrate with a resist pattern was treated with a mixed acid of phosphoric acid / acetic acid / nitric acid to etch the molybdenum metal film, thereby forming the source electrode 50 and the drain electrode 52.
  • the portion of the semiconductor film 40 in contact with the gate insulating film 30 was also etched.
  • the resist was peeled off, washed with pure water, dried by air blowing, and a thin film transistor (a gap (L) between the source and drain electrodes of the channel portion 60 was 200 ⁇ m and a width (W) was 1000 ⁇ m) was produced. Thereafter, this thin film transistor was heat-treated at 300 ° C. for 1 hour in air in a hot air heating furnace.
  • This thin film transistor has a field effect mobility of 62 cm 2 / V ⁇ sec, an On-Off ratio of 3 ⁇ 10 7 , a Vth of 6.8 V, and an S value of 0.9 V / dec.
  • the thin film transistor exhibits normally-off characteristics.
  • the output characteristics showed a clear pinch-off.
  • the shift voltage (Vth) after applying a 20 V voltage to the gate electrode for 100 minutes was 0.25 V.
  • the semiconductor film was crystalline.
  • Example 4 A thin film transistor was manufactured in the same manner as in Example 3 except that the gap (L) between the source and drain electrodes of the channel portion 60 was 20 ⁇ m and the width (W) was 100 ⁇ m.
  • Example 5 A thin film transistor was manufactured in the same manner as in Example 4 except that the gap (L) between the source and drain electrodes of the channel portion 60 was 10 ⁇ m and the width (W) was 20 ⁇ m.
  • This thin film transistor has a field effect mobility of 36 cm 2 / V ⁇ sec, an On / Off ratio of 4.6 ⁇ 10 8 , a Vth of 3.2 V, and an S value of 0.40 V / dec.
  • the thin film transistor exhibits normally-off characteristics.
  • the output characteristics showed a clear pinch-off.
  • the shift voltage (Vth) after applying a 20V voltage to the gate electrode for 100 minutes was 0.16V.
  • the semiconductor film was crystalline.
  • a transfer curve of the thin film transistor manufactured in Example 5 is shown in FIG.
  • This thin film transistor has a field effect mobility of 27 cm 2 / V ⁇ sec, an On / Off ratio of 4 ⁇ 10 8 , a Vth of ⁇ 2.2 V, and an S value of 1.0 V / dec.
  • the thin film transistor exhibits normally-on characteristics.
  • the output characteristics showed a clear pinch-off.
  • the shift voltage (Vth) after applying 20V voltage to the gate electrode for 100 minutes was 0.38V.
  • the semiconductor film was crystalline.
  • the thin film transistor of Example 4 has the same channel length (L) and width (W) as those of the element described in Patent Document 3. Even in this case, a transistor having good transistor characteristics was obtained in the present invention.
  • the gap (L) between the source and drain electrodes of the thin film transistor of Example 5 is 10 ⁇ m, and the width (W) is 20 ⁇ m. Even when the channel width is narrowed, a transistor having good transistor characteristics is obtained in the present invention.
  • the thin film transistor of the present invention can be suitably used for sensors such as display panels, RFID tags, X-ray detector panels, fingerprint sensors, and photosensors.
  • the thin film transistor manufacturing method of the present invention is particularly suitable for a channel etch type thin film transistor manufacturing method.

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Abstract

Disclosed is a thin film transistor wherein a crystalline indium oxide semiconductor film is provided and the content rate of metal elements having a valency of +4 or higher to the total metal elements contained in the semiconductor film is 10 atm ppm or less.

Description

高純度結晶質酸化インジウム半導体膜を有する薄膜トランジスタ、及びその製造方法Thin film transistor having high-purity crystalline indium oxide semiconductor film and method for manufacturing the same
　本発明は、高純度な結晶質酸化インジウムからなる半導体膜を有する薄膜トランジスタ及びその製造方法に関する。 The present invention relates to a thin film transistor having a semiconductor film made of high-purity crystalline indium oxide and a method for manufacturing the same.
　近年、表示装置の発展は目覚ましく、液晶表示装置やＥＬ表示装置等、種々の表示装置がパソコンやワープロ等のＯＡ機器へ活発に導入されている。これらの表示装置は、いずれも表示素子を透明導電膜で挟み込んだサンドイッチ構造を有している。 In recent years, the development of display devices has been remarkable, and various display devices such as liquid crystal display devices and EL display devices have been actively introduced into office automation equipment such as personal computers and word processors. Each of these display devices has a sandwich structure in which a display element is sandwiched between transparent conductive films.
　上記の表示装置を駆動させる薄膜トランジスタ（ＴＦＴ）等のスイッチング素子には、現在、シリコン系の半導体膜が主に使用されている。それは、シリコン系薄膜の安定性、加工性の良さの他、スイッチング速度が速い等が良好なためである。このシリコン系薄膜は、一般に化学蒸気析出法（ＣＶＤ）法により作製されている。 Currently, silicon-based semiconductor films are mainly used as switching elements such as thin film transistors (TFTs) for driving the above display devices. This is because, in addition to the stability and workability of the silicon-based thin film, the switching speed is fast. This silicon-based thin film is generally produced by a chemical vapor deposition method (CVD) method.
　しかしながら、シリコン系薄膜が非晶質の場合、スイッチング速度が比較的遅く、高速な動画等を表示する場合は画像を表示できないという難点を有している。また、結晶質のシリコン系薄膜の場合には、スイッチング速度は比較的速いが、結晶化するために８００℃以上の高温や、レーザーによる加熱等が必要であり、製造時に多大なエネルギーと工程を要する。また、シリコン系の薄膜は、電圧素子としても性能は優れているものの、電流を流した場合、その特性の経時変化が問題となっている。 However, when the silicon-based thin film is amorphous, the switching speed is relatively slow, and there is a problem that an image cannot be displayed when displaying a high-speed moving image or the like. In addition, in the case of a crystalline silicon-based thin film, the switching speed is relatively fast, but a high temperature of 800 ° C. or higher, heating with a laser, etc. are necessary for crystallization. Cost. In addition, although the silicon-based thin film has excellent performance as a voltage element, a change in the characteristics with time is a problem when a current is passed.
　シリコン系薄膜よりも安定性に優れるとともに、ＩＴＯ膜と同等の光透過率を有する透明半導体膜を得るための材料等として、酸化インジウム、酸化ガリウム及び酸化亜鉛からなるスパッタリングターゲットや、酸化亜鉛と酸化マグネシウムからなる透明半導体薄膜が提案されている（例えば、特許文献１）。酸化インジウム、酸化ガリウム及び酸化亜鉛、又は酸化亜鉛と酸化マグネシウムからなる透明半導体膜は、弱酸でのエッチング性が非常に早い特徴を持っている。しかしながら、金属薄膜のエッチング液でもエッチングされ、透明半導体膜上の金属薄膜をエッチングする場合に、同時にエッチングされてしまうことがあり、透明半導体膜上の金属薄膜だけを選択的にエッチングする場合には不適であった。 Sputtering targets composed of indium oxide, gallium oxide, and zinc oxide, as well as zinc oxide and oxide as materials for obtaining a transparent semiconductor film that is more stable than a silicon-based thin film and has a light transmittance equivalent to that of an ITO film. A transparent semiconductor thin film made of magnesium has been proposed (for example, Patent Document 1). A transparent semiconductor film made of indium oxide, gallium oxide and zinc oxide, or zinc oxide and magnesium oxide has a very fast etching property with a weak acid. However, when etching a metal thin film on a transparent semiconductor film by etching with a metal thin film etchant, the metal thin film on the transparent semiconductor film may be etched at the same time. It was inappropriate.
　一方、酸化インジウムの結晶質を含む膜、特に多結晶膜は、酸素欠損を生成しやすく、成膜時の酸素分圧を上げたり、酸化処理等をしても、キャリヤー密度を２×１０＋１７ｃｍ－３にすることが困難と考えられていた。そのために、半導体膜又はＴＦＴとしての試みはほとんどなされていなかった。
　また、特許文献２に酸化インジウムに正２価の金属酸化物を含有させたビックスバイト構造を有する酸化インジウム半導体膜が記載されている。正２価の金属酸化物を含有させることにより、キャリヤー濃度を低減する試みがなされている。しかしながら、正２価の金属酸化物の場合、ビックスバイト構造のエネルギーバンド構造のバンドギャップ内に不純物順位を形成することがあり、これが、移動度を低下させる場合がある。 On the other hand, a film containing crystalline indium oxide, particularly a polycrystalline film, easily generates oxygen vacancies , and the carrier density is 2 × 10 +17 even if the oxygen partial pressure during film formation is increased or oxidation treatment is performed. It was considered difficult to achieve cm −3 . For this reason, almost no attempt has been made as a semiconductor film or TFT.
Patent Document 2 describes an indium oxide semiconductor film having a bixbyite structure in which a positive divalent metal oxide is contained in indium oxide. Attempts have been made to reduce the carrier concentration by including a positive divalent metal oxide. However, in the case of a positive divalent metal oxide, an impurity order may be formed in the band gap of the energy band structure of the bixbite structure, which may reduce the mobility.
　特許文献３には、結晶質の酸化インジウム薄膜を用いた薄膜トランジスタが記載されている。しかしながら、チャンネル部分のトラップ密度が高くなる場合があった。このため、Ｓ値を十分に低減できないことや、ノーマリーオンのトランジスタになる等の問題があった。また、薄膜中のトラップ密度が高いと、トラップによりオフ電流値が十分低減できないという問題があった。
　この点について、特許文献３では酸化インジウム薄膜の膜厚を２０ｎｍとすることにより、オフ電流値が低減できることが記載されている。しかしながら、膜厚を２０ｎｍに制御して、均一に、かつ大面積に成膜することは技術的に難しい。そのため、薄膜トランジスタの特性がばらつく原因となる可能性があった。 Patent Document 3 describes a thin film transistor using a crystalline indium oxide thin film. However, the trap density in the channel portion may increase. For this reason, there are problems that the S value cannot be reduced sufficiently and that a normally-on transistor is formed. Further, when the trap density in the thin film is high, there is a problem that the off-current value cannot be sufficiently reduced by the trap.
In this regard, Patent Document 3 describes that the off-current value can be reduced by setting the thickness of the indium oxide thin film to 20 nm. However, it is technically difficult to control the film thickness to 20 nm to form a film uniformly and in a large area. For this reason, there is a possibility that the characteristics of the thin film transistor vary.
特開２００４－１１９５２５号公報JP 2004-119525 A 国際公開第０７／０５８２４８号パンフレットInternational Publication No. 07/058248 Pamphlet 特開２００８－１３０８１４号公報JP 2008-130814 A
　本発明の目的は、結晶質酸化インジウムからなる半導体膜を使用した薄膜トランジスタであって、半導体膜のトラップ密度を低減することにより高性能な薄膜トランジスタを提供することである。 An object of the present invention is to provide a thin film transistor using a semiconductor film made of crystalline indium oxide and having a high performance by reducing the trap density of the semiconductor film.
　本発明者らは、結晶質酸化インジウムからなる半導体膜の不純物、具体的には、正４価以上の金属元素が半導体膜のトラップ密度に影響を与えることを見出した。そして、この金属元素の含有率を所定値以下とすることにより、高性能な薄膜トランジスタが得られることをつきとめ、本発明を完成させた。 The present inventors have found that impurities in a semiconductor film made of crystalline indium oxide, specifically, a metal element having a positive tetravalence or more affects the trap density of the semiconductor film. The inventors have found that a high-performance thin film transistor can be obtained by setting the content of the metal element to a predetermined value or less, thereby completing the present invention.
　本発明によれば、以下の薄膜トランジスタ等が提供される。
１．結晶質酸化インジウム半導体膜を有し、前記半導体膜に含まれる全金属元素に対する正４価以上の金属元素の含有率が１０原子ｐｐｍ以下である薄膜トランジスタ。
２．結晶質酸化インジウム半導体膜を有し、前記半導体膜に含まれる全金属元素に対する正４価以上の金属元素の含有率が１原子ｐｐｍ以下である薄膜トランジスタ。
３．結晶質酸化インジウム半導体膜を有し、前記半導体膜に含まれる全金属元素に対する正４価以上の金属元素の含有率が０．１原子ｐｐｍ以下である薄膜トランジスタ。
４．前記正４価以上の金属元素がＳｎである１～３のいずれかに記載の薄膜トランジスタ。
５．さらに、前記半導体膜に含まれる全金属元素に対する正２価以下の金属元素の含有率が５０原子ｐｐｍ以下である１～４のいずれかに記載の薄膜トランジスタ。
６．チャンネルエッチ型である１～５のいずれかに記載の薄膜トランジスタ。
７．エッチストッパー型である１～５のいずれかに記載の薄膜トランジスタ。
８．純度が９９．９９原子％以上の酸化インジウムターゲットを用いて半導体膜を成膜する成膜工程と、前記半導体膜を酸化処理する工程、及び／又は前記半導体膜を結晶化する工程を含む、１～７のいずれかに記載の薄膜トランジスタの製造方法。
９．前記酸化インジウムターゲットの純度が９９．９９５原子％以上である８に記載の薄膜トランジスタの製造方法。
１０．前記成膜工程をスパッタリングで実施し、スパッタリング中の雰囲気の酸素濃度を５～２０体積％とする８又は９に記載の薄膜トランジスタの製造方法。
１１．前記半導体膜を酸素の存在下に、１５０～４５０℃で０．１～１２００分間熱処理する８～１０のいずれかに記載の薄膜トランジスタの製造方法。 According to the present invention, the following thin film transistors and the like are provided.
1. A thin film transistor having a crystalline indium oxide semiconductor film and having a content of positive tetravalent or higher metal elements with respect to all metal elements contained in the semiconductor film of 10 atomic ppm or less.
2. A thin film transistor having a crystalline indium oxide semiconductor film, wherein the content of a metal element having a positive tetravalent or higher valence relative to all metal elements contained in the semiconductor film is 1 atomic ppm or less.
3. A thin film transistor having a crystalline indium oxide semiconductor film, wherein the content of a metal element having a positive tetravalent or higher valence relative to all metal elements contained in the semiconductor film is 0.1 atomic ppm or less.
4). 4. The thin film transistor according to any one of 1 to 3, wherein the positive tetravalent or higher metal element is Sn.
5). Furthermore, the thin film transistor according to any one of 1 to 4, wherein the content of metal elements having a positive divalent value or less with respect to all metal elements contained in the semiconductor film is 50 atom ppm or less.
6). 6. The thin film transistor according to any one of 1 to 5, which is a channel etch type.
7). 6. The thin film transistor according to any one of 1 to 5, which is an etch stopper type.
8). Including a film forming step of forming a semiconductor film using an indium oxide target having a purity of 99.99 atomic% or more, a step of oxidizing the semiconductor film, and / or a step of crystallizing the semiconductor film. 8. A method for producing a thin film transistor according to any one of items 1 to 7.
9. 9. The method for producing a thin film transistor according to 8, wherein the indium oxide target has a purity of 99.995 atomic% or more.
10. 10. The method for producing a thin film transistor according to 8 or 9, wherein the film forming step is performed by sputtering, and an oxygen concentration in an atmosphere during sputtering is 5 to 20% by volume.
11. 11. The method for producing a thin film transistor according to any one of 8 to 10, wherein the semiconductor film is heat-treated at 150 to 450 ° C. for 0.1 to 1200 minutes in the presence of oxygen.
　本発明によれば、結晶質酸化インジウム薄膜の不純物濃度が低いことにより、薄膜中、特にチャンネル部分のトラップ密度を少なくできる。その結果、Ｓ値を十分低減することができる。 According to the present invention, since the impurity concentration of the crystalline indium oxide thin film is low, the trap density in the thin film, particularly the channel portion, can be reduced. As a result, the S value can be sufficiently reduced.
本発明のチャンネルエッチ型薄膜トランジスタの実施形態を示す概略断面図である。It is a schematic sectional drawing which shows embodiment of the channel etch type thin-film transistor of this invention. 本発明のエッチストッパー型薄膜トランジスタの実施形態を示す概略断面図である。It is a schematic sectional drawing which shows embodiment of the etch stopper type thin-film transistor of this invention. 実施例１で作製したチャンネルエッチ型薄膜トランジスタの概略断面図である。3 is a schematic cross-sectional view of a channel-etched thin film transistor manufactured in Example 1. FIG. 実施例１で作製した薄膜トランジスタの出力曲線を示す図である。6 is a diagram showing an output curve of a thin film transistor manufactured in Example 1. FIG. 実施例１で作製した薄膜トランジスタの伝達曲線を示す図である。6 is a diagram showing a transfer curve of a thin film transistor manufactured in Example 1. FIG. 実施例３で作製したエッチストッパー型薄膜トランジスタの概略断面図である。6 is a schematic cross-sectional view of an etch stopper type thin film transistor fabricated in Example 3. FIG. 実施例５で作製した薄膜トランジスタの伝達曲線を示す図である。10 is a diagram showing a transfer curve of a thin film transistor manufactured in Example 5. FIG.
　本発明の薄膜トランジスタ（ＴＦＴ）は、結晶質酸化インジウム半導体膜を有し、半導体膜に含まれる全金属元素に対する正４価以上の金属元素の含有率が１０原子ｐｐｍ以下であることを特徴とする。 The thin film transistor (TFT) of the present invention has a crystalline indium oxide semiconductor film, and the content of positive tetravalent or higher metal elements with respect to all metal elements contained in the semiconductor film is 10 atomic ppm or less. .
　図１は、本発明の薄膜トランジスタの実施形態を示す概略断面図である。
　薄膜トランジスタ１は、基板１０及び絶縁膜３０の間にゲート電極２０を挟持しており、ゲート絶縁膜３０上には半導体膜４０が活性層として積層されている。さらに、半導体膜４０の端部付近を覆うようにしてソース電極５０及びドレイン電極５２がそれぞれ設けられている。半導体膜４０、ソース電極５０及びドレイン電極５２で囲まれた部分にチャンネル部６０を形成している。
　尚、図１の薄膜トランジスタ１はいわゆるチャンネルエッチ型薄膜トランジスタである。本発明の薄膜トランジスタは、チャンネルエッチ型薄膜トランジスタに限定されず、本技術分野で公知の素子構成を採用できる。 FIG. 1 is a schematic cross-sectional view showing an embodiment of a thin film transistor of the present invention.
The thin film transistor 1 has a gate electrode 20 sandwiched between a substrate 10 and an insulating film 30, and a semiconductor film 40 is stacked on the gate insulating film 30 as an active layer. Further, a source electrode 50 and a drain electrode 52 are provided so as to cover the vicinity of the end of the semiconductor film 40. A channel portion 60 is formed in a portion surrounded by the semiconductor film 40, the source electrode 50 and the drain electrode 52.
1 is a so-called channel etch type thin film transistor. The thin film transistor of the present invention is not limited to a channel etch type thin film transistor, and an element configuration known in this technical field can be adopted.
　図２は、本発明の薄膜トランジスタの他の実施形態を示す概略断面図である。尚、上述した薄膜トランジスタ１と同じ構成部材には同じ番号を付し、その説明を省略する。
　薄膜トランジスタ２は、エッチストッパー型の薄膜トランジスタである。薄膜トランジスタ２は、チャンネル部６０を覆うようにエッチストッパー７０が形成されている点を除き、上述した薄膜トランジスタ１と同じ構成である。半導体膜４０の端部付近及びエッチストッパー７０の端部付近を覆うようにしてソース電極５０及びドレイン電極５２がそれぞれ設けられている。 FIG. 2 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention. In addition, the same number is attached | subjected to the same structural member as the thin-film transistor 1 mentioned above, and the description is abbreviate | omitted.
The thin film transistor 2 is an etch stopper type thin film transistor. The thin film transistor 2 has the same configuration as the thin film transistor 1 described above except that an etch stopper 70 is formed so as to cover the channel portion 60. A source electrode 50 and a drain electrode 52 are provided so as to cover the vicinity of the end of the semiconductor film 40 and the vicinity of the end of the etch stopper 70.
　本発明では半導体膜４０に、高純度な結晶質酸化インジウムからなる薄膜を使用する。ここで、高純度とは、結晶質酸化インジウム薄膜が不純物として、正４価以上の金属元素を実質的に含まないことを意味する。具体的には、半導体膜を形成する全金属元素に占める正４価以上の金属元素の含有率が１０原子ｐｐｍ以下であることを意味する。これらの含有率を極めて低くすることにより、薄膜中や絶縁膜－半導体膜界面におけるトラップ密度を低減することができる。その結果、Ｓ値を低減することができる。 In the present invention, a thin film made of high-purity crystalline indium oxide is used for the semiconductor film 40. Here, high purity means that the crystalline indium oxide thin film contains substantially no positive tetravalent or higher-valent metal element as an impurity. Specifically, it means that the content of positive tetravalent or higher metal elements in all metal elements forming the semiconductor film is 10 atomic ppm or less. By making these contents extremely low, the trap density in the thin film or at the insulating film-semiconductor film interface can be reduced. As a result, the S value can be reduced.
　薄膜中の不純物は電子の散乱に寄与し、移動度の低下を引き起こす。不純物濃度が低ければ散乱を抑制し、酸化インジウムが本来有する高い移動度を維持することができる。
　また、不純物により結晶構造に乱れが生じ、酸素欠損を十分低減することができずにノーマリーオン動作を示す薄膜トランジスタになる場合がある。本発明では、不純物濃度が極めて低い結晶質酸化インジウムの半導体膜を使用するので、ノーマリーオフで、高移動度、低オフ電流値、さらにＳ値が低く高い動作安定性を示す高性能な薄膜トランジスタが得られる。
　尚、本発明においてノーマリーオフとは、閾値電圧の値が負（正）である場合と定義する。閾値電圧は伝達曲線（Ｉｄ－Ｖｇ）のグラフのＸ切片から求める。 Impurities in the thin film contribute to electron scattering and cause a decrease in mobility. If the impurity concentration is low, scattering can be suppressed and high mobility inherent in indium oxide can be maintained.
In addition, the crystal structure may be disturbed by impurities, so that oxygen vacancies cannot be sufficiently reduced, and a thin film transistor exhibiting a normally-on operation may be obtained. In the present invention, since a crystalline indium oxide semiconductor film having an extremely low impurity concentration is used, a high-performance thin film transistor that is normally off, has high mobility, low off-current value, and low S value and high operational stability. Is obtained.
In the present invention, normally-off is defined as a case where the threshold voltage value is negative (positive). The threshold voltage is determined from the X-intercept of the transfer curve (Id-Vg) graph.
　特に、正４価以上の金属元素の含有率を１０原子ｐｐｍ以下とすることにより、室温付近における半導体膜のキャリヤー密度を２×１０＋１７ｃｍ－３未満に保つことが可能となる。これにより、良好な薄膜トランジスタ特性が得られる。
　尚、半導体膜のキャリヤー密度は、室温付近において好ましくは２×１０＋１７ｃｍ－３未満である。キャリヤー密度が２×１０＋１７ｃｍ－３以上では、ＴＦＴとして駆動しないおそれがある。また、ＴＦＴとして駆動したとしても閾値電圧がマイナスに大きくノーマリーオンを示したり、Ｏｎ／Ｏｆｆ比が小さくなる場合がある。
　正２価以下の金属元素の含有率を５０原子ｐｐｍ以下とすることにより、得られるＴＦＴの移動度を高くすることができる。 In particular, by setting the content of the positive tetravalent or higher metal element to 10 atomic ppm or less, the carrier density of the semiconductor film near room temperature can be kept below 2 × 10 +17 cm −3 . Thereby, good thin film transistor characteristics can be obtained.
Note that the carrier density of the semiconductor film is preferably less than 2 × 10 +17 cm −3 near room temperature. If the carrier density is 2 × 10 +17 cm −3 or more, the TFT may not be driven. Even when the TFT is driven, the threshold voltage may be negatively large and normally on, or the On / Off ratio may be small.
By setting the content of the metal element having a positive divalent value or less to 50 atomic ppm or less, the mobility of the obtained TFT can be increased.
　正４価以上の金属元素及び正２価以下の金属元素は、薄膜内において、金属酸化物として存在している。
　半導体膜に含まれる正４価以上の金属酸化物としては、酸化チタン、酸化ジルコニウム、酸化ハフニウム、酸化バナジウム、酸化ニオブ、酸化タンタル、酸化クロム、酸化モリブデン、酸化タングステン、酸化マンガン、等の正４価以上の重金属酸化物、及び酸化ケイ素、酸化ゲルマニウム、酸化スズ、酸化鉛、酸化アンチモン、酸化ビスマス、酸化セリウムから選択される１種又は２種以上の酸化物である。これらの酸化物は、結晶中に取り込まれた場合には、キャリヤーを発生する場合がある。その結果、室温付近の温度においてのキャリヤー密度を、２×１０＋１７ｃｍ－３未満に制御できない場合がある。
　上記金属酸化物のうち、特に、酸化チタン、酸化ジルコニウム、酸化スズ、は、厳密に管理することが好ましい。 A metal element having a positive tetravalence or more and a metal element having a positive divalent or less are present as metal oxides in the thin film.
Examples of the positive tetravalent or higher metal oxide contained in the semiconductor film include positive oxides such as titanium oxide, zirconium oxide, hafnium oxide, vanadium oxide, niobium oxide, tantalum oxide, chromium oxide, molybdenum oxide, tungsten oxide, and manganese oxide. A heavy metal oxide having a valence of 1 or more, and one or more oxides selected from silicon oxide, germanium oxide, tin oxide, lead oxide, antimony oxide, bismuth oxide, and cerium oxide. These oxides may generate carriers when incorporated in the crystal. As a result, the carrier density at temperatures near room temperature may not be controlled below 2 × 10 +17 cm −3 .
Among the above metal oxides, it is particularly preferable to strictly manage titanium oxide, zirconium oxide, and tin oxide.
　半導体膜に含まれる正２価以下の金属酸化物としては、酸化リチウム、酸化ナトリウム、酸化カリウム、酸化ルビジウム、酸化セシウム、酸化マグネシウム、酸化カルシウム、酸化ストロンチウム、酸化バリウム、等の正２価以下のアルカリ、アルカリ土類属酸化物、及び酸化亜鉛、から選択される１種又は２種以上の酸化物である。これらの酸化物は、結晶中に取り込まれた場合には、バンドギャップ内に不純物順位を形成する場合がある。その結果、キャリヤートラップが発生し、移動度が低下する場合がある。
　上記金属酸化物のうち、特に、酸化ナトリウム、酸化カリウム、酸化マグネシウム、酸化カルシウム、酸化亜鉛は、厳密に管理することが好ましい。 Examples of the metal oxide having a positive or lower valence included in the semiconductor film include a positive or lower valent metal such as lithium oxide, sodium oxide, potassium oxide, rubidium oxide, cesium oxide, magnesium oxide, calcium oxide, strontium oxide, and barium oxide. One or more oxides selected from alkali, alkaline earth oxide, and zinc oxide. These oxides may form an impurity order in the band gap when taken into the crystal. As a result, a carrier trap is generated and mobility may be lowered.
Among the above metal oxides, sodium oxide, potassium oxide, magnesium oxide, calcium oxide, and zinc oxide are preferably strictly controlled.
　本発明において、半導体膜の全金属元素に対する正４価以上の金属酸化物の金属元素（Ｍ４）の含有率は、１０原子ｐｐｍ以下であり、好ましくは５原子ｐｐｍ以下であり、より好ましくは１原子ｐｐｍ以下であり、さらに好ましくは０．５原子ｐｐｍ以下であり、特に好ましくは０．１原子ｐｐｍ以下である。原子比が１０原子ｐｐｍ超では、キャリヤー密度が２×１０＋１７ｃｍ－３以上になる場合があり、ＴＦＴ特性として作動しなくなる場合がある。また、ＴＦＴとして駆動したとしても閾値電圧がマイナスに大きくなりノーマリーオンを示したり、オフ電流値が増加しＯｎ／Ｏｆｆ比が小さくなる場合がある。また薄膜中、及び（又は）絶縁膜－半導体膜の界面のトラップ密度が増加し、Ｓ値が増大するおそれがある。 In the present invention, the content of the metal element (M4) of the metal oxide of positive tetravalent or higher with respect to all the metal elements of the semiconductor film is 10 atomic ppm or less, preferably 5 atomic ppm or less, more preferably 1 It is atomic ppm or less, more preferably 0.5 atomic ppm or less, and particularly preferably 0.1 atomic ppm or less. When the atomic ratio exceeds 10 atomic ppm, the carrier density may be 2 × 10 +17 cm −3 or more, and the TFT characteristics may not be operated. Even if the TFT is driven, the threshold voltage may increase negatively, indicating normally-on, or the off-current value may increase and the On / Off ratio may decrease. Further, the trap density in the thin film and / or the interface between the insulating film and the semiconductor film may increase, and the S value may increase.
　Ｍ４のうち、特にＳｎの含有率が高い場合、元素の酸化力が強いため、キャリヤー密度が増加し、ＴＦＴとして駆動したとしても閾値電圧がマイナスに大きくなりノーマリーオンを示したり、オフ電流値が増加しＯｎ／Ｏｆｆ比が小さくなる場合がある。また薄膜中、及び（又は）絶縁膜－半導体膜の界面のトラップ密度が増加し、Ｓ値が増大するおそれがある。Ｓｎの含有率は好ましくは１原子ｐｐｍ以下であり、さらに好ましくは０．５原子ｐｐｍ以下であり、特に好ましくは０．１原子ｐｐｍ以下である。 Among M4, when the Sn content is particularly high, the oxidizing power of the element is strong, so the carrier density increases, and even when driven as a TFT, the threshold voltage increases negatively, indicating normally-on, or off-current value May increase and the On / Off ratio may decrease. Further, the trap density in the thin film and / or the interface between the insulating film and the semiconductor film may increase, and the S value may increase. The Sn content is preferably 1 atom ppm or less, more preferably 0.5 atom ppm or less, and particularly preferably 0.1 atom ppm or less.
　本発明において、半導体膜の全金属元素に対する正２価以下の金属酸化物の金属元素（Ｍ２）の含有率は、５０原子ｐｐｍ以下であることが好ましい。原子比が５０原子ｐｐｍ超では、移動度が低くなる場合があり、ＴＦＴ特性として作動しなくなる場合がある。また薄膜中、及び（又は）絶縁膜－半導体膜の界面のトラップ密度が増加し、Ｓ値が増大するおそれがある。
　金属元素（Ｍ２）の比率は、より好ましくは、１０原子ｐｐｍ以下であり、さらに好ましくは５原子ｐｐｍ以下であり、特に好ましくは１原子ｐｐｍ以下である。 In this invention, it is preferable that the content rate of the metal element (M2) of the metal oxide of a positive bivalent or less with respect to all the metal elements of a semiconductor film is 50 atomic ppm or less. If the atomic ratio exceeds 50 atomic ppm, the mobility may be low, and the TFT characteristics may not work. Further, the trap density in the thin film and / or the interface between the insulating film and the semiconductor film may increase, and the S value may increase.
The ratio of the metal element (M2) is more preferably 10 atomic ppm or less, further preferably 5 atomic ppm or less, and particularly preferably 1 atomic ppm or less.
　金属元素（Ｍ）の比率は、ＩＣＰ－Ｍａｓｓ（Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ　Ｍａｓｓ）測定により、各元素の存在量を測定することで求めることができる。
　また、金属元素（Ｍ）比率は、例えば、半導体膜を形成する際に使用するスパッタリングターゲットの各元素の存在量を調整することで実施できる。半導体膜の組成は、スパッタリングターゲットの組成とほぼ一致する。 The ratio of the metal element (M) can be obtained by measuring the abundance of each element by ICP-Mass (Inductively Coupled Plasma Mass) measurement.
In addition, the metal element (M) ratio can be implemented, for example, by adjusting the amount of each element in the sputtering target used when forming the semiconductor film. The composition of the semiconductor film substantially matches the composition of the sputtering target.
　本発明では、結晶質酸化インジウム半導体膜を使用することにより、ソース電極５０及びドレイン電極５２のエッチングの際に、半導体膜がエッチングされることを抑制できる。また、ＴＦＴの耐久性を高くできる。
　尚、「結晶質膜」とは、Ｘ線回折により、結晶ピークを確認できることで確認できる膜である。
　結晶質膜は、単結晶膜、エピタキシャル膜及び多結晶膜のいずれであってもよく、工業生産が容易かつ大面積化が可能であることから、好ましくはエピタキシャル膜及び多結晶膜であり、特に好ましくは多結晶膜である。 In the present invention, the use of the crystalline indium oxide semiconductor film can suppress the etching of the semiconductor film when the source electrode 50 and the drain electrode 52 are etched. Further, the durability of the TFT can be increased.
The “crystalline film” is a film that can be confirmed by confirming a crystal peak by X-ray diffraction.
The crystalline film may be any of a single crystal film, an epitaxial film, and a polycrystalline film, and is preferably an epitaxial film and a polycrystalline film because industrial production is easy and the area can be increased. A polycrystalline film is preferred.
　結晶質膜が多結晶膜の場合、当該多結晶膜がナノクリスタルからなることが好ましい。Ｘ線回折からＳｃｈｅｒｒｅｒ’ｓ　ｅｑｕａｔｉｏｎを用いて求めた平均結晶粒径は通常５００ｎｍ以下、好ましくは３００ｎｍ以下、より好ましくは１５０ｎｍ以下、さらに好ましくは８０ｎｍ以下である。５００ｎｍより大きいとトランジスタを微細化した際のばらつきが大きくなるおそれがある。 When the crystalline film is a polycrystalline film, the polycrystalline film is preferably made of nanocrystals. The average crystal grain size determined by using Scherrer's equation from X-ray diffraction is usually 500 nm or less, preferably 300 nm or less, more preferably 150 nm or less, and even more preferably 80 nm or less. If it is larger than 500 nm, there is a possibility that variation when the transistor is miniaturized becomes large.
　本発明の薄膜トランジスタにおいて、基板、ゲート電極、ゲート絶縁膜、ソース・ドレイン電極等の構成部材は、公知のものが使用でき、特に限定されない。
　例えば、各電極にはＡｌ、Ｃｕ、Ａｕ等の金属薄膜が使用でき、ゲート絶縁膜には、酸化シリコン膜、酸化ハフニウム膜等の酸化物薄膜を使用できる。 In the thin film transistor of the present invention, known components can be used for the substrate, gate electrode, gate insulating film, source / drain electrode, and the like, and are not particularly limited.
For example, a metal thin film such as Al, Cu, or Au can be used for each electrode, and an oxide thin film such as a silicon oxide film or a hafnium oxide film can be used for the gate insulating film.
　続いて、本発明の薄膜トランジスタの製造方法を説明する。
　本発明の製造方法は、酸化インジウム半導体膜を成膜する成膜工程と、半導体膜を酸化処理する工程、及び／又は結晶化する工程を含む。尚、ゲート電極、ゲート絶縁膜、ソース・ドレイン電極等の構成部材は、公知の方法により形成できる。 Then, the manufacturing method of the thin-film transistor of this invention is demonstrated.
The manufacturing method of the present invention includes a film forming step of forming an indium oxide semiconductor film, a step of oxidizing the semiconductor film, and / or a step of crystallizing. Note that components such as a gate electrode, a gate insulating film, and a source / drain electrode can be formed by a known method.
　例えば、基板上にＡｌ、Ｃｕ、Ａｕ等の金属薄膜からなるゲート電極を形成し、その上に、酸化シリコン膜、酸化ハフニウム膜等からなる酸化物薄膜をゲート絶縁膜として形成する。その上に、金属マスクを装着して必要な部分だけに酸化インジウム膜からなる半導体膜を形成する。その後、金属マスクを用いて、必要部分にソース・ドレイン電極を形成することで、薄膜トランジスタを製造することができる。 For example, a gate electrode made of a metal thin film such as Al, Cu, or Au is formed on a substrate, and an oxide thin film made of a silicon oxide film, a hafnium oxide film, or the like is formed thereon as a gate insulating film. On top of that, a metal mask is attached to form a semiconductor film made of an indium oxide film only in necessary portions. Thereafter, a source / drain electrode is formed in a necessary portion using a metal mask, whereby a thin film transistor can be manufactured.
　半導体膜の成膜は、スパッタ法、イオンプレーティング法、蒸着法等がある。このなかでは、スパッタ法が好ましい。
　スパッタリングでは、焼結ターゲットを用いる方法が好ましい。具体的に、９９．９９原子％以上、又は９９．９９５原子％（４Ｎ）以上の高純度酸化インジウムの焼結ターゲットが好ましい。焼結ターゲットは、本技術分野において公知の方法により製造できる。
　高純度の酸化インジウム焼結体ターゲットを用いることにより、不純物濃度の極めて低い結晶質酸化インジウム薄膜を得ることができる。 The semiconductor film can be formed by sputtering, ion plating, vapor deposition, or the like. Of these, the sputtering method is preferable.
In sputtering, a method using a sintered target is preferable. Specifically, a high-purity indium oxide sintered target of 99.99 atomic% or more, or 99.995 atomic% (4N) or more is preferable. A sintered target can be manufactured by a well-known method in this technical field.
By using a high-purity indium oxide sintered compact target, a crystalline indium oxide thin film having an extremely low impurity concentration can be obtained.
　スパッタリングの条件は、使用するターゲットや、半導体膜の膜厚等にあわせて適宜調整することができる。スパッタリング方法は、ＲＦスパッタ法、ＤＣスパッタ法、ＡＣスパッタ法が使用できる。中でも、ＤＣスパッタ法、ＡＣスパッタ法が、成膜速度も速く、好ましい。
　成膜中に酸素を存在させることが好ましい。スパッタ中に酸素を存在させることにより、次工程の酸化処理にて、効果的に酸化処理することが出来る。
　スパッタリング中の雰囲気の酸素濃度は５～２０体積％であることが好ましく、さらに前記酸素濃度７～１７％であることが好ましく、特に８～１４体積％であることが好ましい。 The sputtering conditions can be appropriately adjusted according to the target to be used, the thickness of the semiconductor film, and the like. As the sputtering method, an RF sputtering method, a DC sputtering method, or an AC sputtering method can be used. Among these, the DC sputtering method and the AC sputtering method are preferable because the film forming speed is high.
Oxygen is preferably present during film formation. By allowing oxygen to be present during sputtering, it can be effectively oxidized in the oxidation process of the next step.
The oxygen concentration in the atmosphere during sputtering is preferably 5 to 20% by volume, more preferably 7 to 17%, and particularly preferably 8 to 14% by volume.
　本発明の薄膜トランジスタの製造方法では、半導体膜の形成後、薄膜を酸化処理する工程、及び／又は薄膜を結晶化する工程を行う。
　半導体膜の結晶化及び酸化処理には、酸素の存在下にランプアニ―ル装置、レーザーアニール装置、熱風加熱装置、接触加熱装置等を用いることが出来る。
　半導体膜を酸素の存在下に、１５０～４５０℃、０．１～１２００分の条件で熱処理することが好ましい。１５０℃未満では、半導体膜が十分に結晶化しない場合があり、４５０℃超では、基板や半導体膜にダメージを与える場合がある。熱処理温度は、１８０℃～３５０℃がさらに好ましく、特に２００℃～３００℃が好ましい。
　また、熱処理時間が０．１分未満では、熱処理時間が短すぎて膜の結晶化が不十分となる場合があり、１２００分超では時間が掛かりすぎ生産的ではない。熱処理時間は、１分～６００分がさらに好ましく、特に５分～６０分が好ましい。
　尚、半導体膜の結晶化及び／又は酸化処理は、半導体膜の形成後、すぐに実施してもよく、また、ソース・ドレイン電極等、他の構成部材の形成後に実施してもよい。 In the thin film transistor manufacturing method of the present invention, after the semiconductor film is formed, a step of oxidizing the thin film and / or a step of crystallizing the thin film are performed.
For the crystallization and oxidation treatment of the semiconductor film, a lamp annealing device, a laser annealing device, a hot air heating device, a contact heating device, or the like can be used in the presence of oxygen.
The semiconductor film is preferably heat-treated in the presence of oxygen at 150 to 450 ° C. for 0.1 to 1200 minutes. If it is less than 150 ° C., the semiconductor film may not be sufficiently crystallized, and if it exceeds 450 ° C., the substrate and the semiconductor film may be damaged. The heat treatment temperature is more preferably 180 ° C. to 350 ° C., and particularly preferably 200 ° C. to 300 ° C.
If the heat treatment time is less than 0.1 minutes, the heat treatment time may be too short and the crystallization of the film may be insufficient. If it exceeds 1200 minutes, it takes too much time and is not productive. The heat treatment time is more preferably 1 minute to 600 minutes, and particularly preferably 5 minutes to 60 minutes.
The crystallization and / or oxidation treatment of the semiconductor film may be performed immediately after the formation of the semiconductor film, or may be performed after the formation of other components such as source / drain electrodes.
　本発明の製造方法は、特に、チャンネルエッチ型の薄膜トランジスタの製造方法に適している。本発明の半導体膜は結晶質であるため、Ａｌ等の金属薄膜からソース・ドレイン電極及びチャンネル部を形成する方法として、フォトリソグラフィーを使用したエッチング工程を採用できる。即ち、金属薄膜を除去するエッチング液では、半導体膜はエッチングされず、金属薄膜を選択的にエッチングできる。尚、エッチストッパー型の薄膜トランジスタの製造方法であってもよい。 The manufacturing method of the present invention is particularly suitable for a manufacturing method of a channel etch type thin film transistor. Since the semiconductor film of the present invention is crystalline, an etching process using photolithography can be adopted as a method for forming the source / drain electrodes and the channel portion from a metal thin film such as Al. That is, the etching solution for removing the metal thin film can selectively etch the metal thin film without etching the semiconductor film. An etch stopper type thin film transistor manufacturing method may also be used.
　実施例において、「ｐｐｍ」は原子ｐｐｍを意味する。
実施例１
（Ａ）薄膜トランジスタの作製
　図３に示すチャンネルエッチ型の薄膜トランジスタを作製した。
　１００ｎｍ厚みの熱酸化膜（ＳｉＯ２膜）付きの導電性シリコン基板１０を使用した。熱酸化膜がゲート絶縁膜３０として機能し、導電性シリコン部がゲート電極２０として機能する。
　ゲート絶縁膜３０上に、純度が４Ｎ以上の高純度酸化インジウム（湘南電子材料研究所作製）からなるターゲット（正４価以上の金属元素：Ｓｎ，Ｔｉ，Ｚｒの総合計：０．０９ｐｐｍ（Ｓｎ：０．０２ｐｐｍ）、正２価以下の金属元素：Ｎａ，Ｋ，Ｍｇ，Ｚｎの総合計：０．８ｐｐｍ）を用いて、スパッタリング法で５０ｎｍの半導体膜４０を成膜した。
　尚、ターゲットの不純物はＩＣＰ－Ｍａｓｓ（Ｉｎｄｕｃｔｉｖｅｌｙ　Ｃｏｕｐｌｅｄ　Ｐｌａｓｍａ　Ｍａｓｓ）により測定した。
　スパッタリングは、背圧が５×１０－４Ｐａとなるまで真空排気したあと、アルゴン９．０ｓｃｃｍ、酸素１．０ｓｃｃｍを流しながら、圧力を０．２Ｐａに調整し、Ｔ－Ｓ間距離を１０ｃｍ、基板温度を室温とし、スパッタパワー１００Ｗにて行った。 In the examples, “ppm” means atomic ppm.
Example 1
(A) Production of Thin Film Transistor A channel etch type thin film transistor shown in FIG. 3 was produced.
A conductive silicon substrate 10 with a thermal oxide film (SiO 2 film) having a thickness of 100 nm was used. The thermal oxide film functions as the gate insulating film 30 and the conductive silicon portion functions as the gate electrode 20.
On the gate insulating film 30, a target made of high-purity indium oxide having a purity of 4N or more (manufactured by Shonan Electronics Materials Laboratory) (total of positive tetravalent or more metal elements: Sn, Ti, Zr: 0.09 ppm (Sn : 0.02 ppm), and a metal element having a positive divalent value or less: total of Na, K, Mg, and Zn: 0.8 ppm) was used to form a semiconductor film 40 of 50 nm by sputtering.
The target impurity was measured by ICP-Mass (Inductively Coupled Plasma Mass).
Sputtering was performed by evacuating the back pressure to 5 × 10 −4 Pa, then adjusting the pressure to 0.2 Pa while flowing argon 9.0 sccm and oxygen 1.0 sccm, and the distance between TS was 10 cm. The substrate temperature was set to room temperature and the sputtering power was 100 W.
　半導体膜４０の上に金属マスクを設置し、ソース・ドレイン電極間間隙（Ｌ）が２００μｍ、幅（Ｗ）が１０００μｍのチャンネル部６０が形成されるように、チャンネル部６０の両端部付近に、金を蒸着してソース電極５０及びドレイン電極５２を形成した。
　その後、熱風加熱炉内で、空気中、３００℃で１時間熱処理し、薄膜トランジスタを作製した。
　この薄膜トランジスタの電界効果移動度は６０ｃｍ２／Ｖ・ｓｅｃ、Ｏｎ／Ｏｆｆ比は５×１０６であり、閾値電圧（Ｖｔｈ）は７．１Ｖ、Ｓ値は１．１Ｖ／ｄｅｃ．で、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。
　実施例及び比較例について、半導体膜形成に使用したターゲットの不純物量、素子構成、及び薄膜トランジスタの性能を表１に示す A metal mask is placed on the semiconductor film 40, and in the vicinity of both ends of the channel part 60, a channel part 60 having a gap (L) between the source and drain electrodes of 200 μm and a width (W) of 1000 μm is formed. Gold was deposited to form the source electrode 50 and the drain electrode 52.
Then, it heat-processed in the air at 300 degreeC for 1 hour in the hot-air heating furnace, and produced the thin-film transistor.
This thin film transistor has a field effect mobility of 60 cm 2 / V · sec, an On / Off ratio of 5 × 10 6 , a threshold voltage (Vth) of 7.1 V, and an S value of 1.1 V / dec. Thus, the thin film transistor exhibits normally-off characteristics. The output characteristics showed a clear pinch-off.
Table 1 shows the impurity amount of the target used for forming the semiconductor film, the element configuration, and the performance of the thin film transistor for the examples and comparative examples.
Figure JPOXMLDOC01-appb-T000001
Figure JPOXMLDOC01-appb-T000001
（Ｂ）半導体膜の評価
　石英ガラス基板上に、上記（Ａ）のスパッタリングと同じ条件にて半導体膜を形成した。この半導体膜は非晶質であった。その後、熱風加熱炉内で、空気中、３００℃で１時間熱処理した。得られた半導体膜のＸ線回折（ＸＲＤ）測定をしたところ、酸化インジウムのビックスバイト構造のピークが観察された。これにより、半導体膜が結晶質であることが確認できた。
　尚、半導体膜の熱処理条件を、空気中、４５０℃で５時間とし、同じくＸＲＤ測定した。３００℃にて熱処理したＸＲＤのピーク強度を比較したところ、３００℃で得られたピーク強度は、４５０℃で得られたピーク強度の約９８％であった。 (B) Evaluation of Semiconductor Film A semiconductor film was formed on a quartz glass substrate under the same conditions as the sputtering in (A) above. This semiconductor film was amorphous. Then, it heat-processed at 300 degreeC in the air for 1 hour in the hot-air heating furnace. When the X-ray diffraction (XRD) measurement of the obtained semiconductor film was performed, the peak of the bixbite structure of indium oxide was observed. This confirmed that the semiconductor film was crystalline.
Note that the heat treatment conditions for the semiconductor film were set at 450 ° C. for 5 hours in air, and XRD measurement was performed in the same manner. When the peak intensity of XRD heat-treated at 300 ° C. was compared, the peak intensity obtained at 300 ° C. was about 98% of the peak intensity obtained at 450 ° C.
　実施例１で作製した薄膜トランジスタの出力曲線を図４に、伝達曲線を図５に示す。図４は、ゲート電圧（Ｖｇｓ）を－５Ｖ～２５Ｖと変更したときの、ドレイン電圧（Ｖｄｓ）と同電流（Ｉｄｓ）の関係を示したものである。図５は、ゲート電圧（Ｖｇｓ）とドレイン電流（Ｉｄｓ）の関係を示したものであり、白丸からなる線は、ゲート電圧に対するドレイン電流を１／２乗した曲線であり、黒丸からなる線は、ゲート電圧に対するドレイン電流を示す曲線である。
　図４及び図５において、「ＸＥ－Ｙ」はＸ×１０－Ｙを意味する。例えば、１．０Ｅ－０５は１．０×１０－５である。 The output curve of the thin film transistor manufactured in Example 1 is shown in FIG. 4, and the transfer curve is shown in FIG. FIG. 4 shows the relationship between the drain voltage (Vds) and the same current (Ids) when the gate voltage (Vgs) is changed from -5V to 25V. FIG. 5 shows the relationship between the gate voltage (Vgs) and the drain current (Ids). The white circle line is a curve obtained by raising the drain current to the gate voltage by a power of 1/2, and the black circle line is 4 is a curve showing a drain current with respect to a gate voltage.
4 and 5, “XE-Y” means X × 10 −Y . For example, 1.0E-05 is 1.0 × 10 −5 .
実施例２
　スパッタリングターゲットとして、高純度酸化インジウムからなるターゲット（正４価以上の金属元素：Ｓｎ，Ｔｉ，Ｚｒの総合計：０．４ｐｐｍ（Ｓｎ：０．１ｐｐｍ）、正２価以下の金属元素：Ｎａ，Ｋ，Ｍｇ，Ｚｎの総合計：３ｐｐｍ）、湘南電子材料研究所作製］を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。
　この薄膜トランジスタの電界効果移動度は５２ｃｍ２／Ｖ・ｓｅｃ、Ｏｎ／Ｏｆｆ比は１０６であり、Ｖｔｈは５．５Ｖ、Ｓ値は１．５Ｖ／ｄｅｃ．で、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。
　また、半導体膜は結晶質性であった。 Example 2
As a sputtering target, a target composed of high-purity indium oxide (a total of positive tetravalent metal elements: Sn, Ti, Zr: 0.4 ppm (Sn: 0.1 ppm), a positive divalent or lower metal element: Na, A thin film transistor was manufactured in the same manner as in Example 1 except that the total of K, Mg, and Zn: 3 ppm), manufactured by Shonan Electronic Materials Laboratory] was used.
Field effect mobility of the thin film transistor is 52cm 2 / V · sec, On / Off ratio is 10 6, Vth is 5.5V, S value is 1.5V / dec. Thus, the thin film transistor exhibits normally-off characteristics. The output characteristics showed a clear pinch-off.
The semiconductor film was crystalline.
比較例１
　スパッタリングターゲットとして、純度３Ｎの酸化インジウムからなるターゲット（正４価以上の金属元素：Ｓｎ，Ｔｉ，Ｚｒの総合計：１２０ｐｐｍ（Ｓｎ：３０ｐｐｍ）、正２価以下の金属元素：Ｎａ，Ｋ，Ｍｇ，Ｚｎの総合計：６０ｐｐｍ）を用いた他は、実施例１と同様にして、薄膜トランジスタを作製した。
　この薄膜トランジスタの電界効果移動度は４６ｃｍ２／Ｖ・ｓｅｃ、Ｏｎ／Ｏｆｆ比は２．５×１０５であり、Ｖｔｈは－１．２Ｖ、Ｓ値は２．４Ｖ／ｄｅｃ．で、ノーマリーオンの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。
　また、半導体膜は結晶質性であった。 Comparative Example 1
As a sputtering target, a target made of indium oxide with a purity of 3N (total tetravalent or higher metal elements: Sn, Ti, Zr total: 120 ppm (Sn: 30 ppm), positive divalent or lower metal elements: Na, K, Mg , Zn was used in the same manner as in Example 1 except that the total amount of Zn was 60 ppm).
This thin film transistor has a field effect mobility of 46 cm 2 / V · sec, an On / Off ratio of 2.5 × 10 5 , a Vth of −1.2 V, and an S value of 2.4 V / dec. Thus, the thin film transistor exhibits normally-on characteristics. The output characteristics showed a clear pinch-off.
The semiconductor film was crystalline.
　このように、実施例のように純度が高い酸化インジウム焼結体ターゲットから成膜して得られた結晶質酸化インジウム膜を薄膜トランジスタに使用することにより、電界効果移動度、Ｏｎ／Ｏｆｆ比及びＳ値の良好なトランジスタ特性を得ることができる。 Thus, by using a crystalline indium oxide film obtained by forming a film of an indium oxide sintered target having a high purity as in the embodiment for a thin film transistor, field effect mobility, On / Off ratio, and S Transistor characteristics with good values can be obtained.
実施例３
　図６に示すエッチストッパー型の薄膜トランジスタを、フォトレジスト法にて作製した。
　熱酸化膜（ＳｉＯ２膜）付きの導電性シリコン基板１０上に、実施例１と同様にして、高純度酸化インジウムからなるターゲット（正４価以上の金属元素：Ｓｎ，Ｔｉ，Ｚｒの総合計：０．０９ｐｐｍ（Ｓｎ：０．０２ｐｐｍ）、正２価以下の金属元素：Ｎａ，Ｋ，Ｍｇ，Ｚｎの総合計：０．８ｐｐｍ）を用いて、スパッタリング法で５０ｎｍの半導体膜４０を成膜した。
　その後、エッチストッパーとなる層として、ＳｉＯ２をＲＦスパッタにて、酸素分圧１５％、アルゴン８５％の条件にて、３００ｎｍ成膜した。
このＳｉＯ２付き半導体膜上にレジストを塗布し、８０℃で１５分間プレベークした。その後、マスクを通してＵＶ光（光強度：３００ｍＪ／ｃｍ２）をレジスト膜に照射し、その後、３ｗｔ％のテトラメチルアンモニウムハイドロオキサイド（ＴＭＡＨ）にて現像した。純水で洗浄後、レジスト膜を１３０℃で１５分ポストベークし、ＣＦ４を用いたドライエッチングによりＳｉＯ２をエッチングして所望の形状のエッチストッパー７０を形成した。
　その後、半導体膜４０、ゲート絶縁膜（熱酸化膜）３０及びエッチストッパー７０上に、モリブデン金属膜を３００ｎｍ成膜した。
　モリブデン金属膜にレジストを塗布し、８０℃で１５分間プレベークした。その後、マスクを通してＵＶ光（光強度：３００ｍＪ／ｃｍ２）をレジスト膜に照射し、その後、３ｗｔ％のテトラメチルアンモニウムハイドロオキサイド（ＴＭＡＨ）にて現像した。純水で洗浄後、レジスト膜を１３０℃で１５分ポストベークし、所望の形状のソース・ドレイン電極形状のレジストパターンを形成した。
　レジストパターン付き基板を、燐酸・酢酸・硝酸の混合酸で処理することで、モリブデン金属膜をエッチングし、ソース電極５０及びドレイン電極５２を形成した。同時に、半導体膜４０のゲート絶縁膜３０に接する部分も同時にエッチングした。その後レジストを剥離し、純水で洗浄しエアーブローして乾燥させ、薄膜トランジスタ（チャンネル部６０のソース・ドレイン電極間間隙（Ｌ）が２００μｍ、幅（Ｗ）が１０００μｍ）を作製した。
　その後、この薄膜トランジスタを熱風加熱炉内で空気中、３００℃で１時間熱処理した。 Example 3
The etch stopper type thin film transistor shown in FIG. 6 was manufactured by a photoresist method.
On a conductive silicon substrate 10 with a thermal oxide film (SiO 2 film), in the same manner as in Example 1, a target made of high-purity indium oxide (a total of positive tetravalent or higher metal elements: Sn, Ti, Zr) : 0.09 ppm (Sn: 0.02 ppm), and a metal element having a positive divalent value or less: Total of Na, K, Mg, Zn: 0.8 ppm) is used to form a 50 nm semiconductor film 40 by sputtering. did.
After that, as a layer to be an etch stopper, SiO 2 was deposited by RF sputtering at 300 nm under conditions of oxygen partial pressure of 15% and argon of 85%.
A resist was applied on the semiconductor film with SiO 2 and prebaked at 80 ° C. for 15 minutes. Thereafter, the resist film was irradiated with UV light (light intensity: 300 mJ / cm 2 ) through a mask, and then developed with 3 wt% tetramethylammonium hydroxide (TMAH). After washing with pure water, the resist film was post-baked at 130 ° C. for 15 minutes, and SiO 2 was etched by dry etching using CF 4 to form an etch stopper 70 having a desired shape.
Thereafter, a molybdenum metal film having a thickness of 300 nm was formed on the semiconductor film 40, the gate insulating film (thermal oxide film) 30, and the etch stopper 70.
A resist was applied to the molybdenum metal film, and prebaked at 80 ° C. for 15 minutes. Thereafter, the resist film was irradiated with UV light (light intensity: 300 mJ / cm 2 ) through a mask, and then developed with 3 wt% tetramethylammonium hydroxide (TMAH). After washing with pure water, the resist film was post-baked at 130 ° C. for 15 minutes to form a resist pattern having a desired source / drain electrode shape.
The substrate with a resist pattern was treated with a mixed acid of phosphoric acid / acetic acid / nitric acid to etch the molybdenum metal film, thereby forming the source electrode 50 and the drain electrode 52. At the same time, the portion of the semiconductor film 40 in contact with the gate insulating film 30 was also etched. Thereafter, the resist was peeled off, washed with pure water, dried by air blowing, and a thin film transistor (a gap (L) between the source and drain electrodes of the channel portion 60 was 200 μm and a width (W) was 1000 μm) was produced.
Thereafter, this thin film transistor was heat-treated at 300 ° C. for 1 hour in air in a hot air heating furnace.
　この薄膜トランジスタの電界効果移動度は６２ｃｍ２／Ｖ・ｓｅｃ、Ｏｎ－Ｏｆｆ比は３×１０７であり、Ｖｔｈは６．８Ｖ、Ｓ値は０．９Ｖ／ｄｅｃ．で、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。ゲート電極に２０Ｖ電圧を１００分間印加した後のシフト電圧（Ｖｔｈ）は、０．２５Ｖであった。
　半導体膜は結晶質であった。 This thin film transistor has a field effect mobility of 62 cm 2 / V · sec, an On-Off ratio of 3 × 10 7 , a Vth of 6.8 V, and an S value of 0.9 V / dec. Thus, the thin film transistor exhibits normally-off characteristics. The output characteristics showed a clear pinch-off. The shift voltage (Vth) after applying a 20 V voltage to the gate electrode for 100 minutes was 0.25 V.
The semiconductor film was crystalline.
比較例２
　スパッタリングターゲットに、純度３Ｎの酸化インジウムからなるターゲット（正４価以上の金属元素：Ｓｎ，Ｔｉ，Ｚｒの総合計：１２０ｐｐｍ（Ｓｎ：３０ｐｐｍ）、正２価以下の金属元素：Ｎａ，Ｋ，Ｍｇ，Ｚｎの総合計：６０ｐｐｍ）からなるターゲットを使用した他は、実施例３と同様にして薄膜トランジスタを作製した。 Comparative Example 2
Sputtering target made of indium oxide having a purity of 3N (positive tetravalent or higher metal elements: Sn, Ti, Zr total: 120 ppm (Sn: 30 ppm), positive divalent or lower metal elements: Na, K, Mg , Zn total amount: 60 ppm) A thin film transistor was fabricated in the same manner as in Example 3 except that a target consisting of 60 ppm was used.
　この薄膜トランジスタの電界効果移動度は４８ｃｍ２／Ｖ・ｓｅｃ、Ｏｎ／Ｏｆｆ比は１０７であり、Ｖｔｈは－２．８Ｖ、Ｓ値は１．９Ｖ／ｄｅｃ．で、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。ゲート電極に２０Ｖ電圧を１００分間印加した後のシフト電圧（Ｖｔｈ）は、０．４Ｖであった。
　半導体膜は結晶質であった。 Field effect mobility of the thin film transistor is 48cm 2 / V · sec, On / Off ratio is 10 7, Vth is -2.8 V, S value is 1.9V / dec. Thus, the thin film transistor exhibits normally-off characteristics. The output characteristics showed a clear pinch-off. The shift voltage (Vth) after applying 20V voltage to the gate electrode for 100 minutes was 0.4V.
The semiconductor film was crystalline.
　このようにフォトリソグラフィー及びリフトオフプロセスによりエッチストッパー型の薄膜トランジスタにおいても、純度の高い酸化インジウム焼結体ターゲットにより得た結晶質酸化インジウム薄膜を使用した場合はＳ値が低く、良好なトランジスタ特性を示す。 Thus, even in an etch stopper type thin film transistor by photolithography and a lift-off process, when a crystalline indium oxide thin film obtained with a high purity indium oxide sintered target is used, the S value is low, and good transistor characteristics are exhibited. .
実施例４
　チャンネル部６０のソース・ドレイン電極間間隙（Ｌ）を２０μｍ、幅（Ｗ）を１００μｍとした他は、実施例３と同様にして、薄膜トランジスタを作製した。 Example 4
A thin film transistor was manufactured in the same manner as in Example 3 except that the gap (L) between the source and drain electrodes of the channel portion 60 was 20 μm and the width (W) was 100 μm.
　この薄膜トランジスタの電界効果移動度は３２ｃｍ２／Ｖ・ｓｅｃ、Ｏｎ／Ｏｆｆ比は１０９であり、Ｖｔｈは３．５Ｖ、Ｓ値は０．４５Ｖ／ｄｅｃ．で、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。ゲート電極に２０Ｖ電圧を１００分間印加した後のシフト電圧（Ｖｔｈ）は、０．１８Ｖであった。
　半導体膜は結晶質であった。 Field effect mobility of the thin film transistor is 32cm 2 / V · sec, On / Off ratio is 10 9, Vth is 3.5 V, S value 0.45 V / dec. Thus, the thin film transistor exhibits normally-off characteristics. The output characteristics showed a clear pinch-off. The shift voltage (Vth) after applying 20V voltage to the gate electrode for 100 minutes was 0.18V.
The semiconductor film was crystalline.
実施例５
　チャンネル部６０のソース・ドレイン電極間間隙（Ｌ）を１０μｍ、幅（Ｗ）を２０μｍとした他は、実施例４と同様にして、薄膜トランジスタを作製した。 Example 5
A thin film transistor was manufactured in the same manner as in Example 4 except that the gap (L) between the source and drain electrodes of the channel portion 60 was 10 μm and the width (W) was 20 μm.
　この薄膜トランジスタの電界効果移動度は３６ｃｍ２／Ｖ・ｓｅｃ、Ｏｎ／Ｏｆｆ比は４．６×１０８であり、Ｖｔｈは３．２Ｖ、Ｓ値は０．４０Ｖ／ｄｅｃ．で、ノーマリーオフの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。ゲート電極に２０Ｖ電圧を１００分間印加した後のシフト電圧（Ｖｔｈ）は、０．１６Ｖであった。
　半導体膜は結晶質であった。
　実施例５で作製した薄膜トランジスタの伝達曲線を図７に示す。 This thin film transistor has a field effect mobility of 36 cm 2 / V · sec, an On / Off ratio of 4.6 × 10 8 , a Vth of 3.2 V, and an S value of 0.40 V / dec. Thus, the thin film transistor exhibits normally-off characteristics. The output characteristics showed a clear pinch-off. The shift voltage (Vth) after applying a 20V voltage to the gate electrode for 100 minutes was 0.16V.
The semiconductor film was crystalline.
A transfer curve of the thin film transistor manufactured in Example 5 is shown in FIG.
比較例３
　スパッタリングターゲットに、純度３Ｎの酸化インジウムからなるターゲット（正４価以上の金属元素：Ｓｎ，Ｔｉ，Ｚｒの総合計：１２０ｐｐｍ（Ｓｎ：３０ｐｐｍ）、正２価以下の金属元素：Ｎａ，Ｋ，Ｍｇ，Ｚｎの総合計：６０ｐｐｍ）からなるターゲットを使用した他は、実施例４と同様にして薄膜トランジスタを作製した。 Comparative Example 3
Sputtering target made of indium oxide having a purity of 3N (positive tetravalent or higher metal elements: Sn, Ti, Zr total: 120 ppm (Sn: 30 ppm), positive divalent or lower metal elements: Na, K, Mg , Zn total amount: 60 ppm) A thin film transistor was fabricated in the same manner as in Example 4 except that the target was used.
　この薄膜トランジスタの電界効果移動度は２７ｃｍ２／Ｖ・ｓｅｃ、Ｏｎ／Ｏｆｆ比は４×１０８であり、Ｖｔｈは－２．２Ｖ、Ｓ値は１．０Ｖ／ｄｅｃ．で、ノーマリーオンの特性を示す薄膜トランジスタであった。また、出力特性は明瞭なピンチオフを示した。ゲート電極に２０Ｖ電圧を１００分間印加した後のシフト電圧（Ｖｔｈ）は、０．３８Ｖであった。半導体膜は結晶質であった。 This thin film transistor has a field effect mobility of 27 cm 2 / V · sec, an On / Off ratio of 4 × 10 8 , a Vth of −2.2 V, and an S value of 1.0 V / dec. Thus, the thin film transistor exhibits normally-on characteristics. The output characteristics showed a clear pinch-off. The shift voltage (Vth) after applying 20V voltage to the gate electrode for 100 minutes was 0.38V. The semiconductor film was crystalline.
　実施例４の薄膜トランジスタは、素子サイズを特許文献３に記載の素子と同程度のチャンネル長（Ｌ）及び幅（Ｗ）を持つ。この場合でも、本発明では良好なトランジスタ特性を有するトランジスタが得られた。 The thin film transistor of Example 4 has the same channel length (L) and width (W) as those of the element described in Patent Document 3. Even in this case, a transistor having good transistor characteristics was obtained in the present invention.
　実施例５の薄膜トランジスタのソース・ドレイン電極間間隙（Ｌ）は１０μｍ、幅（Ｗ）は２０μｍである。チャンネル幅を狭くした場合においても、本発明では良好なトランジスタ特性を有するトランジスタが得られた。 The gap (L) between the source and drain electrodes of the thin film transistor of Example 5 is 10 μm, and the width (W) is 20 μm. Even when the channel width is narrowed, a transistor having good transistor characteristics is obtained in the present invention.
　本発明の薄膜トランジスタは、ディスプレイ用パネル、ＲＦＩＤタグ、Ｘ線ディテクタパネル・指紋センサ・フォトセンサ等のセンサ等に好適に使用できる。
　本発明の薄膜トランジスタの製造方法は、特に、チャンネルエッチ型の薄膜トランジスタの製造方法に適している。 The thin film transistor of the present invention can be suitably used for sensors such as display panels, RFID tags, X-ray detector panels, fingerprint sensors, and photosensors.
The thin film transistor manufacturing method of the present invention is particularly suitable for a channel etch type thin film transistor manufacturing method.
　上記に本発明の実施形態及び／又は実施例を幾つか詳細に説明したが、当業者は、本発明の新規な教示及び効果から実質的に離れることなく、これら例示である実施形態及び／又は実施例に多くの変更を加えることが容易である。従って、これらの多くの変更は本発明の範囲に含まれる。
　この明細書に記載の文献の内容を全てここに援用する。 Although several embodiments and / or examples of the present invention have been described in detail above, those skilled in the art will appreciate that these exemplary embodiments and / or embodiments are substantially without departing from the novel teachings and advantages of the present invention. It is easy to make many changes to the embodiment. Accordingly, many of these modifications are within the scope of the present invention.
The entire contents of the documents described in this specification are incorporated herein by reference.

Claims (11)

  1. 　結晶質酸化インジウム半導体膜を有し、前記半導体膜に含まれる全金属元素に対する正４価以上の金属元素の含有率が１０原子ｐｐｍ以下である薄膜トランジスタ。 A thin film transistor having a crystalline indium oxide semiconductor film and having a content of positive tetravalent or higher metal elements with respect to all metal elements contained in the semiconductor film of 10 atomic ppm or less.
  2. 　結晶質酸化インジウム半導体膜を有し、前記半導体膜に含まれる全金属元素に対する正４価以上の金属元素の含有率が１原子ｐｐｍ以下である薄膜トランジスタ。 A thin film transistor having a crystalline indium oxide semiconductor film and having a content of positive tetravalent or higher metal elements of 1 atomic ppm or less with respect to all metal elements contained in the semiconductor film.
  3. 　結晶質酸化インジウム半導体膜を有し、前記半導体膜に含まれる全金属元素に対する正４価以上の金属元素の含有率が０．１原子ｐｐｍ以下である薄膜トランジスタ。 A thin film transistor having a crystalline indium oxide semiconductor film and having a content of positive tetravalent or higher metal elements with respect to all metal elements contained in the semiconductor film being 0.1 atomic ppm or less.
  4. 　前記正４価以上の金属元素がＳｎである請求項１～３のいずれかに記載の薄膜トランジスタ。 4. The thin film transistor according to claim 1, wherein the positive tetravalent or higher metal element is Sn.
  5. 　さらに、前記半導体膜に含まれる全金属元素に対する正２価以下の金属元素の含有率が５０原子ｐｐｍ以下である請求項１～４のいずれかに記載の薄膜トランジスタ。 The thin film transistor according to any one of claims 1 to 4, wherein the content of metal elements having a positive divalent value or less relative to all metal elements contained in the semiconductor film is 50 atomic ppm or less.
  6. 　チャンネルエッチ型である請求項１～５のいずれかに記載の薄膜トランジスタ。 6. The thin film transistor according to claim 1, which is a channel etch type.
  7. 　エッチストッパー型である請求項１～５のいずれかに記載の薄膜トランジスタ。 6. The thin film transistor according to claim 1, which is of an etch stopper type.
  8. 　純度が９９．９９原子％以上の酸化インジウムターゲットを用いて半導体膜を成膜する成膜工程と、前記半導体膜を酸化処理する工程、及び／又は前記半導体膜を結晶化する工程を含む、請求項１～７のいずれかに記載の薄膜トランジスタの製造方法。 A film forming step of forming a semiconductor film using an indium oxide target having a purity of 99.99 atomic% or more, a step of oxidizing the semiconductor film, and / or a step of crystallizing the semiconductor film. Item 8. The method for producing a thin film transistor according to any one of Items 1 to 7.
  9. 　前記酸化インジウムターゲットの純度が９９．９９５原子％以上である請求項８に記載の薄膜トランジスタの製造方法。 The method of manufacturing a thin film transistor according to claim 8, wherein the purity of the indium oxide target is 99.995 atomic% or more.
  10. 　前記成膜工程をスパッタリングで実施し、スパッタリング中の雰囲気の酸素濃度を５～２０体積％とする請求項８又は９に記載の薄膜トランジスタの製造方法。 10. The method of manufacturing a thin film transistor according to claim 8, wherein the film forming step is performed by sputtering, and an oxygen concentration in an atmosphere during sputtering is set to 5 to 20% by volume.
  11. 　前記半導体膜を酸素の存在下に、１５０～４５０℃で０．１～１２００分間熱処理する請求項８～１０のいずれかに記載の薄膜トランジスタの製造方法。 11. The method of manufacturing a thin film transistor according to claim 8, wherein the semiconductor film is heat-treated at 150 to 450 ° C. for 0.1 to 1200 minutes in the presence of oxygen.
PCT/JP2009/005384 2008-10-23 2009-10-15 Thin film transistor having high-purity crystalline indium oxide semiconductor film, and method for manufacturing the thin film transistor WO2010047063A1 (en)

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JP5101719B2 (en) 2010-11-05 2012-12-19 日東電工株式会社 Transparent conductive film, method for producing the same, and touch panel provided with the same
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