201023357 六、發明說明： 【潑^明戶斤屬之_技_彳,好<員域^】 發明領域 本發明係關於一種具有高純度結晶質氧化銦所形成之 半導體膜的薄膜電晶體及其製造方法。 L· ^tr y 發明背景 近年來，顯示裝置的發展令人矚目，液晶顯示裝置和 EL顯不裝置等各種顯示裝置被積極地應用於個人電腦戋文 字處理器等之OA機ϋ。這些顯示裝置每—種都具有以透明 導電膜夾住顯示元件之三明治結構。 驅動上述顯示裝置的薄膜電晶體（TFT)等之開關__ 件，目前主要使用珍系的半導體膜。這是因為:％ 安定性、加工性的優點之外，有開關速度快等合適的除 該碎系薄膜-般可藉化學氣相沉積法(cvd)法來製作。201023357 VI. Description of the invention: [Spray of the genus of the genus _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ _ Its manufacturing method. BACKGROUND OF THE INVENTION In recent years, development of display devices has been attracting attention, and various display devices such as liquid crystal display devices and EL display devices have been actively applied to OA devices such as personal computer data processors. Each of these display devices has a sandwich structure in which a display member is sandwiched by a transparent conductive film. A switch for a thin film transistor (TFT) or the like of the above display device is mainly used for a semiconductor film. This is because: in addition to the advantages of stability and workability, there is a suitable switching speed, such as a fast switching speed, which can be produced by a chemical vapor deposition (cvd) method.
但疋’石夕系薄膜為非晶質時，開關速度較慢、 示高速的動畫等時有無法顯示圖像之難點。另外，/顯 的石夕系薄膜之情形中，雖然開關速度比較快，但是：：質 必須在赋以上的高温或者要利用雷射來加熱等，二曰化 :需要大量的能量和許多步驟。另外，石夕=造 壓元件也是性能優良的材料，但是在通上電流時^電 的經時變化會成為問題。 /、特性 作為用以獲得比矽系薄膜安定 膜同等的光透射k透料料_#料，以有化與^ 3 201023357 氧化鎵及氧化鋅㈣之魏姊，由氧化鋅和氧化鎮形 ^透明半導體薄膜被提_如，專利文獻υ。由氧化鋼、 氧化鎵及氧化鋅，或氧化鋅和氧化鎂形成之透明半導體 膜’具有在弱酸中腐钱性非常快的特徵。雖是這樣，但在 金屬薄膜_贿中也會被舰，而有在_透明半導體媒 上之金屬_時，會同時被钱_情形’對於只要選擇性地 蚀刻透明半導體膜上之金屬薄膜的情料言，並不適用。 另一方面，已知含有氧化銦的結晶質膜，尤其是多結 晶膜，容易發生缺氧，即使提高成麟之氧分壓，或進彳 ⑩ 氧化處理等’載子密度仍難以達到2xl〇+17cm_3。因此幾 乎沒有進行其作為半導體膜或TFT之嘗試。 另外，專利文獻2中記載具有使氧化銦含有正2價的金 屬氧化物之方鐵錳礦結構的氧化銦半導體膜。做了透過使 其含有正2價的金屬氧化物的方式來降低載子濃度的嘗 試然而，正2價之金屬氧化物的情形，有時會在方鐵猛礦 結構的能帶結構之能帶隙内形成雜質能階，這個情形有時 會使移動率降低。 〇 專利文獻3中記載使用結晶質氧化銦薄膜之薄膜電晶 體。但是’通道部的陷阱密度會有升高的情形。因此，有 無法充分地降低S值和，變成常開的電晶體等之問題。另 外，如果薄膜中的陷阱密度高，會因陷阱而有無法充分降 低關閉電流值之問題。 針對這點，專利文獻3中記載透過取氧化銦薄膜的膜厚 為20nm，可降低關閉電流值。然而，將膜厚控制在20nm， 4 201023357 並形成均勻，且大面積的膜，在技術上是困難的。因此， 可能會成為薄膜電晶體特性出現變異的原因。 【先前技術文獻】 專利文獻 專利文獻1 :特開2004-119525號公報 專利文獻2:國際公開第07/058248號公報 專利文獻3 :特開2008-130814號公報 【發明内容】 發明概要 本發明之目的係通過一種使用由結晶質氧化銦形成之 半導體膜的薄膜電晶體，並降低半導體膜的陷阱密度以提 供高性能的薄膜電晶體。 本發明人等發現，由結晶質氧化銦形成之半導體膜的 雜質，具體而言，即正4價以上的金屬元素，會對半導體膜 的陷阱密度產生影響。然後，確定透過將該金屬元素的含 有率設為預定值以下，可獲得高性能的薄膜電晶體之情 形，藉而完成本發明。 依據本發明，可提供以下的薄膜電晶體等。 1. 一種薄膜電晶體，其具有結晶質氧化銦半導體膜， 且相對於前述半導體膜中含有之全部金屬元素，正4價以上 的金屬元素含有率為10原子ppm以下。 2. —種薄膜電晶體，其具有結晶質氧化銦半導體膜， 且相對於前述半導體膜中含有之全部金屬元素，正4價以上 的金屬元素含有率為1原子ppm以下。 201023357 3. —種薄膜電晶體，其具有結晶質氧化銦半導體膜， 且相對於前述半導體膜中含有之全部金屬元素，正4價以上 的金屬元素含有率為0·1原子ppm以下。 4. 如第1項〜第3項之任一項記載的薄膜電晶體，其中 前述正4價以上的金屬元素為Sn。 5. 如第1項〜第4項之任一項記載的薄膜電晶體，更 且，其中相對於前述半導體膜中含有之全部金屬元素，正2 價以下的金屬元素之含有率在50原子ppm以下。 6. 如第1項〜第5項之任一項記載的薄膜電晶體，其係 通道蝕刻梨。 7. 如第1項〜第5項之任一項記載的薄膜電晶體，其係 蝕刻阻擋蜇。 8. —種如第1項〜第7項之任一項記載的薄膜電晶體之 製造方法，其包含使用純度為99.99原子°/〇以上的氧化銦靶 材使半導體膜成琪之成膜步驟和，氧化處理前述半導體膜 之步驟’及/或使前述半導體膜結晶化之步驟。 9. 如第8項記載之薄膜電晶體的製造方法，其中前述 氧化銦靶材的純度為99.995原子％以上。 10. 如第8項或第9項記載之薄膜電晶體的製造方法， 其係以濺鍵法來實施前述成膜步驟，且將濺鍍中之氛圍氣 的氧濃度設在5〜20體積％。 u.如第8項〜第1〇項之任一項記載的薄膜電晶體之製 造方法，其係在氧的存在下，以15〇〜450。(：熱處理前述半 導體膜0.1〜1200分鐘。 201023357 若依據本發明，因結晶質氧化銦薄膜的雜質濃度低， 可降低薄膜中，尤其是通道部分的陷阱密度。其結果可充 . 分降低s值。 圖式簡單說明 第1圖顯示本發明之通道蝕刻型薄膜電晶體的實施熊 樣之概略斷面圖。 〜 第2圖顯示本發明之蝕刻阻擋型薄膜電晶體的實施熊 樣之概略斷面圖。 第3圖由實施例1製作之通道姓刻型薄勝電晶體的概略 斷面圖。 第4圖顯示由實施例1製作之薄膜電晶體的 第5圖顯示由實施例1製作之薄膜電晶體的傳輸曲線圖。 第6圖由實施例3製作之侧阻擋型薄膜電晶體的概略 斷面圖。 第7圖顯示由實施例5製作之薄膜電晶體的傳輸曲線圖。 φ 【實施方式】 較佳實施例之詳細說明 本發明之薄膜電晶體(TFT) ’特徵在於其具有結晶質氧 化銦半導體膜，且相對於半導體膜所含之全部金屬元素， 正4價以上金屬元素的含有率為10原子ppm以下。 第1圖是顯示本發明之薄膜電晶體的實施態樣之概略 斷面圖。 '專膜電晶體1是將閘電極20夾在基板10與絕緣膜30之 間’並於問極絕緣膜3〇上積層半導體膜4〇作為活性層。此 201023357 外，分別設置源電極50和汲電極52以覆蓋半導體膜40的端 部附近。在由半導體膜40、源電極50和汲電極52圍出之部 分形成通道部60。 另外’第1圖的薄膜電晶體1是所謂的通道蝕刻型薄獏 電晶體。本發明之薄膜電晶體並未限定於通道蝕刻型薄膜 電晶體，可採用本技術領域中公知的元件結構。 第2圖是顯示本發明之薄膜電晶體的其他實施態樣之 概略斷面圖。另外，對與上述薄膜電晶體1相同的結構部件 附以同一編號，省略其說明。 薄膜電晶體2是蝕刻阻檔型薄膜電晶體。薄膜電晶體2 除形成蝕刻阻擋層70以覆蓋通道部6〇這點以外，與上述薄 祺電晶體1為相同的結構。分別設置源電極5〇和汲電極52以 覆蓋半導體膜40的端部附近及蝕刻阻擋層7〇的端部附近。 本發明中，使用由高純度的結晶質氧化銦形成之薄膜 做為半導體膜40。此處，所謂高純度，意指結晶質氧化銦 溥犋實質上不包含作為雜質的正4價以上之金屬元素。具體 而言，意指形成半導體膜之全部金屬中所占的正4價以上之 金屬元素的含有率為10原子ppm以下。透過極力降低該等之 含有率，可降低薄膜中或絕緣膜-半導體膜界面的陷阱密 度。其結果可降低s值。 薄膜中的雜質會造成電子的散射，引起移動率的降 低。雜質濃度如果低，就可以抑制散射’維持氧化鋼本來 所具有之两移動率。 另外，會有因雜質而在結晶構造中產生齋亂 益 ^ · ί»\ 201023357 法充分降低缺氧狀態而變成顯示常開動作的薄膜電晶體之 情形。本發明中，因為使用雜質濃度極低的結晶質氧化銦 半導體膜，故可獲得常關，高移動率、低關閉電流值，而 且s值低，並顯示高動作安定性的高性能薄膜電晶體。 另外’本發明中常關定義為，閾值電壓的值為負（正) 之情形。閾值電壓由傳輸曲線(Id-Vg)圖的X截距求得。 尤其，將正4價以上的金屬元素之含有率設定在1〇原子 φ ppm以下，可藉而將室溫附近之半導體膜的載子密度保持於 低於2xl〇+17cm·3。藉此，可獲得良好的薄膜電晶體特性。 此外’半導體膜的載子密度在室溫附近以小於 2xl〇 cm為佳。載子密度在2xl〇+17cm·3以上，作為有 不驅動之虞。而，作為TFT即使已經驅動，也會有閾值電壓 大幅降為負值並顯示常開，或Οη/Off比變小之情形。 將正2價以下的金屬元素之含有率設定為50原子ppm以 下，可藉而提高所製得之TFT的移動率。 ® 正4價以上的金屬元素及正2價以下的金屬元素在薄膜 内以金屬氧化物的形式存在。 半導體膜中包含的正4價以上的金屬氧化物，是從氧化 ,、氧化鍅、氧化铪、氧化釩、氧化鈮、氧化鈕、氧化鉻、 氧，翻、氧化鎮、氧化料之正4價以上的重金屬氧化物， 及氧切、氧化錯、氧化錫、氧㈣、氧化録、氧化叙、氧 姓飾中選出之i種或2種以上的氧化物$些氧化物被捕捉到 結晶中時，會有生成載子的情形。其結果，在室溫附近的温 度下有無法將載子密度控制在小於2xlO+1W3之情形。 201023357 上述金屬氧化物中，尤其是氧化鈦、氧化鍅、氧化錫， 宜嚴密地加以管理。 半導趙膜中所含有之正2價以下的金屬氧化物，是從氧 化裡、氧化納、氧化卸、氧化麵、氧化绝、氡化鎂、氧化 約、氧化錄、氧化鋇等之正2價訂的驗、鹼土類屬氧化物 及氧化鋅中選出之1種或2種以上的氧化物。這些氧化物被 捕捉到結晶中時，有時會在能帶㈣形成雜質能階。其結 果，載子陷阱生成，有移動率降低之情形。 上述金屬氧化物中，尤其是氧化鈉、氧化鉀、氧化鎂、 氧化鈣、氧化辞，宜嚴密地加以管理。 本發明中，相對於半導體膜的全部金屬元素，正4價以 上之金屬氧化物的金屬元素(M4)之含有率在10原子ppm以 下以5原子PPm以下為佳，1原子ppm以下較佳，〇.5原子 ppm以下更佳，〇丨原子卩㈣以下特佳。原子比超過1〇原子 PPm時，耗子密度達到2xl〇+1W3以上的情形，並有不產 生TFT特性之情形。另外，作為TFT，即使已經驅動也會有 閾值電壓大幅降為負值而顯示常開’或關閉電流值增加 On/Off比變小之情形。另外還會有薄膜中及（或）絕緣膜半 導體膜界面的陷阱密度增加，S值增大之虞。 M4中，尤其是Sn含有率高時，因為元素的氧化能力 強’故栽子濃度增加’即使驅動TFT依然會有閾值電壓大幅 變為負值而顯示常開，或斷開電流值增加On/Off比減小之 清形。另外會有薄骐中及（或）絕緣膜半導體膜界面的陷阱 密度增加，8值增大之虞。Sn的含有率以1原子ppm以下為 201023357 佳，0.5原子ppm以下更好’ 0.1原子ppm以下特別合適。 — 本發明中，相對半導體膜的全部金屬元素，正2價以下 的金屬氧化物之金屬元素(M2)的含有率以5〇原子ppm以下 為佳。如果原子比超過50原子ppm，會有移動率降低，或不 起動TFT特性之情形。另外，會有薄膜中及（或）絕緣膜_半 導體膜界面的陷阱密度增加，S值增大之虞。 金屬元素(M2)的比例，以1〇原子ppm以下較佳，5原子 表 ppm以下更佳，1原子ppm以下特佳。 金屬元素(M)的比例是藉ICP-Mass(Inductively Coupled Plasma Mass)測定，可透過測定各元素的存在量求算出β 另外，金屬元素(Μ)的比例，可藉調整例如形成半導體 膜時使用之濺鑛把的各元素存在量的方式來實施。半導體 膜的組成大致與濺鑛把的組成一致。 本發明中，透過使用結晶質氧化銦半導體膜，在蝕刻 源電極50和汲電極52時，可抑制半導體膜被蝕。另外，還 φ 可提高TFT的耐久性。 另外，「結晶膜」係指，可利用X射線繞射確定結晶波 蜂之膜。 結晶膜可為單晶膜、磊晶膜及多晶膜的任一種，從容 易工業生產且可大面積化的觀點，以磊晶膜及多晶膜為 佳，特別合適的是多晶膜。 結晶質膜為多結晶膜的情形中，該多結晶質膜宜由奈 米明體形成。由X射線繞射使用Scherrer's equation求算之平 均結晶粒徑通常為5〇〇nm以下’以300nm以下為佳，15〇nm 11 201023357 以下較佳’ 80議以下更好。若大於5〇〇賺則會有微細化電 晶體時偏差增大之虞。 本發明的薄膜電晶體中，基板、閘電極、閘極絕緣膜、 源.汲電極等之構成元件，可使用公知者，並無特殊限制。 例如，各電極可使用A卜Cu、Au等之金屬薄膜，閘極 絕緣膜可使用氧化矽膜、氧化铪膜等之氧化物薄膜。 接著，說明本發明之薄膜電晶體的製造方法。However, when the 石'shishi film is amorphous, the switching speed is slow, and the high-speed animation or the like may cause difficulty in displaying an image. In addition, in the case of the Shixian film, although the switching speed is relatively fast, the quality must be above the high temperature or the laser is used for heating, etc., which requires a large amount of energy and many steps. In addition, Shi Xi = the pressure component is also a material with excellent performance, but the change with time of electricity when the current is applied may become a problem. /, characteristics as used to obtain the same light transmission than the lanthanide film stabilizer film _# material, with the chemical and ^ 3 201023357 gallium oxide and zinc oxide (four) Wei Wei, from zinc oxide and oxidized town shape ^ A transparent semiconductor film is proposed, for example, in the patent document υ. The transparent semiconductor film ' formed of oxidized steel, gallium oxide and zinc oxide, or zinc oxide and magnesium oxide has a characteristic that the rot is very fast in a weak acid. This is the case, but in the metal film _ bribes will also be ship, and there is a metal on the _ transparent semiconductor medium _, at the same time will be money _ case 'as long as the metal film on the transparent semiconductor film is selectively etched Unexpectedly, it does not apply. On the other hand, it is known that a crystalline film containing indium oxide, especially a polycrystalline film, is prone to oxygen deficiency, and it is difficult to achieve a carrier density of 2xl even if the oxygen partial pressure of Chenglin or the oxidation treatment of 彳10 is increased. +17cm_3. Therefore, almost no attempt has been made as a semiconductor film or TFT. Further, Patent Document 2 describes an indium oxide semiconductor film having a cubic iron-manganese structure in which indium oxide contains a positive divalent metal oxide. Attempts to reduce the concentration of the carrier by means of a metal oxide having a positive divalent value, however, the case of a positively valence metal oxide sometimes occurs in the band gap of the band structure of the square iron ore structure. An impurity level is formed, which sometimes causes a decrease in mobility.专利 Patent Document 3 describes a thin film transistor using a crystalline indium oxide thin film. However, the trap density of the channel section will increase. Therefore, there is a problem that the S value cannot be sufficiently lowered and the transistor is normally turned on. In addition, if the trap density in the film is high, there is a problem that the off current value cannot be sufficiently lowered due to the trap. In view of this, Patent Document 3 discloses that the film thickness of the indium oxide thin film is 20 nm, and the shutdown current value can be lowered. However, it is technically difficult to control the film thickness at 20 nm, 4 201023357 and form a uniform, large-area film. Therefore, it may become a cause of variation in the characteristics of the thin film transistor. [PRIOR ART DOCUMENT PATENT DOCUMENT PATENT DOCUMENT PATENT DOCUMENT PATENT DOCUMENT PATENT DOCUMENT PATENT DOCUMENT PATENT DOCUMENT PATENT DOCUMENT PATENT DOCUMENT PATENT DOCUMENT PRIOR ART The object is to provide a high-performance thin film transistor by using a thin film transistor using a semiconductor film formed of crystalline indium oxide and reducing the trap density of the semiconductor film. The present inventors have found that an impurity of a semiconductor film formed of crystalline indium oxide, specifically, a tetravalent or higher metal element affects the trap density of the semiconductor film. Then, it is determined that the high-performance thin film transistor can be obtained by setting the content of the metal element to a predetermined value or less, and the present invention has been completed. According to the present invention, the following thin film transistors and the like can be provided. 1. A thin film transistor having a crystalline indium oxide semiconductor film and having a tetravalent or higher metal element content of 10 atomic ppm or less with respect to all metal elements contained in the semiconductor film. 2. A thin film transistor having a crystalline indium oxide semiconductor film and having a tetravalent or higher metal element content of 1 atomic ppm or less with respect to all metal elements contained in the semiconductor film. 201023357. A thin film transistor having a crystalline indium oxide semiconductor film and having a tetravalent or higher metal element content of 0.1 atomic ppm or less with respect to all metal elements contained in the semiconductor film. 4. The thin film transistor according to any one of the preceding claims, wherein the positive tetravalent or higher metal element is Sn. 5. The thin film transistor according to any one of the items 1 to 4, wherein the content of the metal element having a positive valence or less is 50 atomic ppm with respect to all the metal elements contained in the semiconductor film. the following. 6. The thin film transistor according to any one of the items 1 to 5, wherein the film is etched into a pear. 7. The thin film transistor according to any one of the items 1 to 5, which is an etching stopper. The method for producing a thin film transistor according to any one of the items 1 to 7, comprising the step of forming a semiconductor film by using an indium oxide target having a purity of 99.99 atom/min or more. And a step of oxidizing the semiconductor film and/or a step of crystallizing the semiconductor film. 9. The method for producing a thin film transistor according to the eighth aspect, wherein the indium oxide target has a purity of 99.995 atom% or more. 10. The method for producing a thin film transistor according to Item 8 or 9, wherein the film forming step is performed by a sputtering method, and an oxygen concentration of the atmosphere in the sputtering is set to 5 to 20% by volume. . The method for producing a thin film transistor according to any one of the items 8 to 1 wherein the method is 15 to 450 in the presence of oxygen. (: heat treatment of the semiconductor film for 0.1 to 1200 minutes. 201023357 According to the present invention, since the impurity concentration of the crystalline indium oxide thin film is low, the trap density in the film, particularly the channel portion, can be lowered. BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing the implementation of the channel-etched thin film transistor of the present invention. Fig. 2 is a schematic cross-sectional view showing the implementation of the etching-blocking thin film transistor of the present invention. Fig. 3 is a schematic cross-sectional view of a channel-type thin-film transistor produced by the first embodiment. Fig. 4 is a view showing a film made of the film of the first embodiment. Fig. 6 is a schematic cross-sectional view showing a side barrier type thin film transistor produced in the third embodiment. Fig. 7 is a view showing a transmission curve of the thin film transistor produced in the fifth embodiment. DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The thin film transistor (TFT) of the present invention is characterized in that it has a crystalline indium oxide semiconductor film and is positive with respect to all metal elements contained in the semiconductor film. The content of the above metal element is 10 atomic ppm or less. Fig. 1 is a schematic cross-sectional view showing an embodiment of the thin film transistor of the present invention. 'Special film transistor 1 is a structure in which the gate electrode 20 is sandwiched between the substrate 10 and the insulating film. A semiconductor film 4 is laminated on the interposer insulating film 3A as an active layer between the films 30. In addition to 201023357, the source electrode 50 and the germanium electrode 52 are respectively disposed to cover the vicinity of the end portion of the semiconductor film 40. 40. The portion surrounded by the source electrode 50 and the drain electrode 52 forms the channel portion 60. Further, the thin film transistor 1 of Fig. 1 is a so-called channel-etched thin germanium transistor. The thin film transistor of the present invention is not limited to the channel. For the etched type thin film transistor, an element structure known in the art can be used. Fig. 2 is a schematic cross-sectional view showing another embodiment of the thin film transistor of the present invention, and is the same as the above-mentioned thin film transistor 1. The structural members are denoted by the same reference numerals, and the description thereof will be omitted. The thin film transistor 2 is an etching stopper type thin film transistor. The thin film transistor 2 is thinner than the above except that the etching stopper layer 70 is formed to cover the channel portion 6? The transistor 1 has the same structure. The source electrode 5 and the germanium electrode 52 are respectively provided to cover the vicinity of the end portion of the semiconductor film 40 and the end portion of the etching stopper layer 7A. In the present invention, the crystal is oxidized by high purity. The thin film formed of indium is used as the semiconductor film 40. Here, the high purity means that the crystalline indium oxide lanthanum does not substantially contain a positive tetravalent or higher metal element as an impurity. Specifically, it means forming a semiconductor film. The content of the metal element having a positive tetravalent or higher value in all the metals is 10 atomic ppm or less. By reducing the content ratio by the above, the trap density in the film or the insulating film-semiconductor film interface can be lowered. s value. Impurities in the film cause scattering of electrons, causing a decrease in mobility. If the impurity concentration is low, the scattering can be suppressed to maintain the two mobility rates inherent in the oxidized steel. In addition, there is a case where a thin film transistor which exhibits a normally open operation is formed by a method of sufficiently reducing the oxygen deficiency state in the crystal structure due to impurities. In the present invention, since a crystalline indium oxide semiconductor film having an extremely low impurity concentration is used, a high performance thin film transistor which is normally closed, has a high mobility, a low shutdown current value, and has a low s value and exhibits high operational stability can be obtained. . Further, the present invention is often defined as the case where the value of the threshold voltage is negative (positive). The threshold voltage is obtained from the X intercept of the transmission curve (Id-Vg) map. In particular, when the content of the metal element having a positive tetravalent or higher is set to 1 〇 atom φ ppm or less, the carrier density of the semiconductor film near the room temperature can be kept below 2x1 〇 + 17 cm·3. Thereby, good film crystal characteristics can be obtained. Further, the carrier density of the semiconductor film is preferably less than 2 x 1 〇 cm near room temperature. The carrier density is 2xl 〇 + 17 cm · 3 or more, as there is no driving. However, even if the TFT is already driven, there is a case where the threshold voltage is largely reduced to a negative value and the normally open is displayed, or the Οη/Off ratio becomes small. When the content of the metal element having a positive divalent or lower is set to 50 atomic ppm or less, the mobility of the obtained TFT can be increased. ® A metal element having a positive tetravalent or higher value and a metal element having a positive divalent or lower value are present as a metal oxide in the film. The positive tetravalent or higher metal oxide contained in the semiconductor film is a positive tetravalent value from oxidation, yttrium oxide, ytterbium oxide, vanadium oxide, yttrium oxide, oxidized knob, chromium oxide, oxygen, oxidized, oxidized, and oxidized material. The above heavy metal oxides, and oxygen, oxidized, tin oxide, oxygen (4), oxide, oxidized, oxygen, or other oxides selected from the oxides are captured in the crystals. There will be cases where a carrier is generated. As a result, there is a case where the carrier density cannot be controlled to be less than 2xlO+1W3 at a temperature near room temperature. 201023357 Among the above metal oxides, especially titanium oxide, antimony oxide and tin oxide, it should be strictly managed. The metal oxide having a positive divalent or lower content contained in the semi-conductive film is positive from oxidation, sodium oxide, oxidative desorption, oxidation surface, oxidation, magnesium telluride, oxidation, oxidation, and ruthenium oxide. One or two or more oxides selected from the group consisting of alkaline earth oxides and zinc oxide. When these oxides are trapped in the crystal, an impurity level is sometimes formed in the energy band (4). As a result, carrier traps are generated and there is a case where the mobility is lowered. Among the above metal oxides, in particular, sodium oxide, potassium oxide, magnesium oxide, calcium oxide, and oxidized words are preferably managed closely. In the present invention, the content of the metal element (M4) of the tetravalent or higher metal oxide is preferably 10 atomic ppm or less, more preferably 5 atomic ppm or less, and preferably 1 atomic ppm or less, based on the total metal element of the semiconductor film. 〇.5 atomic ppm or less is more preferable, and 〇丨 atomic 卩 (four) or less is particularly preferable. When the atomic ratio exceeds 1 〇 atom of PPm, the density of the mouse reaches 2x1 〇 +1 W3 or more, and there is a case where TFT characteristics are not generated. Further, as the TFT, even if it has been driven, there is a case where the threshold voltage is largely lowered to a negative value and the normally-on or 'off-current value is increased. In addition, there is an increase in trap density at the interface between the film and/or the insulating film semiconductor film, and an increase in the S value. In M4, especially when the Sn content is high, since the oxidation ability of the element is strong, the concentration of the plant is increased. Even if the TFT is driven, the threshold voltage is largely changed to a negative value and the display is normally open, or the off current value is increased. Off is smaller than the clear shape. In addition, there is an increase in the trap density at the interface of the thin film and/or the insulating film semiconductor film, and the value of 8 increases. The content of Sn is preferably 1 ,030 ppm or less, more preferably 0.5 atomic ppm or less, more preferably 0.1 atomic ppm or less. In the present invention, the content of the metal element (M2) of the metal oxide having a positive divalent or lower value is preferably 5 〇 atomic ppm or less with respect to all the metal elements of the semiconductor film. If the atomic ratio exceeds 50 atomic ppm, there is a case where the mobility is lowered or the characteristics of the TFT are not activated. In addition, there is a possibility that the trap density at the interface of the film and/or the insulating film_semiconductor film increases, and the S value increases. The ratio of the metal element (M2) is preferably 1 〇 atomic ppm or less, more preferably 5 atomic ppm or less, and particularly preferably 1 atomic ppm or less. The ratio of the metal element (M) is measured by ICP-Mass (Inductively Coupled Plasma Mass), and the amount of each element can be measured to calculate β. In addition, the ratio of the metal element (Μ) can be adjusted by, for example, forming a semiconductor film. It is implemented in the form of the amount of each element of the splash. The composition of the semiconductor film is approximately the same as the composition of the sputtering. In the present invention, by using the crystalline indium oxide semiconductor film, when the source electrode 50 and the germanium electrode 52 are etched, the semiconductor film can be suppressed from being etched. In addition, φ can improve the durability of the TFT. Further, "crystalline film" means that a film of a crystal wave bee can be determined by X-ray diffraction. The crystal film may be any one of a single crystal film, an epitaxial film, and a polycrystalline film. From the viewpoint of easy industrial production and large area, an epitaxial film and a polycrystalline film are preferable, and a polycrystalline film is particularly suitable. In the case where the crystalline film is a polycrystalline film, the polycrystalline film is preferably formed of a nanocrystalline body. The average crystal grain size calculated by Scherrer's equation by X-ray diffraction is usually 5 〇〇 nm or less, preferably 300 nm or less, and 15 〇 nm 11 201023357 or less is preferably 8% or less. If it is greater than 5 〇〇, there will be a slight increase in the deviation of the transistor. In the thin film transistor of the present invention, constituent elements such as a substrate, a gate electrode, a gate insulating film, and a source/germanium electrode can be used, and are not particularly limited. For example, a metal thin film such as A or Cu or Au may be used for each electrode, and an oxide thin film such as a hafnium oxide film or a hafnium oxide film may be used as the gate insulating film. Next, a method of producing the thin film transistor of the present invention will be described.
本發明的製造方法包含成膜氧化銦半導體臈之成膜步 驟和，氧域理半導韻之㈣，及/或結晶化之㈣。& G 外，閘電極、閘極絕緣膜、源.汲電極等之構成元件，可 藉由公知的方法來形成。 例如，將由Al、Cu、Au等的金屬薄膜形成之閘電極形 成於基板上’然後在其上形成由氧化石夕膜、氧化給膜等形 成之氧化物薄膜作為閘極絕緣膜。然後在其上安裝金屬遮 罩，僅在必要部分形成由氧化銦膜形成之半導體膜。然後， 使用金屬遮罩，透過在必要部分形成源·汲電極，可製造 薄膜電晶體。 © 半導體骐的成膜有濺鍍法、離子鍍法、蒸鍍法等。其 中以濺鍍法為佳。 激錢法中，以使用燒結靶材之方法為佳。具體而言， 以"."原子％以上’或99.995原子％(4N)以上之高純度氧化 銦的燒結耙材為佳。燒結靶材可藉本技術領域公知的方法 來製造。 藉由使用高純度的氧化銦燒結體靶材，可獲得雜質濃 12 201023357 度極低的結晶質氧化銦薄膜。 濺鍍條件可根據使用之靶材或半導體膜的膜厚等進行 - 適宜調整。濺鍍方法可使用高頻濺鍍法、直流濺鍍法、交 流濺鍍法。其中，直流濺鍍法、交流濺鍍法成膜速度快， 適宜使用。 宜使成膜過程中有氧存在。透過使濺鍍中有氧存在， 在接下來的氧化處理步驟中，可有效地進行氧化處理。 _ 濺鍍中氛圍氣的氧濃度以5〜20體積°/〇為佳，前述氧濃 度以7〜17%更佳，8〜14體積％是特別好的。 本發明之薄膜電晶體的製造方法中，半導體膜形成 後，進行氧化處理薄膜的步驟及/或結晶化薄膜之步驟。 半導體薄膜的結晶化及氧化處理中，可在氧存在下使 用燈退火裝置、雷射光退火裴置、熱風加熱裝置、接觸加 熱裝置等。 在氧的存在下，宜用150〜450°C，0.1〜1200分鐘的條件 φ 熱處理半導體膜。低於15〇°c時，會有半導體膜無法充分結晶 化之情形，超過450°C時會對基板或半導體膜帶來損傷。熱處 理溫度以180°C〜350。(：更佳，特別好的是2〇〇°c〜300。(：。 另外，熱處理時間不足0.1分鐘時，會有熱處理時間過 紐使膜的結晶化不充分之情形，超過12〇〇分鐘時則過於花 費時間而不具生產性。熱處理時間分鐘〜6〇〇分鐘更 佳’尤為合宜的是5分鐘〜60分鐘。 此外’半導體膜的結晶化及/或氧化處理，可在半導體 膜形成後立即實施，另外亦可在源·汲電極等其他構成元 13 201023357 件形成後實施。 本發明的製造方法尤其適用於通道触刻型薄膜電晶體 的製造方法。因為本發明之半導體膜為結晶質，故在從μ 等之金屬薄膜形成源·汲電極及通道部的方法上，可以採 用使用光微影法(photolithography)之蝕刻程序。亦即，用蝕 刻液除去金屬薄膜時，半導體膜未受到敍刻，可選擇性地 蝕刻金屬薄膜。另外，亦可適用於蝕刻阻擋型薄膜電晶體 的製造方法。 實施例 在實施例中，「ppm」意指原子ppm。 實施例1 (A)薄膜電晶體的製作 製作示於第3圖之通道姓刻型薄膜電晶體。 使用附著1 OOnm厚的熱氧化膜（Si〇2膜）之導電性矽基 板10。熱氧化膜提供作為閘極絕緣膜3〇之機能，導電性矽 部提供作為閘電極20之機能。 使用由純度4N以上的高純度氧化銦（湘南電子材料研 究所製）製成之靶材（正4價以上的金屬元素：Sn、Ti、&的 總合計：0.09ppm(Sn : 0.02ppm)，正2價以下的金屬元素： Na、K、Mg、Zn的總合計：〇.8ppm)，利用濺鍵法在閘極絕 緣膜30上使50nm的半導體膜40成膜。 另外’用 ICP-Mass(Inductively Coupled Plasma Mass) 測定靶材的雜質。 漱鑛是抽真空至背壓為5><1〇->3後，邊流通氬氣 14 t 201023357 9.0sccm，氧氣l.Osccm ’邊將壓力調整到〇.2Pa，將T-S間距 設成10cm，基板溫度設為室溫，在濺鍍功率100W下進行。 將金屬遮罩設置在半導體膜40上，於通道部60的兩端 附近蒸鑛金而形成源電極50及j：及電極52，以便形成源.j：及 電極間間隙(L)為2〇Ομιη、寬(W)為ΙΟΟΟμπι的通道部60。 然後’在熱風加熱爐内，於空氣中以300°C熱處理1小 時，製作成薄膜電晶體。 該薄膜電晶體的場效移動率為60cm2/V . sec，〇n/〇ff 比為5χ106 ’閾值電壓(Vth)為7.1V，S值為l.lV/dec.，是顯示 常關特性之薄膜電晶體。另外，輸出特性顯示明顯的夾止。 就實施例及比較例，將形成半導體膜時使用之靶材的 雜質量、元件構成及薄膜電晶體的性能示於表1。 [表1] — ., 實施例1 實施例2 比較例1 實施例3 比較例2 實施例4 實施例5 比較例3 把材雜 正4價以上的 金展元素 0.09 0.4 120 0.09 120 0.09 0.09 120 質量 (Ppm) 正2價以下的 金属元音 0.8 3 60 0.8 60 0.8 0.8 60 --— — 「Sn含量 0.02 0.1 30 0.02 30 0.02 0.02 30 形狀 - 通道钱刻 通道姓刻 通道蝕刻 蝕刻阻播 蝕刻阻擋 蝕刻阻擋 蝕刻阻擋 蝕刻阻擋 使用製程 金屬遮罩 金屬遮革 金屬遮罩 光微影 剝離 光微影 剝離 光微影 剝離 光微影 制齙 光微影 剝離 媒厚度(nm) 50 50 50 50 50 50 50 50 ^Χμιη) 1000/200 1000/200 1000/200 1000/200 1000/200 100/20 20/10 100/20 移動率(cm2/Vs) 60 52 46 62 48 32 36 27 比 5.〇χ106 Ι.ΟχΙΟ6 2.5χ105 3.0χ107 Ι.ΟχΙΟ7 Ι.ΟχΙΟ9 4.6x10® 4.0χ108 閎值^電壓(Vtfa) 7.1 5.5 -1.2 6.8 •2.8 3.5 3.2 2.2 5>1a(V/clec) 1.10 1.50 2.40 0.90 1.90 0.45 0.40 1.00 3值冤壓的漂移量(V) 】〇〇ir»in - - - 0.25 0.40 0.18 0.16 0.38 W:源.汲電極寬L·:源·汲電極間間隙 (B)半導體膜的評估 於石英玻璃基板上，用與上述(A)的濺鍍相同之條件形 15 201023357 成半導體膜。該半導體膜為非晶質。然後’在熱風加熱爐 内’於空氣中以300°C熱處理1小時。進行獲得之半導體膜 的X射線繞射(XRD)測定時，觀察到氧化銦的方鐵猛礦結構 的波峰。藉此可確認半導體膜為結晶質。 另外’將半導體膜的熱處理條件定為空氣中，以45〇。〇 處理5小時，並進行相同的XRD測定。比較300°C下經熱處 理之XRD的波峰強度時，在300°C獲得之波峰強度約為在 450°C獲得之波峰強度的98〇/〇。 由實施例1製作之薄膜電晶體的輸出曲線示於第4圖， ® 傳輸曲線示於第5圖。第4圖是顯示將閘極電壓(Vgs)在-5V 〜25V變更時的汲極電壓(Vds)與同極電流(Ids)之關係。第5 圖是顯示閘極電壓(Vgs)與汲極電流(Ids)的關係之圖式，由 白色圓點形成的曲線是相對於閘極電壓之將汲極電流乘以 1/2的曲線’由黑色圓點形成的曲線是顯示相對於閘極電壓 之汲極電流的曲線。 在第4圖及第5圖中，「χΕ_γ」意指χχΐ〇_γ。例如，i.OE_〇5 為 1.0χ10_5。 ❿ 實施例2 除使用由高純度氧化銦形成之靶材（正4價以上的金屬 元素·· Sn、Ti、Zr的總合計：0.4ppm(Sn : 〇」PPm)，正2價 以下的金屬元素：Na、K、Mg、Zn的總合計：3ppm)，湘 南電子材料研究所製]作為減鑛把以外，與實施例1同樣地 處理，製作薄膜電晶體。 該薄膜電晶體的場效移動率為52Cni2/V . sec，On/Off 16 201023357 比為10，Vth為5.5V，S值為1.5V/dec.，是顯示常關特性之 薄膜電晶體。另外，輸出特性顯示明顯的失止。 另外’半導體膜為結晶質性質。 比較例1The production method of the present invention comprises a film formation step of forming a film of indium oxide semiconductor and a (4) oxygen atomic semiconducting phase, and/or crystallization (4). In addition to the & G, constituent elements such as a gate electrode, a gate insulating film, and a source/germanium electrode can be formed by a known method. For example, a gate electrode formed of a metal thin film of Al, Cu, Au or the like is formed on a substrate. Then, an oxide film formed of an oxidized oxide film, an oxide film, or the like is formed thereon as a gate insulating film. Then, a metal mask is mounted thereon, and a semiconductor film formed of an indium oxide film is formed only in a necessary portion. Then, a thin film transistor can be manufactured by using a metal mask to form a source/germanium electrode in a necessary portion. © Film formation of semiconductor germanium includes sputtering, ion plating, vapor deposition, and the like. Among them, sputtering is preferred. In the method of stimulating money, a method of using a sintered target is preferred. Specifically, a sintered coffin of high purity indium oxide of "." atomic % or more or 99.995 atomic % (4N) or more is preferred. The sintered target can be made by methods well known in the art. By using a high-purity indium oxide sintered body target, a crystalline indium oxide thin film having an extremely low impurity concentration of 12,023,533 357 can be obtained. The sputtering conditions can be appropriately adjusted depending on the thickness of the target or semiconductor film to be used. The sputtering method can be performed by high frequency sputtering, direct current sputtering, or alternating sputtering. Among them, the direct current sputtering method and the alternating current sputtering method have a high film forming speed and are suitable for use. It is preferred to have oxygen in the film formation process. By allowing oxygen to exist in the sputtering, the oxidation treatment can be efficiently performed in the subsequent oxidation treatment step. The oxygen concentration of the atmosphere in the sputtering is preferably 5 to 20 vol / ha, and the oxygen concentration is preferably 7 to 17%, particularly preferably 8 to 14 vol%. In the method for producing a thin film transistor of the present invention, after the semiconductor film is formed, the step of oxidizing the film and/or the step of crystallizing the film are performed. In the crystallization and oxidation treatment of the semiconductor thin film, a lamp annealing device, a laser annealing device, a hot air heating device, a contact heating device, or the like can be used in the presence of oxygen. In the presence of oxygen, the semiconductor film is preferably heat-treated at 150 to 450 ° C for 0.1 to 1200 minutes. When the temperature is lower than 15 °C, the semiconductor film may not be sufficiently crystallized, and when it exceeds 450 °C, the substrate or the semiconductor film may be damaged. The heat treatment temperature is from 180 ° C to 350 ° C. (: Better, especially good is 2〇〇°c~300. (:. In addition, when the heat treatment time is less than 0.1 minutes, there is a case where the heat treatment time is too long to make the crystallization of the film insufficient, more than 12 minutes. It takes too much time and is not productive. The heat treatment time is preferably ~6 minutes in minutes. It is especially suitable for 5 minutes to 60 minutes. In addition, the crystallization and/or oxidation treatment of the semiconductor film can be formed after the semiconductor film is formed. It can be carried out immediately, or it can be carried out after formation of other constituent elements such as source/tantalum electrodes 13 201023357. The manufacturing method of the present invention is particularly suitable for a method for manufacturing a channel-touch type thin film transistor because the semiconductor film of the present invention is crystalline. Therefore, in the method of forming the source/germanium electrode and the channel portion from the metal thin film such as μ, an etching process using photolithography can be employed. That is, when the metal thin film is removed by the etching liquid, the semiconductor film is not subjected to the semiconductor film. The metal film can be selectively etched, and can also be applied to a method for manufacturing an etch barrier film transistor. Embodiments In the examples, "ppm" Refers to the atomic ppm.Example 1 (A) Preparation of Thin Film Transistor A channel-type thin film transistor of the channel name shown in Fig. 3 was fabricated. Conductivity of a thermal oxide film (Si〇2 film) having a thickness of 1 OO nm was used. The substrate 10 is provided with a function as a gate insulating film 3, and a conductive beak is provided as a gate electrode 20. The high-purity indium oxide (manufactured by Shonan Electronic Materials Research Institute) having a purity of 4 N or more is used. Target (metal element of positive tetravalent or higher: total of Sn, Ti, & total: 0.09ppm (Sn: 0.02ppm), metal element of positive or lower valence: total of Na, K, Mg, Zn: 〇 .8 ppm), a 50 nm semiconductor film 40 was formed on the gate insulating film 30 by a sputtering method. Further, the impurity of the target was measured by ICP-Mass (Inductively Coupled Plasma Mass). The antimony was vacuumed to back pressure. After 5 <1〇->3, argon gas 14 t 201023357 9.0 sccm, oxygen l.Osccm ', the pressure is adjusted to 〇.2Pa, the TS pitch is set to 10 cm, and the substrate temperature is set to room temperature. The sputtering power is performed at 100 W. A metal mask is placed on the semiconductor film 40 at the channel portion 6 The source electrodes 50 and j: and the electrode 52 are formed by vaporizing the ore near both ends of 0 to form a channel portion 60 having a source .j: and an interelectrode gap (L) of 2 μm and a width (W) of ΙΟΟΟμπι. 'In a hot air heating furnace, heat-treated at 300 ° C for 1 hour in air to prepare a thin film transistor. The field effect mobility of the thin film transistor is 60 cm 2 /V . sec, 〇n / 〇ff ratio is 5 χ 106 'threshold The voltage (Vth) is 7.1 V, and the S value is l.lV/dec., which is a thin film transistor showing a normally-off characteristic. In addition, the output characteristics show significant pinch. In the examples and comparative examples, the impurity amount, the element constitution, and the properties of the thin film transistor used for forming the semiconductor film are shown in Table 1. [Table 1] - ., Example 1 Example 2 Comparative Example 1 Example 3 Comparative Example 2 Example 4 Example 5 Comparative Example 3 A gold alloy element having a tetravalent or higher valence of 0.09 0.4 120 0.09 120 0.09 0.09 120 Mass (Ppm) Metal vowels below the positive price of 0.8 3 60 0.8 60 0.8 0.8 60 --- "Sn content 0.02 0.1 30 0.02 30 0.02 0.02 30 Shape - Channel channel engraved channel engraved channel etching etch stop etching block Etch Obstruction Etch Block Etch Block Use Process Metal Mask Metal Occlusion Metal Mask Photolithography Peeling Light Micro-Film Peeling Photolithography Peeling Light Micro-Shadowing Micro-Film Peeling Media Thickness (nm) 50 50 50 50 50 50 50 50 ^Χμιη) 1000/200 1000/200 1000/200 1000/200 1000/200 100/20 20/10 100/20 Movement rate (cm2/Vs) 60 52 46 62 48 32 36 27 Ratio 5.〇χ106 Ι. ΟχΙΟ6 2.5χ105 3.0χ107 Ι.ΟχΙΟ7 Ι.ΟχΙΟ9 4.6x10® 4.0χ108 闳value^voltage (Vtfa) 7.1 5.5 -1.2 6.8 •2.8 3.5 3.2 2.2 5>1a(V/clec) 1.10 1.50 2.40 0.90 1.90 0.45 0.40 1.00 3 Value drift (V) 〇〇ir»in - - - 0.25 0.40 0.18 0.16 0.38 W: source. 汲 electrode width L·: source/汲 electrode gap (B) evaluation of the semiconductor film on the quartz glass substrate, using the same condition as the above-mentioned (A) sputtering form 15 201023357 into a semiconductor film. The film was amorphous. Then, it was heat-treated in air at 300 ° C for 1 hour in a hot air heating furnace. When X-ray diffraction (XRD) of the obtained semiconductor film was measured, an indium oxide ferrite structure was observed. The peak of the semiconductor film was confirmed to be crystalline. In addition, the heat treatment conditions of the semiconductor film were determined to be 45 Torr in air, and the same XRD measurement was performed for 5 hours. The XRD was heat treated at 300 ° C. At the peak intensity, the peak intensity obtained at 300 ° C is about 98 〇 / 〇 of the peak intensity obtained at 450 ° C. The output curve of the thin film transistor produced in Example 1 is shown in Fig. 4, ® transmission curve This is shown in Fig. 5. Fig. 4 is a graph showing the relationship between the gate voltage (Vds) and the same-pole current (Ids) when the gate voltage (Vgs) is changed from -5V to 25V. Figure 5 is a graph showing the relationship between the gate voltage (Vgs) and the drain current (Ids). The curve formed by the white dots is the curve of the gate current multiplied by 1/2 with respect to the gate voltage. The curve formed by the black dots is a curve showing the drain current with respect to the gate voltage. In FIGS. 4 and 5, "χΕ_γ" means χχΐ〇_γ. For example, i.OE_〇5 is 1.0χ10_5.实施 Example 2 In addition to the use of a target formed of high-purity indium oxide (a total of four or more metal elements, · total of Sn, Ti, and Zr: 0.4 ppm (Sn : 〇) PPm), a metal having a positive divalent or lower Element: Total of Na, K, Mg, and Zn: 3 ppm), manufactured by Shonan Institute of Electronic Materials, and treated in the same manner as in Example 1 except for the reduction of the ore. The thin film transistor has a field effect mobility of 52 Cni2/V . sec, On/Off 16 201023357 ratio of 10, Vth of 5.5 V, and S value of 1.5 V/dec., which is a thin film transistor exhibiting a normally-off characteristic. In addition, the output characteristics show a significant loss. Further, the semiconductor film is crystalline in nature. Comparative example 1
除使用由純度3N的氧化銦形成之靶材（正4價以上的金 屬元素：Sn、Ti、Zr的總合計：l2〇Ppm(sn : 3〇ppm)，正2 價以下的金屬元素：Na、K、Mg、Zn的總合計：6〇ppm)作 為濺鍍靶以外，與實施例1同樣地處理，製作薄膜電晶體。 該薄膜電晶體的場效移動率為46cm2/V . sec，Qn/Off 比為2_5xl〇5 ’ 乂仇為_1.2¥，s值為2.4V/dec.，是顯示常開特 性之薄膜電晶體。另外，輸出特性顯示明顯的夾止。 另外’半導體膜為結晶質性質。 像這樣處理，透過如實施例那樣地將純度高的氧化銦 燒結體靶材經成膜獲得之結晶質氧化銦膜用於薄膜電晶 體’可獲得場效移動率、Οη/Off比及S值良好的電晶體特性。 實施例3 利用光阻餘刻法(photoresist method)製作示於第6圖之 蝕刻阻擋型薄膜電晶體。 在附著熱氧化膜(Si〇2膜）的導電性矽基板1〇上，與實施 例1同樣地處理，使用由高純度氧化銦形成之靶材（正4價以 上的金屬元素：Sn、Ti、Zr的總合計：0.〇9ppm(Sn: 0.02ppm)， 正2價以下的金屬元素：他、尺、]^、211的總合計：〇抑？111)， 用濺鍍法成膜5〇nm的半導體膜40。 然後，利用高頻濺鍍法，在氧分壓15%、氬85%的條件 17 201023357 下成膜3〇〇nm的Si〇2 ’以作為形成触刻阻擋層的層。在該帶 有si〇2的半導體膜上塗布抗蚀劑，以阶預烘15分鐘。然 後，通過遮罩對抗敍膜照射―光（光強度：3〇〇mj/cm2)，然 後用3Wt%的四曱基氫氧化鍵(TMAH)進行顯影。用純水洗 淨後，在13GC下后供抗㈣β分鐘，藉制CF4的乾法麵 刻來触刻SiQ2以形成所需形狀的⑽阻擒層％。 然後在半導體膜40、閘極絕緣膜(熱氧化膜)3〇及蚀刻阻 擋層70上成膜鉬金屬膜3〇〇nm。 在翻金屬膜上塗布抗14劑，在8(rc下進行15分鐘的預 e 烘。然後，通過遮罩對抗蝕膜照射uv光（光強度： 300mJ/cm )，然後’用3wt%四甲基氫氧化錢進行顯 影。用純水洗淨後，在13(rc下后烘抗蚀膜15分鐘後，形成 所需形狀之源·波電極形狀的抗蚀圖案。 對該帶有抗姓圖案的基板用鱗酸醋酸石肖酸的混合 酸處理，藉此金屬膜，形成源電極50和汲電極52。 同時也同時钱刻半導體膜4〇與閘極絕緣膜相鄰接之部 ❹ 分。然後剝離抗蚀劑，用純水洗淨然後吹風使其乾燥製 作成薄膜電晶體（通道部6〇的源汲電極間間隙（L)為 200μηι ’ 寬(W)為 lOOOpm)。 然後，在熱風加熱爐内於空氣中，以3〇〇。〇熱處理該薄 膜電晶體1小時。 該薄膜電晶體的場效移動率g62cm2/v . sec，on_off 比為3x10，Vth為6.8V，S值為0 9V/dec·，是顯示常關特性 之薄膜電晶體。另外’輸出特性顯示明顯的失止。對問電 18 201023357 極施加2〇V電壓100分鐘後的漂移電壓(Vth)為0.25V。 半導體臈為結晶質。 . 比較例2In addition to using a target formed of indium oxide having a purity of 3N (a total of four or more metal elements: total of Sn, Ti, and Zr: l2〇Ppm(sn: 3〇ppm), a metal element of a positive or lower valence: Na The total of K, Mg, and Zn (6 〇 ppm) was treated in the same manner as in Example 1 except for the sputtering target to prepare a thin film transistor. The field effect mobility of the thin film transistor is 46 cm 2 /V . sec, Qn / Off ratio is 2_5xl 〇 5 ' 乂 为 _ 1.2 ¥, s value is 2.4V / dec., is a thin film transistor showing normally open characteristics . In addition, the output characteristics show significant pinch. Further, the semiconductor film is crystalline in nature. By processing in this manner, a crystalline indium oxide film obtained by film-forming a high-purity indium oxide sintered body target as a film can be used for a thin film transistor to obtain field effect mobility, Οη/Off ratio, and S value. Good transistor properties. Example 3 An etch-stop type thin film transistor shown in Fig. 6 was produced by a photoresist method. On the conductive tantalum substrate 1 to which the thermal oxide film (Si 2 film) was attached, a target formed of high-purity indium oxide was used in the same manner as in Example 1 (positive tetravalent or higher metal element: Sn, Ti) Total of Zr: 0. 〇 9ppm (Sn: 0.02ppm), metal element below positive valence: total of he, ruler, ]^, 211: 〇? 111), film formation by sputtering 5 The semiconductor film 40 of 〇 nm. Then, 3 〇〇 nm of Si 〇 2 ′ was formed by a high-frequency sputtering method under the conditions of an oxygen partial pressure of 15% and an argon 85% condition 17 201023357 as a layer for forming a etch barrier layer. A resist was applied on the semiconductor film with si 〇 2, and pre-baked for 15 minutes. Then, the film was irradiated with a mask - light (light intensity: 3 〇〇 mj/cm 2 ), and then developed with 3 Wt% of a tetradecyl hydroxide bond (TMAH). After washing with pure water, it was subjected to anti-(iv) β minutes at 13 GC, and the dry surface of CF4 was used to touch SiQ2 to form a desired layer of (10) barrier layer. Then, a molybdenum metal film 3 〇〇 nm is formed on the semiconductor film 40, the gate insulating film (thermal oxide film) 3 〇, and the etching stopper layer 70. The anti-14 agent was coated on the metal film, and pre-e baking was performed for 15 minutes at 8 (rc). Then, the resist film was irradiated with uv light (light intensity: 300 mJ/cm) through a mask, and then '3 wt% of the four The base hydrogen hydroxide was developed, and after washing with pure water, the resist pattern of the source and wave electrode of a desired shape was formed after the resist film was baked for 13 minutes at 13 (rc). The substrate is treated with a mixed acid of phthalic acid acetate, and the metal film is used to form the source electrode 50 and the ruthenium electrode 52. At the same time, the semiconductor film 4 〇 is adjacent to the gate insulating film. Then, the resist is peeled off, washed with pure water, and then blown and dried to form a thin film transistor (the gap between the source and the electrodes (L) of the channel portion 6 is 200 μm' width (W) is 1000 ppm). Then, in the hot air The film transistor was heat-treated in the air in a heating chamber for 3 hours. The field effect mobility of the film transistor was g62 cm2/v. sec, the on_off ratio was 3x10, the Vth was 6.8V, and the S value was 0. 9V/dec· is a thin film transistor that shows the characteristics of the normally off. In addition, the 'output characteristics show obvious aberrations. Q electrode for applying electrical 18201023357 2〇V voltage shift voltage (Vth) 100 minutes after was 0.25V. The semiconductor is crystalline Ge. Comparative Example 2
除使用由純度3N的氧化銦形成之祀材（正4價以上的金 屬兀素：Sn、Ti、Zr的總合計：12〇ppm(sn : 30ppm)，正2 價以下的金屬元素：Na、K、Mg、Zn的總合計：6〇ppm)B 成之靶材作為濺鍍靶以外，與實施例3同樣地處理，製作薄 膜電晶體。In addition to using a tantalum material formed of indium oxide having a purity of 3N (a total of four or more metal halogens: total of Sn, Ti, and Zr: 12 〇ppm (sn: 30 ppm), a metal element having a positive valence of 2 or less: Na, A total of K, Mg, and Zn: 6 〇 ppm) B was formed into a thin film transistor in the same manner as in Example 3 except that the target was used as a sputtering target.
該薄膜電晶體的場效移動率為48cm2/V . sec，On/Off 比為107 ’ Vth為-2.8V，S值為1.9V/dec.，是顯示常關特性之 薄膜電晶體。另外，輸出特性顯示明顯的夾止。對閘電極 施加20V電壓1〇〇分鐘後的漂移電壓(Vth)為〇 4v。 半導體膜為結晶質。 像這樣地利用光微影及剝離製程，在蝕刻阻擋型薄膜 電晶體中’當使用由純度高的氧化銦燒結體靶材而獲得之 結晶質氧化銦薄膜時，同樣也是S值低，並顯示良好的電晶 體特性。 實施例4 除將通道部60的源·汲電極間間隙(L)定為20μπι，寬(W) 定為ΙΟΟμηι以外，與實施例3同樣地處理，製作薄膜電晶體。 該薄膜電晶體的場效移動率為32cm2/V ♦ sec，On/Off 比為109，Vth為3.5V，S值為0.45V/dec.，是顯示常關特性 之薄膜電晶體。另外’輸出特性顯示明顯的夾止。對閘電 極施加20V電壓1〇〇分鐘後的漂移電壓(Vth)為0.18V。 19 201023357 半導體膜為結晶質。 實施例5 除將通道部60的源·汲電極間間隙(L)定為1 〇μηι，寬(w) 定為20μιη以外，與實施例4同樣地處理，製作薄膜電晶體。The thin film transistor has a field effect mobility of 48 cm 2 /V. sec, an On/Off ratio of 107 ′ Vth of -2.8 V, and an S value of 1.9 V/dec., which is a thin film transistor exhibiting a normally-off characteristic. In addition, the output characteristics show significant pinch. The drift voltage (Vth) after applying a voltage of 20 V to the gate electrode for 1 minute was 〇 4v. The semiconductor film is crystalline. In the etching-blocking thin film transistor, when a crystalline indium oxide thin film obtained from a high-purity indium oxide sintered compact target is used, the S value is also low and is displayed by using the photolithography and the lift-off process. Good transistor properties. (Example 4) A thin film transistor was produced in the same manner as in Example 3 except that the gap between the source and the electrode of the channel portion 60 (L) was 20 μm and the width (W) was changed to ΙΟΟμηι. The thin film transistor has a field effect mobility of 32 cm 2 /V ♦ sec, an On/Off ratio of 109, a Vth of 3.5 V, and an S value of 0.45 V/dec., which is a thin film transistor exhibiting a normally-off characteristic. In addition, the output characteristics show a significant pinch. The drift voltage (Vth) after applying a voltage of 20 V to the gate electrode for 1 minute was 0.18V. 19 201023357 The semiconductor film is crystalline. Example 5 A thin film transistor was produced in the same manner as in Example 4 except that the gap between the source and the inter-electrode (L) of the channel portion 60 was set to 1 〇μηι and the width (w) was set to 20 μm.
該薄膜電晶體的場效移動率為36cm2/V . sec，On/Off 比為4.6><108，\^11為3.2\7,8值為0.40\7(^.，是顯示常關特 性之薄膜電晶體。另外，輸出特性顯示明顯的夾止。對閘 電極施加20V電壓100分鐘後的漂移電壓(Vth)為0.16V。 半導體膜為結晶質。 由實施例5製作之薄膜電晶體的傳輸曲線示於第7圖。 比較例3 除使用由純度3N的氧化銦形成之靶材（正4價以上的金 屬元素：Sn、Ti、Zr的總合計·· l2〇ppm(sn ·· 30ppm)，正2 價以下的金屬元素：Na、K、Mg、Zn的總合計：60ppm)形 成之靶材作為濺鍍靶以外，與實施例4同樣地處理，製作薄 膜電晶體。The field effect mobility of the thin film transistor is 36 cm 2 /V . sec, the On/Off ratio is 4.6 >< 108, \^11 is 3.2\7, and the 8 value is 0.40\7 (^. In addition, the output characteristics showed a significant pinch. The drift voltage (Vth) after applying a voltage of 20 V to the gate electrode for 100 minutes was 0.16 V. The semiconductor film was crystalline. The thin film transistor fabricated in Example 5. The transmission curve is shown in Fig. 7. Comparative Example 3 In addition to the use of a target formed of indium oxide having a purity of 3N (a total of four or more metal elements: total sum of Sn, Ti, Zr · l2 〇 ppm (sn · · 30 ppm), a metal element having a positive valence of 2 or less: total of Na, K, Mg, and Zn: 60 ppm) The formed target was treated in the same manner as in Example 4 except that the target was formed as a sputtering target to prepare a thin film transistor.
該薄膜電晶體的場效移動率為27cm2/V · sec，〇n/〇ff 比為4X108，Vth為-2.2V，S值為l.OV/dec·，是顯示常開特性 之薄膜電晶體。科，輸出特性顯示明顯的夾止。對閘電 極施加20V電壓1〇〇分鐘後的漂移電壓(v叫為〇 38v。半導 體膜為結晶質。 _實施例4的薄膜電晶體，係具有與專利文獻3中記載的 疋件相同程度之通道長(L)和寬(W)的元件大小。此種情形 本發月依然可以獲得具有良好電晶體特性之電晶體。 20 201023357 實施例5之薄膜電晶體的源.汲電極間間隙（L)為 ΙΟμπι，寬(W)為20μηι。即使在縮小通道寬度的情形中，利 用本發明依然可以獲得具有良好電晶體特性之電晶體。 產業之可利用性 本發明之薄膜電晶體’可適宜的用於顯示用平板、射 頻識別標籤(Radio Frequency Identification tag)、Χ射線平板 探測器.指紋傳感器.光傳感器等之傳感器等。 ^ 本發明之薄膜電晶體的製造方法，尤其適用於通道蝕 刻型薄膜電晶體的製造方法。 上述内容中雖詳細說明了幾個本發明之實施態樣及/ 或實施例，惟熟悉該項技術者，在不實質地脫離本發明之 新穎教示及效果下，容易在這些例示之實施態樣及/或實施 例中加入多種變更。因此，該等多種變更包含於本發明的 範圍内。 本說明書記載之文獻的内容全部援引於此。The thin film transistor has a field effect mobility of 27 cm 2 /V · sec, a 〇n/〇ff ratio of 4×108, a Vth of -2.2 V, and an S value of 1.0 V/dec·, which is a thin film transistor exhibiting normally-on characteristics. . Section, the output characteristics show a significant pinch. The drift voltage (v is 〇38v) after applying a voltage of 20 V to the gate electrode for 1 minute. The semiconductor film is crystalline. The thin film transistor of Example 4 has the same degree as the element described in Patent Document 3. The element size of the channel length (L) and width (W). In this case, a transistor having good transistor characteristics can still be obtained in this month. 20 201023357 The source of the thin film transistor of Example 5, the inter-electrode gap (L) It is ΙΟμπι, and the width (W) is 20 μm. Even in the case of narrowing the channel width, a transistor having good crystal characteristics can be obtained by the present invention. Industrial Applicability The thin film transistor of the present invention can be suitably used. A sensor for displaying a flat panel, a radio frequency identification tag, a xenon radiation flat panel detector, a fingerprint sensor, a photo sensor, etc. ^ A method for manufacturing a thin film transistor of the present invention, particularly suitable for a channel etching type film Method for manufacturing a transistor. Although several embodiments of the present invention and/or embodiments have been described in detail above, those skilled in the art are not A variety of modifications are possible in the embodiments and/or embodiments of the present invention, and various modifications are included in the scope of the present invention. The contents of the documents described in the present specification are included in the present invention. All cited here.
❹ 【圖式簡單說明：J 第1圖顯示本發明之通道蝕刻型薄膜電晶體的實施態 樣之概略斷面圖。 第2圖顯不本發明之姓刻ρ且推型薄膜電晶體的實施態 樣之概略斷面圖。 第3圖由實施例1製作之通道蚀刻型薄膜電晶體的概略 斷面圖。 第4圖顯示由實施例1製作之薄膜電晶體的輸出曲線圖。 第5關示由實施例1製作<薄_晶咖傳輸曲線圖。 21 201023357 第6圖由實施例3製作之蝕刻阻擋型薄膜電晶體的概略 斷面圖。 第7圖顯示由實施例5製作之薄膜電晶體的傳輸曲線圖。 【主要元件符號說明】 1、2···薄膜電晶體 10…基板 20…閘電極 30…閘極絕緣膜 40…半導體膜 50…源電極 52…汲電極 60…通道部 70…姓刻阻撞層 ❿BRIEF DESCRIPTION OF THE DRAWINGS Fig. 1 is a schematic cross-sectional view showing an embodiment of a channel-etched thin film transistor of the present invention. Fig. 2 is a schematic cross-sectional view showing an embodiment of the present invention and a push type thin film transistor. Fig. 3 is a schematic cross-sectional view showing a channel-etched thin film transistor produced in the first embodiment. Fig. 4 is a graph showing the output of the thin film transistor produced in Example 1. In the fifth aspect, a <thin_crystal coffee transfer graph is produced by the first embodiment. 21 201023357 Fig. 6 is a schematic cross-sectional view showing an etch-stop type film transistor produced in Example 3. Fig. 7 is a graph showing the transmission of a thin film transistor produced in Example 5. [Description of main component symbols] 1, 2, ..., thin film transistor 10, substrate 20, gate electrode 30, gate insulating film 40, semiconductor film 50, source electrode 52, germanium electrode 60, channel portion 70, last name blocking Layer
22twenty two