WO2010024279A1 - Procédé et dispositif de fabrication d'un transistor à effet de champ - Google Patents

Procédé et dispositif de fabrication d'un transistor à effet de champ Download PDF

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Publication number
WO2010024279A1
WO2010024279A1 PCT/JP2009/064842 JP2009064842W WO2010024279A1 WO 2010024279 A1 WO2010024279 A1 WO 2010024279A1 JP 2009064842 W JP2009064842 W JP 2009064842W WO 2010024279 A1 WO2010024279 A1 WO 2010024279A1
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Prior art keywords
film
forming
insulating film
active layer
effect transistor
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PCT/JP2009/064842
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English (en)
Japanese (ja)
Inventor
敬臣 倉田
淳也 清田
真 新井
泰彦 赤松
伸 浅利
征典 橋本
重光 佐藤
正志 菊池
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株式会社アルバック
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Priority to JP2010526734A priority Critical patent/JP5417332B2/ja
Priority to CN2009801379296A priority patent/CN102165570A/zh
Priority to KR1020137005674A priority patent/KR101273143B1/ko
Publication of WO2010024279A1 publication Critical patent/WO2010024279A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02551—Group 12/16 materials
    • H01L21/02554—Oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02518—Deposited layers
    • H01L21/02521—Materials
    • H01L21/02565—Oxide semiconducting materials not being Group 12/16 materials, e.g. ternary compounds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02365—Forming inorganic semiconducting materials on a substrate
    • H01L21/02612—Formation types
    • H01L21/02617—Deposition types
    • H01L21/02631—Physical deposition at reduced pressure, e.g. MBE, sputtering, evaporation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66742—Thin film unipolar transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device

Definitions

  • the present invention relates to a method and apparatus for manufacturing a field effect transistor having an active layer formed of an InGaZnO-based semiconductor oxide.
  • An active matrix liquid crystal display has a field effect thin film transistor (TFT) as a switching element for each pixel.
  • TFT thin film transistor
  • a polysilicon thin film transistor in which an active layer is made of polysilicon and an amorphous silicon thin film transistor in which an active layer is made of amorphous silicon are known.
  • An amorphous silicon thin film transistor has an advantage that it can be uniformly formed on a substrate having a relatively large area because an active layer can be easily produced as compared with a polysilicon thin film transistor.
  • Patent Document 2 discloses the manufacture of a field effect transistor in which an In—Ga—Zn—O-based active layer is formed by sputtering a target material made of a polycrystalline sintered body having an InGaO 3 (ZnO) 4 composition. A method is described.
  • An amorphous silicon thin film transistor had an active layer made of amorphous silicon formed by a CVD method.
  • an In—Ga—Zn—O-based active layer cannot be formed by a CVD method, it must be formed by a sputtering method.
  • An In—Ga—Zn—O-based thin film is soluble in acids and alkalis. Therefore, in the patterning process using the etchant (etching solution), it is necessary to form a protective layer for protecting the In—Ga—Zn—O thin film from the etchant.
  • a resist mask made of a photosensitive resin has been widely used for pattern etching of a thin film.
  • JP 2004-103957 A (paragraph [0010])
  • JP 2006-165527 A (paragraphs [0103] to [0119])
  • the resist mask is usually formed in an air atmosphere.
  • the protective layer is formed of a resist mask
  • the active layer is exposed to the air atmosphere after the active layer is formed.
  • membrane quality of an active layer may be impaired by the water
  • a great amount of time is required for forming the protective layer, which may cause a reduction in productivity.
  • an object of the present invention is to provide a method for manufacturing a field effect transistor and an apparatus for manufacturing the same, which can protect an active layer from an etchant without being exposed to an air atmosphere.
  • a method for manufacturing a field effect transistor according to one embodiment of the present invention includes a step of forming an active layer having an In—Ga—Zn—O-based composition on a base material by a sputtering method.
  • a stopper layer for protecting the active layer from an etchant for the active layer is formed on the active layer by a sputtering method.
  • the active layer is etched using the stopper layer as a mask.
  • a field effect transistor manufacturing apparatus is a field effect transistor for forming an active layer and a stopper layer for protecting the active layer from an etchant for the active layer on a base material, respectively.
  • the present invention relates to a transistor manufacturing apparatus.
  • the manufacturing apparatus includes a first film formation chamber and a second film formation chamber.
  • the first deposition chamber includes a first sputtering cathode for depositing the active layer having an In—Ga—Zn—O-based composition on the substrate.
  • the second film forming chamber includes a second sputtering cathode for forming the stopper layer made of a silicon oxide film or a silicon nitride film on the base material.
  • a method for manufacturing a field effect transistor according to an embodiment of the present invention includes a step of forming an active layer having an In—Ga—Zn—O-based composition on a base material by a sputtering method.
  • a stopper layer for protecting the active layer from an etchant for the active layer is formed on the active layer by a sputtering method.
  • the active layer is etched using the stopper layer as a mask.
  • the stopper layer is formed by sputtering. This makes it possible to form a stopper layer after the active layer is formed without exposing the active layer to the atmosphere, so that the film quality is deteriorated due to the adhesion of moisture and impurities in the atmosphere to the surface of the active layer. Can be prevented. Further, since the stopper layer can be continuously formed after the active layer is formed, the process time required for forming the stopper layer can be shortened, and the productivity can be improved.
  • the base material is typically a glass substrate.
  • the size of the substrate is not particularly limited.
  • the active layer may be formed by a reactive sputtering method with an oxidizing gas (for example, O 2 , O 3 , H 2 O, etc.).
  • an oxidizing gas for example, O 2 , O 3 , H 2 O, etc.
  • a sputtering target for forming an In—Ga—Zn—O thin film a single target of In—Ga—Zn—O may be used, or an In 2 O 3 target, a Ga 2 O 3 target, and a ZnO target.
  • a plurality of targets such as may be used.
  • the oxygen concentration in the film can be easily controlled by controlling the partial pressure (flow rate) of the introduced oxygen.
  • the stopper layer may be continuously formed in the active layer deposition chamber after the active layer is formed. As a result, the stopper layer can be formed without carrying out the substrate from the active layer forming chamber, so that the productivity can be further improved.
  • a sputtering target for forming a stopper layer is disposed in the film forming chamber in addition to the sputtering target for forming an active layer. And each sputtering target is properly used for every film-forming process.
  • the step of forming the stopper layer includes a step of forming a first insulating film made of a silicon oxide film or a silicon nitride film on the active layer by a sputtering method, and a metal on the first insulating film. And a step of forming a second insulating film made of an oxide film by a sputtering method.
  • the step of forming the stopper layer includes a step of forming a first insulating film made of a metal oxide film on the active layer by a sputtering method, and a silicon oxide film on the first insulating film.
  • a step of forming a second insulating film made of a silicon nitride film by a sputtering method may be included.
  • the stopper layer has a function of ensuring a predetermined electrical insulation
  • the second insulating film has a function of ensuring a predetermined barrier property.
  • the first insulating film and the second insulating film may be continuously formed in the same chamber.
  • the stopper layer can be collectively formed in one chamber, and productivity can be improved.
  • a sputtering target for forming the first insulating film and a sputtering target for forming the second insulating film are arranged in the chamber. And each sputtering target is properly used for every film-forming process.
  • the stopper layer may be continuously formed in the active layer deposition chamber after the active layer is formed. As a result, the stopper layer can be formed without carrying out the substrate from the active layer forming chamber, so that the productivity can be further improved.
  • the base material may include a gate electrode, and a gate insulating film covering the gate electrode may be further formed before forming the active layer.
  • a bottom-gate field effect transistor can be manufactured.
  • the gate electrode may be an electrode film formed on a base material, or the base material itself may be composed of a gate electrode.
  • the gate insulating film may be formed by a sputtering method. Thereby, the gate insulating film, the active layer, and the stopper layer can be continuously formed in a vacuum atmosphere.
  • the step of forming the gate insulating film includes a step of forming a first gate insulating film made of a metal oxide film on the gate electrode by a sputtering method, and a silicon oxide film on the first gate insulating film. Forming a second gate insulating film made of a film or a silicon nitride film by a sputtering method.
  • the step of forming the gate insulating film includes a step of forming a first gate insulating film made of a silicon oxide film or a silicon nitride film on the gate electrode, and a step of forming on the first gate insulating film. And a step of forming a second gate insulating film made of a metal oxide film.
  • the gate insulating film By configuring the gate insulating film as a multilayer film in this way, various functions required for the gate insulating film can be ensured.
  • the first insulating film has a function of ensuring a predetermined barrier property
  • the second insulating film has a function of ensuring a predetermined electrical insulating property.
  • a protective film covering the active layer can be formed, and a source electrode and a drain electrode in contact with the active layer can be formed.
  • the protective film can be formed by a sputtering method.
  • An apparatus for manufacturing a field effect transistor includes an electric field for forming an active layer and a stopper layer for protecting the active layer from an etchant for the active layer on a base material, respectively.
  • the present invention relates to an effect transistor manufacturing apparatus.
  • the manufacturing apparatus includes a first film formation chamber and a second film formation chamber.
  • the first deposition chamber includes a first sputtering cathode for depositing the active layer having an In—Ga—Zn—O-based composition on the substrate.
  • the second film forming chamber includes a second sputtering cathode for forming the stopper layer made of a silicon oxide film or a silicon nitride film on the base material.
  • an active layer having an In—Ga—Zn—O-based composition is formed by a sputtering method in a first film formation chamber, and a silicon oxide film or a film is formed in a second film formation chamber.
  • a stopper layer made of a silicon nitride film is formed by sputtering. This makes it possible to form a stopper layer after the active layer is formed without exposing the active layer to the atmosphere, so that the film quality is deteriorated due to the adhesion of moisture and impurities in the atmosphere to the surface of the active layer. Can be prevented. Further, since the stopper layer can be continuously formed after the active layer is formed, the process time required for forming the stopper layer can be shortened, and the productivity can be improved.
  • the first film formation chamber and the second film formation chamber may be configured as a common film formation chamber. Thereby, the active layer and the stopper layer can be continuously formed in the same chamber.
  • the second sputtering cathode may have a first target material made of silicon oxide or silicon nitride and a second target material made of metal oxide. Accordingly, it is possible to continuously form a stopper layer having a multilayer structure of a first insulating film made of a silicon oxide film or a silicon nitride film and a second insulating film made of a metal oxide film. A stopper layer having can be obtained.
  • the field effect transistor manufacturing apparatus may further include a third film formation chamber for forming a gate insulating film on the base material.
  • a third film formation chamber for forming a gate insulating film on the base material.
  • the field effect transistor manufacturing apparatus may further include a third film formation chamber including a third sputtering cathode for forming a gate insulating film on the base material.
  • a third film formation chamber including a third sputtering cathode for forming a gate insulating film on the base material.
  • the third sputtering cathode may include a third target material made of a metal oxide and a fourth target material made of silicon oxide or silicon nitride.
  • a stopper layer having a multilayer structure of a first gate insulating film made of a silicon oxide film or a silicon nitride film and a second gate insulating film made of a metal oxide film.
  • a gate insulating film having barrier properties can be obtained.
  • the manufacturing apparatus may further include a transfer chamber capable of being evacuated and having a transfer robot for transferring the substrate to and from the first film formation chamber and the second film formation chamber.
  • the first film formation chamber and the second film formation chamber are installed around the transfer chamber. That is, the manufacturing apparatus can be configured as a cluster-type film forming apparatus.
  • the manufacturing apparatus may further include a transport mechanism that transports the base material from the first film formation chamber to the second film formation chamber.
  • the first film formation chamber and the second film formation chamber are installed adjacent to each other. That is, the manufacturing apparatus can be configured as an in-line film forming apparatus.
  • First Embodiment> 1 to 5 are cross-sectional views of the main part of each step for explaining the method of manufacturing a field effect transistor according to the first embodiment of the present invention.
  • a method for manufacturing a field-effect transistor having a so-called bottom-gate transistor structure is described.
  • a gate electrode film 11F is formed on one surface of the substrate 10.
  • the base material 10 is typically a glass substrate.
  • the gate electrode film 11F is typically composed of a metal single layer film or a metal multilayer film such as molybdenum, chromium, or aluminum, and is formed by, for example, a sputtering method.
  • the thickness of the gate electrode film 11F is not particularly limited and is, for example, 300 nm.
  • a resist mask 12 for patterning the gate electrode film 11F into a predetermined shape is formed.
  • This step includes a step of forming a photoresist film 12F (FIG. 1B), an exposure step (FIG. 1C), and a development step (FIG. 1D).
  • the photoresist film 12F is formed by applying a liquid photosensitive material on the gate electrode film 11F and then drying it.
  • a dry film resist may be used as the photoresist film 12F.
  • the formed photoresist film 12F is exposed through the mask 13 and then developed. Thereby, a resist mask 12 is formed on the gate electrode film 11F.
  • the gate electrode film 11F is etched using the resist mask 12 as a mask. Thereby, the gate electrode 11 is formed on the surface of the substrate 10.
  • the etching method of the gate electrode film 11F is not particularly limited, and may be a wet etching method or a dry etching method. After the etching, the resist mask 12 is removed.
  • the method for removing the resist mask 12 is an ashing process using oxygen gas plasma, but is not limited to this, and may be dissolved and removed using a chemical solution.
  • a gate insulating film 14 is formed on the surface of the base material 10 so as to cover the gate electrode 11.
  • the gate insulating film 14 is typically composed of an oxide film or a nitride film such as a silicon oxide film (SiO 2 ) or a silicon nitride film (SiNx), and is formed by, for example, a CVD method or a sputtering method.
  • the thickness of the gate electrode film 11F is not particularly limited, and is, for example, 200 nm to 500 nm.
  • IGZO film 15F having an In—Ga—Zn—O-based composition and a stopper layer forming film 16F are formed. Are formed in order.
  • the IGZO film 15F and the stopper layer forming film 16F are formed by a sputtering method.
  • the IGZO film 15F and the stopper layer forming film 16F can be continuously formed.
  • the sputtering target for forming the IGZO film 15F and the sputtering target for forming the stopper layer forming film 16F may be disposed in the same sputtering chamber. By switching the target to be used, the IGZO film 15F and the stopper layer forming film 16F can be formed independently.
  • the IGZO film 15F is formed with the base material 10 heated to a predetermined temperature.
  • the active layer 15 is formed by a reactive sputtering method in which a reaction product with oxygen is deposited on the substrate 10 by sputtering a target in an oxygen gas atmosphere.
  • the discharge type may be any of DC discharge, AC discharge, and RF discharge.
  • each of the IGZO film 15F and the stopper layer forming film 16F is not particularly limited.
  • the thickness of the IGZO film 15F is 50 nm to 200 nm, and the thickness of the stopper layer forming film 16F is 30 nm to 300 nm.
  • the IGZO film 15F constitutes an active layer (carrier layer) 15 of the transistor.
  • the stopper layer forming film 16F is an etching protection that protects the channel region of the IGZO film from the etchant in the patterning process of the metal film constituting the source electrode and the drain electrode, which will be described later, and the process of etching away the unnecessary area of the IGZO film 15F. Acts as a layer.
  • the stopper layer forming film 16F is made of, for example, SiO 2 .
  • the stopper layer forming film 16F is passed through the resist mask 27. Etch. Thereby, the stopper layer 16 facing the gate electrode 11 is formed with the gate insulating film 14 and the IGZO film 15F interposed therebetween.
  • a metal film 17F is formed so as to cover the IGZO film 15F and the stopper layer 16 as shown in FIG.
  • the metal film 17F is typically composed of a metal single layer film or a metal multilayer film such as molybdenum, chromium, or aluminum, and is formed by, for example, a sputtering method.
  • the thickness of the metal film 17F is not particularly limited, and is, for example, 100 nm to 500 nm.
  • the metal film 17F is patterned.
  • the patterning process of the metal film 17F includes a resist mask 18 formation process (FIG. 3A) and a metal film 17F etching process (FIG. 3B).
  • the resist mask 18 has a mask pattern that opens the region immediately above the stopper layer 16 and the peripheral region of each transistor.
  • the metal film 17F is etched by wet etching. Thereby, the metal film 17F is separated into the source electrode 17S and the drain electrode 17D.
  • the source electrode 17S and the drain electrode 17D are also collectively referred to as the source / drain electrode 17.
  • the stopper layer 16 functions as an etching stopper layer for the metal film 17F. That is, the stopper layer 16 has a function of protecting the IGZO film 15F from an etchant (for example, phosphorous nitric acid) with respect to the metal film 17F.
  • the stopper layer 16 is formed so as to cover a region (hereinafter referred to as “channel region”) located between the source electrode 17S and the drain electrode 17D of the IGZO film 15F. Therefore, the channel region of the IGZO film 15F is not affected by the etching process of the metal film 17F.
  • the IGZO thin film 15F is etched using the resist mask 18 as a mask.
  • the etching method is not particularly limited, and may be a wet etching method or a dry etching method.
  • the IGZO film 15F is isolated in element units and an active layer 15 made of the IGZO film 15F is formed.
  • the stopper layer 16 functions as an etching protective film for the IGZO film 15F located in the channel region. That is, the stopper layer 16 has a function of protecting the channel region immediately below the stopper layer 16 from an etchant (for example, oxalic acid type) for the IGZO film 15F. Thereby, the channel region of the active layer 15 is not affected by the etching process of the IGZO film 15F.
  • an etchant for example, oxalic acid type
  • the resist mask 18 is removed from the source / drain electrode 17 by ashing or the like (FIG. 3D).
  • a protective film (passivation film) 19 is formed so as to cover the surface of the substrate 10 with the source / drain electrode 17, the stopper layer 16, the active layer 15, and the gate insulating film 14. Is formed.
  • the protective film 19 is for securing predetermined electrical and material characteristics by blocking the transistor element including the active layer 15 from the outside air.
  • the protective film 19 is typically composed of an oxide film or nitride film such as a silicon oxide film (SiO 2 ) or a silicon nitride film (SiNx), and is formed by, for example, a CVD method or a sputtering method.
  • the thickness of the protective film 19 is not particularly limited, and is, for example, 200 nm to 500 nm.
  • contact holes 19 a communicating with the source / drain electrodes 17 are formed in the protective film 19.
  • This step includes a step of forming a resist mask 20 on the protective film 19 (FIG. 4B) and a step of etching the protective film 19 exposed from the opening 20a of the resist mask 20 (FIG. 4C). And a step of removing the resist mask 20 (FIG. 4D).
  • the contact hole 19a is formed by a dry etching method, but may be a wet etching method. Although not shown, a contact hole that communicates with the source electrode 17S is also formed at an arbitrary position.
  • a transparent conductive film 21 that contacts the source / drain electrode 17 through the contact hole 19a is formed.
  • This step includes the step of forming the transparent conductive film 21F (FIG. 5A), the step of forming the resist mask 22 on the transparent conductive film 21F (FIG. 5B), and the resist mask 22. It has a step (FIG. 5C) of etching the transparent conductive film 21F that has not been removed and a step of removing the resist mask 20 (FIG. 5D).
  • the transparent conductive film 21F is typically composed of an ITO film or an IZO film, and is formed by, for example, a sputtering method or a CVD method.
  • the etching of the transparent conductive film 21F employs a wet etching method, but is not limited thereto, and a dry etching method may be employed.
  • the transistor element 100 having the transparent conductive film 21 shown in FIG. 5D is then subjected to an annealing process for the purpose of relaxing the structure of the active layer 15. As a result, desired transistor characteristics are imparted to the active layer 15.
  • transistor element 100 As described above, a field effect transistor (transistor element 100) is manufactured.
  • the IGZO film 15F constituting the active layer 15 and the stopper layer forming film 16F constituting the stopper layer 16 are formed by sputtering.
  • the stopper layer 16 can be formed without exposing the IGZO film 15F to the atmosphere. Deterioration of the film quality due to the adhesion of impurities can be prevented.
  • the stopper layer 16 can be continuously formed after the active layer 15 is formed, the process time required for forming the stopper layer 16 can be shortened and the productivity can be improved. Become.
  • 6 (A) and 6 (B) are schematic configuration diagrams of a vacuum processing apparatus for carrying out a part of the manufacturing process of the transistor element 100 (field effect transistor) described above.
  • a vacuum processing apparatus 201 illustrated in FIG. 6A is a single wafer type (cluster type) vacuum processing apparatus, and includes a transfer chamber 210 and a plurality of processing chambers 211 to 215 arranged around the transfer chamber 210.
  • the processing chamber includes a load chamber 211, a heating chamber 212, a CVD chamber 213, a sputtering chamber 214, and an unload chamber 215.
  • a transfer robot for transferring the base material 10 to each processing chamber is installed in the transfer chamber 210, and the transfer robot moves the base material 10 to each processing chamber in a direction indicated by an arrow in the drawing, for example. Transport to.
  • the transfer chamber 210 and each processing chamber are both maintained at a predetermined degree of vacuum so that the transfer of the base material 10 between the processing chambers 211 to 215 via the transfer chamber 210 is performed in a vacuum atmosphere. It has become.
  • the base material 10 on which the gate electrode 11 is formed is carried into the load chamber 211.
  • the transfer robot transfers the base material 10 from the load chamber 211 to the heating chamber 212.
  • the base material 10 is heat-treated, and moisture adhering to or adsorbed on the surface is removed.
  • the base material 10 is transferred to the CVD chamber 213, and the gate insulating film 14 is formed in the CVD chamber 213 (FIG. 2A).
  • the base material 10 is transferred to the sputtering chamber 214, and an IGZO film 15F and a stopper layer forming film 16F are formed in the sputtering chamber 214 (FIG. 2B).
  • the base material 10 is transferred to the unload chamber 215 and carried out of the vacuum processing apparatus 201.
  • the sputtering chamber 214 has a sputtering cathode Tc containing a target material for forming the IGZO film 15F and a sputtering cathode Ts containing a target material for forming the stopper layer forming film 16F.
  • the sputtering target for forming the IGZO film 15F may be a single target of In—Ga—Zn—O, or a plurality of targets such as an In 2 O 3 target, a Ga 2 O 3 target, and a ZnO target. May be.
  • a sputtering target for forming the stopper layer forming film 16F a silicon oxide or silicon nitride target is used, but it is not limited to this.
  • the sputtering chamber 214 includes a gas introduction system for introducing an oxidizing gas into the chamber, and the IGZO film 15F and the stopper layer forming film 16F can be formed by a reactive sputtering method with an oxidizing gas. By controlling the partial pressure (flow rate) of the introduced gas, the oxygen concentration in the film can be easily controlled. Examples of the gas introduced into the sputtering chamber 214 include, but are not limited to, O 2 , O 3 , H 2 O, and the like.
  • the vacuum processing apparatus 202 shown in FIG. 6B is also composed of a single wafer type (cluster type) vacuum processing apparatus.
  • the sputtering chamber is divided into a sputtering chamber 214A for forming the IGZO film 15F and a sputtering chamber 214B for forming the stopper layer forming film 16F.
  • the vacuum processing apparatuses 201 and 202 having the above-described configuration, it is possible to form the stopper layer forming film 16F without exposing the IGZO film 15F to the atmosphere after the IGZO film 15F is formed. Thereby, it is possible to prevent film quality deterioration due to adhesion of moisture and impurities in the atmosphere to the surface of the IGZO film 15F. Further, since the stopper layer forming film 16F can be continuously formed after the IGZO film 15F is formed, the process time required for forming the stopper layer forming film 16F can be shortened, and the productivity is improved. be able to.
  • the stopper layer forming film 16F can be continuously formed in the film forming chamber of the IGZO film 15F. Thereby, since it is possible to form the stopper layer forming film 16F without carrying out the substrate 10 from the film forming chamber of the IGZO film 15F, it is possible to further improve the productivity.
  • FIG. 7 shows a second embodiment of the present invention.
  • portions corresponding to those of the first embodiment described above are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the transistor element 101 of the present embodiment is manufactured through the same process as that of the first embodiment.
  • the illustrated transistor element 101 is different from the transistor element 100 of the first embodiment described above in that the stopper layer 16 has a multilayer structure of a first insulating film 16A and a second insulating film 16B. Yes.
  • a semiconductor layer containing zinc (Zn) has low resistance to acids and alkalis and is easily etched. Therefore, when the active layer 15 is formed, the stopper layer 16 for protecting from the etchant is formed in the channel region of the IGZO film 15F.
  • the stopper layer 16 functions not only as an etching mask for the IGZO film 15F but also as an insulating film for maintaining electrical insulation between the source electrode 17S and the drain electrode 17D on the upper layer side of the active layer 15.
  • the silicon oxide film constituting the stopper layer 16 may not be able to sufficiently prevent the contamination of impurities from the atmosphere.
  • impurities from the atmosphere are mixed into the active layer 15, the transistor characteristics are varied.
  • the stopper layer 16 includes two layers, a first insulating film 16A made of a silicon oxide film or a silicon nitride film and a second insulating film 16B made of a metal oxide film formed thereon.
  • the first insulating film 16A ensures the desired electrical insulation
  • the second insulating film 16B ensures the barrier property against the entry of impurities from the atmosphere.
  • the second insulating film 16B is made of an insulating metal oxide having a high barrier property against mixing of impurities from the atmosphere.
  • the second insulating film 16B can be composed of tantalum oxide (TaOx), alumina (Al 2 O 3 ), yttria (Y 2 O 3 ), or the like.
  • the first insulating film 16A may be composed of a metal oxide film
  • the second insulating film 16B may be composed of a silicon oxide film or a silicon nitride film. Even with such a configuration, it is possible to obtain the same effects as described above.
  • FIG. 8A, 8B, and 8C are schematic configuration diagrams of a vacuum processing apparatus for carrying out part of the manufacturing process of the transistor element 101 (field effect transistor) described above. Note that portions corresponding to those in FIG. 6 are denoted by the same reference numerals, and detailed description thereof is omitted.
  • a vacuum processing apparatus 203 shown in FIG. 8A is a single wafer type (cluster type) vacuum processing apparatus.
  • the sputtering chamber 214 includes a sputtering cathode Tc for forming the IGZO film 15F constituting the active layer 15, a sputtering cathode Ts1 for forming the first insulating film 16A of the stopper layer 16, and the stopper layer 16 Each has a sputtering cathode Ts2 for forming the second insulating film 16B.
  • the vacuum processing apparatuses 204 and 205 shown in FIGS. 8B and 8C are configured by single-wafer type (cluster type) vacuum processing apparatuses.
  • the vacuum processing apparatus 204 includes a first sputtering chamber 214A for forming the IGZO film 15F and a first layer for forming the stopper layer forming film 16F (the first insulating film 16A and the second insulating film 16B). 2 sputter chambers 214B.
  • the vacuum processing apparatus 205 includes a first sputtering chamber 214A for forming the IGZO film 15F, a second sputtering chamber 214B for forming the first insulating film 16A constituting the stopper layer 16, and a stopper.
  • the stopper layer forming film 16F can be formed without exposing the IGZO film 15F to the atmosphere. Thereby, it is possible to prevent film quality deterioration due to adhesion of moisture and impurities in the atmosphere to the surface of the IGZO film 15F. Further, since the stopper layer forming film 16F can be continuously formed after the IGZO film 15F is formed, the process time required for forming the stopper layer forming film 16F can be shortened, and the productivity is improved. be able to.
  • the stopper layer forming film 16F can be continuously formed in the film forming chamber of the IGZO film 15F. Therefore, since it is possible to form the stopper layer forming film 16F without carrying out the substrate 10 from the film forming chamber of the IGZO film 15F, it is possible to further improve the productivity.
  • FIG. 9 shows a third embodiment of the present invention.
  • portions corresponding to those in the first and second embodiments described above are denoted by the same reference numerals, and detailed description thereof is omitted.
  • the transistor element 102 of the present embodiment is manufactured through the same process as that of the first embodiment.
  • the transistor element 102 shown in the figure has the multilayer structure of the first gate insulating film 14A and the second gate insulating film 14B, and the transistor element 101 of the above-described second embodiment. Is different.
  • the gate insulating film is formed for the purpose of ensuring electrical insulation between the gate electrode and the active layer.
  • a gate insulating film made of a silicon oxide film has a low barrier property against diffusion of impurities from the substrate (base material)
  • a predetermined insulating function cannot be ensured by diffusion of impurities from the substrate into the gate insulating film.
  • the desired insulating function cannot be obtained in the gate insulating film, there is a possibility that the gate threshold voltage varies or an electrical leak with the active layer occurs.
  • the gate insulating film 14 includes a first gate insulating film 14A made of a metal oxide film and a second gate insulating film 14B made of a silicon oxide film or a silicon nitride film formed thereon. And a two-layer structure.
  • the first gate insulating film 14A ensures the desired barrier properties
  • the second gate insulating film 14B ensures the desired electrical insulation properties.
  • the first gate insulating film 14A an insulating metal oxide having a high barrier property against diffusion of impurities from the substrate is used.
  • the first gate insulating film 14A can be made of tantalum oxide (TaOx), alumina (Al 2 O 3 ), yttria (Y 2 O 3 ), or the like.
  • TaOx tantalum oxide
  • Al 2 O 3 alumina
  • Y 2 O 3 yttria
  • the first gate insulating film 14A may be composed of a silicon oxide film or a silicon nitride film
  • the second gate insulating film 14B may be composed of a metal oxide film. Even with such a configuration, the same effect as described above can be obtained.
  • FIGS. 10A, 10B, and 10C are schematic configuration diagrams of a vacuum processing apparatus for performing a part of the manufacturing process of the transistor element 102 (field effect transistor) described above. Note that portions corresponding to those in FIGS. 6 and 8 are denoted by the same reference numerals, and detailed description thereof is omitted.
  • a vacuum processing apparatus 206 shown in FIG. 10A is a single wafer type (cluster type) vacuum processing apparatus.
  • the vacuum processing apparatus 206 includes two sputtering chambers, a sputtering chamber 213A for forming the first gate insulating film 14A and a sputtering chamber 213B for forming the second gate insulating film 14B.
  • the sputtering chamber 213A has a sputtering cathode Tg1 for forming the first gate insulating film 14A
  • the sputtering chamber 213B has a sputtering cathode Tg2 for forming the second gate insulating film 14B.
  • a sputtering chamber for forming the IGZO film 15F constituting the active layer and the first and second insulating films 16A and 16B constituting the stopper layer 16 is constituted by a common sputtering chamber 214.
  • the vacuum processing apparatus 207 includes a first sputtering chamber 213 for forming the first and second gate insulating films 14A and 14B constituting the gate insulating film 14, and an IGZO film 15F constituting the active layer 15.
  • a second sputtering chamber 214A for forming a film and a third sputtering chamber 214B for forming first and second insulating films 16A and 16B constituting the stopper layer 16 are provided.
  • the vacuum processing apparatus 208 includes a first sputtering chamber 213A for forming the first gate insulating film 14A, a second sputtering chamber 213B for forming the second gate insulating film 14B, and an IGZO film.
  • a sputter chamber 214C is a sputtering chamber 213A for forming the first gate insulating film 14A, a second sputtering chamber 213B for forming the second gate insulating film 14B, and an IGZO film.
  • the stopper layer forming film 16F can be formed after the IGZO film 15F is formed without exposing the IGZO film 15F to the atmosphere, as in the first and second embodiments described above. It becomes. Thereby, it is possible to prevent film quality deterioration due to adhesion of moisture and impurities in the atmosphere to the surface of the IGZO film 15F. Further, since the stopper layer forming film 16F can be continuously formed after the IGZO film 15F is formed, the process time required for forming the stopper layer forming film 16F can be shortened, and the productivity is improved. be able to.
  • the gate insulating film 14 is formed by the sputtering method, so that a source gas introduction system and exhaust gas detoxification equipment required for the CVD process become unnecessary. . This makes it possible to reduce equipment costs and clean the process.
  • FIGS. 11A, 11B, and 11C are schematic configuration diagrams of a field-effect transistor manufacturing apparatus according to the fourth embodiment of the present invention.
  • the manufacturing apparatus is configured by an inline vacuum processing apparatus.
  • the vacuum processing apparatus may be a horizontal type that conveys the substrate in a horizontal position or a vertical type that conveys the substrate in a substantially upright position.
  • the vertical type is advantageous in that the installation area can be reduced.
  • the film formation on the substrate 10 may be a passing film formation in which the substrate is transported in the process chamber, or a stationary film formation (stop formation) in which the substrate is stationary in the process chamber. Any type of film) may be employed.
  • a vacuum treatment apparatus 301 illustrated in FIG. 11A includes a load chamber 311, a first heating chamber 312, a CVD chamber 313, a buffer chamber 314, a first sputtering chamber 315, a second heating chamber 316, and a second sputtering.
  • a chamber 317 and an unload chamber 318 are provided.
  • the vacuum processing apparatus 301 is provided with a transport mechanism for transporting the base material 10 to each processing chamber.
  • the transport mechanism moves the base material 10 from the load chamber 311 toward the unload chamber 318. Transport to each processing chamber.
  • a valve mechanism such as a gate valve is interposed between adjacent processing chambers, not shown, and a gate necessary for transporting the substrate is opened.
  • Each processing chamber is maintained at a predetermined degree of vacuum, and the transfer of the base material 10 between the processing chambers 311 to 318 is performed in a vacuum atmosphere.
  • the base material 10 (see FIG. 1F) on which the gate electrode 11 is formed is carried into the load chamber 311.
  • the base material 10 carried into the load chamber 311 is transported to the first heating chamber 312.
  • the base material 10 is subjected to a heat treatment, and moisture and the like attached or adsorbed on the surface is removed.
  • the base material 10 is transferred to the CVD chamber 313, and the gate insulating film 14 is formed in the CVD chamber 313 (FIG. 2A).
  • the substrate 10 is transferred to the first sputtering chamber 314 through the buffer chamber 314, and the IGZO film 15F is formed in the first sputtering chamber 314.
  • the base material 10 is transferred to the second heating chamber 316, and in the second heating chamber 316, heat treatment for imparting predetermined transistor characteristics to the IGZO film 15F is performed.
  • the substrate 10 is transferred to the second sputtering chamber 317, and a stopper layer forming film 16F is formed in the second sputtering chamber 317 (FIG. 2B).
  • the base material 10 is transferred to the unload chamber 318 and carried out of the vacuum processing apparatus 301.
  • the buffer chamber 314 is installed for the purpose of securing the atmosphere insulation between the CVD chamber 313 and the first sputtering chamber 315. That is, in general, the CVD chamber is processed under a lower vacuum than the sputtering chamber, and the atmospheric gas is different. For this reason, when the CVD chamber and the sputtering chamber are disposed adjacent to each other in an in-line vacuum processing apparatus, the atmosphere in the CVD chamber flows out into the sputtering chamber, thereby contaminating the sputtering chamber. In order to prevent this, a buffer chamber maintained at a higher degree of vacuum than these processing chambers is interposed between the CVD chamber and the sputtering chamber to prevent crosstalk of the atmosphere between the CVD chamber and the sputtering chamber. Yes.
  • the stopper layer 16 has a two-layer structure of the first insulating film 16A and the second insulating film 16B, and the transistor according to the second embodiment described above. It is used for manufacturing the element 101 (FIG. 7). That is, the vacuum processing apparatus 302 includes a sputtering chamber 317A for forming the first insulating film 16A and a sputtering chamber 317B for forming the second insulating film 16B.
  • the gate insulating film 14 has a two-layer structure of a first gate insulating film 14A and a second gate insulating film 14B, and the stopper layer 16 has a first insulating film.
  • the transistor element 102 (FIG. 9) according to the third embodiment described above, which has a two-layer structure of 16A and the second insulating film 16B, is used. That is, the vacuum processing apparatus 303 includes a sputtering chamber 313A for forming the first gate insulating film 14A, a sputter material 313B for forming the second gate insulating film 14A, and the first insulating film 16A.
  • the stopper layer forming film 16F can be formed after the IGZO film 15F is formed without exposing the IGZO film 15F to the atmosphere, as in the first and second embodiments described above. It becomes. Thereby, it is possible to prevent film quality deterioration due to adhesion of moisture and impurities in the atmosphere to the surface of the IGZO film 15F. Further, since the stopper layer forming film 16F can be continuously formed after the IGZO film 15F is formed, the process time required for forming the stopper layer forming film 16F can be shortened, and the productivity is improved. be able to.
  • the gate insulating film 14 is formed by the sputtering method, the introduction system of the source gas and the exhaust gas removal equipment required for the CVD process become unnecessary. . This makes it possible to reduce equipment costs and clean the process. Furthermore, since the gate insulating film 14 is formed by the sputtering method, it is not necessary to install a buffer chamber between the sputtering chamber for forming the active layer.
  • the method for manufacturing a bottom gate type field effect transistor has been described as an example.
  • the present invention is not limited to this, and the present invention can be applied to a method for manufacturing a top gate type field effect transistor. It is.
  • the present invention is not limited to this, and at least one of the first and second gate insulating films 14A and 14B may be formed by a CVD method.
  • the gate insulating film 14 is not limited to an example composed of a single layer film of a silicon oxide film or a silicon nitride film.
  • the gate insulating film can be composed of a laminated film of a silicon oxide film and a silicon nitride film. is there.

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Abstract

La présente invention concerne un procédé de fabrication d'un transistor à effet de champ. Selon ce procédé, une couche active peut être protégée d'un agent de gravure sans être exposée à l’air ambiant. La présente invention concerne également un dispositif permettant de fabriquer ce transistor. Un procédé de fabrication d'un transistor à effet de champ comprend une étape consistant à réaliser une couche active (15) (film IGZO (15F)) ayant une composition à base de In-Ga-Zn-O, sur un matériau de base (10), en utilisant un procédé de pulvérisation. Le procédé comprend également une étape consistant à réaliser, sur la couche active, une couche tampon (16) (film de formation de couche tampon (16F)) qui a pour fonction de protéger la couche active d'un agent de gravure utilisé pour réaliser la couche active selon le procédé de pulvérisation. Le procédé comprend en outre une étape consistant à graver la couche active, en utilisant la couche tampon comme masque. En déposant la couche tampon selon le procédé de pulvérisation, il est possible de réaliser la couche tampon sans exposer la couche active à l'air ambiant après que la couche active a été déposée. Il est donc ainsi possible de prévenir une dégradation de la qualité du film, occasionnée par l'adhérence d'eau et d'impuretés contenues dans l'air à la surface de la couche active.
PCT/JP2009/064842 2008-08-29 2009-08-26 Procédé et dispositif de fabrication d'un transistor à effet de champ WO2010024279A1 (fr)

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KR1020137005674A KR101273143B1 (ko) 2008-08-29 2009-08-26 전계 효과형 트랜지스터의 제조 방법 및 제조 장치

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Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011243631A (ja) * 2010-05-14 2011-12-01 Fujifilm Corp 電子デバイスの製造方法、薄膜トランジスタ、電気光学装置及びセンサー
JP2011249674A (ja) * 2010-05-28 2011-12-08 Fujifilm Corp 薄膜トランジスタおよびその製造方法
JP2012023359A (ja) * 2010-06-18 2012-02-02 Semiconductor Energy Lab Co Ltd 半導体装置
CN102403225A (zh) * 2010-09-07 2012-04-04 无锡华润上华半导体有限公司 沟渠双扩散金属氧化半导体制作方法及装置
JP2012074596A (ja) * 2010-09-29 2012-04-12 Toppan Printing Co Ltd 薄膜トランジスタ、薄膜トランジスタを備える画像表示装置、薄膜トランジスタの製造方法、画像表示装置の製造方法
WO2013112026A1 (fr) 2012-01-27 2013-08-01 주식회사 유피케미칼 Couche d'oxyde contenant de l'indium et son procédé de fabrication
KR101293130B1 (ko) 2010-05-28 2013-08-12 엘지디스플레이 주식회사 어레이 기판 및 이의 제조방법
US9449852B2 (en) 2010-04-28 2016-09-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
KR101815324B1 (ko) 2010-11-05 2018-01-04 가부시키가이샤 제이올레드 박막 트랜지스터 및 그 제조 방법
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CN113725157B (zh) * 2021-08-27 2024-03-12 昆山龙腾光电股份有限公司 阵列基板及其制作方法

Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04177736A (ja) * 1990-11-09 1992-06-24 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型半導体装置の作製方法
JP2001257350A (ja) * 2000-03-08 2001-09-21 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2005285890A (ja) * 2004-03-29 2005-10-13 Casio Comput Co Ltd 亜鉛酸化物の加工方法
JP2007220818A (ja) * 2006-02-15 2007-08-30 Kochi Prefecture Sangyo Shinko Center 薄膜トランジスタ及びその製法
JP2008042088A (ja) * 2006-08-09 2008-02-21 Nec Corp 薄膜デバイス及びその製造方法
JP2008166716A (ja) * 2006-12-05 2008-07-17 Canon Inc ボトムゲート型薄膜トランジスタ、ボトムゲート型薄膜トランジスタの製造方法及び表示装置
JP2008172243A (ja) * 2007-01-09 2008-07-24 Korea Electronics Telecommun 原子層蒸着法を利用したｐ型ＺｎＯ半導体膜の製造方法及びその製造方法で製造されたＺｎＯ半導体膜を含む薄膜トランジスタ

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01125978A (ja) * 1987-11-11 1989-05-18 Hitachi Ltd 薄膜トランジスタの製造方法
JPH03148136A (ja) * 1989-11-02 1991-06-24 Matsushita Electric Ind Co Ltd 半導体素子および半導体素子の製造方法
JP2913737B2 (ja) * 1990-03-14 1999-06-28 富士通株式会社 薄膜トランジスタの製造方法
JPH05160152A (ja) * 1991-12-05 1993-06-25 Fujitsu Ltd 薄膜トランジスタの製造方法
JPH06188422A (ja) * 1992-12-18 1994-07-08 Fuji Xerox Co Ltd 薄膜トランジスタ
JP3429957B2 (ja) * 1996-08-28 2003-07-28 松下電器産業株式会社 スパッタリング方法及び装置
JP4870403B2 (ja) * 2005-09-02 2012-02-08 財団法人高知県産業振興センター 薄膜トランジスタの製法
JP2007073705A (ja) 2005-09-06 2007-03-22 Canon Inc 酸化物半導体チャネル薄膜トランジスタおよびその製造方法
JP5064747B2 (ja) 2005-09-29 2012-10-31 株式会社半導体エネルギー研究所 半導体装置、電気泳動表示装置、表示モジュール、電子機器、及び半導体装置の作製方法
EP1933293A4 (fr) * 2005-10-05 2009-12-23 Idemitsu Kosan Co Substrat pour tft et procede de fabrication d'un substrat pour tft

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04177736A (ja) * 1990-11-09 1992-06-24 Semiconductor Energy Lab Co Ltd 絶縁ゲイト型半導体装置の作製方法
JP2001257350A (ja) * 2000-03-08 2001-09-21 Semiconductor Energy Lab Co Ltd 半導体装置およびその作製方法
JP2005285890A (ja) * 2004-03-29 2005-10-13 Casio Comput Co Ltd 亜鉛酸化物の加工方法
JP2007220818A (ja) * 2006-02-15 2007-08-30 Kochi Prefecture Sangyo Shinko Center 薄膜トランジスタ及びその製法
JP2008042088A (ja) * 2006-08-09 2008-02-21 Nec Corp 薄膜デバイス及びその製造方法
JP2008166716A (ja) * 2006-12-05 2008-07-17 Canon Inc ボトムゲート型薄膜トランジスタ、ボトムゲート型薄膜トランジスタの製造方法及び表示装置
JP2008172243A (ja) * 2007-01-09 2008-07-24 Korea Electronics Telecommun 原子層蒸着法を利用したｐ型ＺｎＯ半導体膜の製造方法及びその製造方法で製造されたＺｎＯ半導体膜を含む薄膜トランジスタ

Cited By (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2018182337A (ja) * 2010-02-05 2018-11-15 株式会社半導体エネルギー研究所 半導体装置
JP2020150266A (ja) * 2010-04-09 2020-09-17 株式会社半導体エネルギー研究所 表示装置
US9449852B2 (en) 2010-04-28 2016-09-20 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor device
JP2011243631A (ja) * 2010-05-14 2011-12-01 Fujifilm Corp 電子デバイスの製造方法、薄膜トランジスタ、電気光学装置及びセンサー
JP2011249674A (ja) * 2010-05-28 2011-12-08 Fujifilm Corp 薄膜トランジスタおよびその製造方法
KR101792258B1 (ko) * 2010-05-28 2017-11-20 후지필름 가부시키가이샤 박막 트랜지스터 및 그 제조 방법
KR101293130B1 (ko) 2010-05-28 2013-08-12 엘지디스플레이 주식회사 어레이 기판 및 이의 제조방법
KR101862808B1 (ko) * 2010-06-18 2018-05-30 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 장치
JP2015213184A (ja) * 2010-06-18 2015-11-26 株式会社半導体エネルギー研究所 半導体装置
US9590112B2 (en) 2010-06-18 2017-03-07 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
JP2012023359A (ja) * 2010-06-18 2012-02-02 Semiconductor Energy Lab Co Ltd 半導体装置
US9947799B2 (en) 2010-06-18 2018-04-17 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
CN102403225A (zh) * 2010-09-07 2012-04-04 无锡华润上华半导体有限公司 沟渠双扩散金属氧化半导体制作方法及装置
JP2012074596A (ja) * 2010-09-29 2012-04-12 Toppan Printing Co Ltd 薄膜トランジスタ、薄膜トランジスタを備える画像表示装置、薄膜トランジスタの製造方法、画像表示装置の製造方法
KR101815324B1 (ko) 2010-11-05 2018-01-04 가부시키가이샤 제이올레드 박막 트랜지스터 및 그 제조 방법
WO2013112026A1 (fr) 2012-01-27 2013-08-01 주식회사 유피케미칼 Couche d'oxyde contenant de l'indium et son procédé de fabrication
US9431144B2 (en) 2012-01-27 2016-08-30 Up Chemical Co., Ltd. Indium-containing oxide film and preparing method thereof
JP2018026598A (ja) * 2012-11-16 2018-02-15 株式会社半導体エネルギー研究所 トランジスタ
US10361318B2 (en) 2012-11-16 2019-07-23 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US10886413B2 (en) 2012-11-16 2021-01-05 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US11710794B2 (en) 2012-11-16 2023-07-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device

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JP5417332B2 (ja) 2014-02-12
TW201017774A (en) 2010-05-01
KR101273143B1 (ko) 2013-06-17
TWI514478B (zh) 2015-12-21
JPWO2010024279A1 (ja) 2012-01-26
KR20130029454A (ko) 2013-03-22
KR20110028393A (ko) 2011-03-17
CN102165570A (zh) 2011-08-24

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