WO2010098101A1 - Transistor, procédé de fabrication de transistor et dispositif de fabrication associé - Google Patents

Transistor, procédé de fabrication de transistor et dispositif de fabrication associé Download PDF

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Publication number
WO2010098101A1
WO2010098101A1 PCT/JP2010/001270 JP2010001270W WO2010098101A1 WO 2010098101 A1 WO2010098101 A1 WO 2010098101A1 JP 2010001270 W JP2010001270 W JP 2010001270W WO 2010098101 A1 WO2010098101 A1 WO 2010098101A1
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film
transistor
insulating layer
layer
active layer
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PCT/JP2010/001270
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English (en)
Japanese (ja)
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武井応樹
赤松泰彦
小林大士
湯川富之
清田淳也
石橋暁
清水美穂
倉田敬臣
中村久三
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株式会社アルバック
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Priority to JP2011501508A priority Critical patent/JPWO2010098101A1/ja
Publication of WO2010098101A1 publication Critical patent/WO2010098101A1/fr

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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/7869—Thin film transistors, i.e. transistors with a channel being at least partly a thin film having a semiconductor body comprising an oxide semiconductor material, e.g. zinc oxide, copper aluminium oxide, cadmium stannate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
    • H01L29/4908—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET for thin film semiconductor, e.g. gate of TFT
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66969—Multistep manufacturing processes of devices having semiconductor bodies not comprising group 14 or group 13/15 materials

Definitions

  • the present invention relates to a transistor having an active layer made of an oxide semiconductor, a method for manufacturing the transistor, and an apparatus for manufacturing the transistor.
  • An active matrix liquid crystal display has a field effect thin film transistor (TFT) as a switching element for each pixel.
  • TFT thin film transistor
  • a polysilicon thin film transistor in which an active layer is made of polysilicon and an amorphous silicon thin film transistor in which an active layer is made of amorphous silicon are known.
  • An amorphous silicon thin film transistor has an advantage that it can be uniformly formed on a substrate having a relatively large area because an active layer can be easily produced as compared with a polysilicon thin film transistor.
  • Patent Document 2 discloses that various metal oxides, silicon oxides, and silicon nitrides can be applied as a constituent material of a gate dielectric in a transistor having a channel made of an oxide semiconductor. .
  • JP 2004-103957 A (paragraph [0010]) JP-T-2007-529119 (paragraphs [0014] to [0016])
  • the electrical conductivity of the active layer made of an oxide semiconductor is affected by the amount of oxygen contained. Therefore, depending on the type of constituent material of the gate insulating film and the film forming method, the oxygen concentration ratio of the active layer varies due to the interface reaction between the active layer and the gate insulating film, and the electrical conductivity of the active layer is reduced. May change. For example, when a silicon nitride film formed by a CVD method is used as the gate insulating film, oxygen in the active layer may be reduced due to residual hydrogen in the film. In this case, the electrical conductivity of the active layer is increased, which causes a problem that the off-current characteristics (current characteristics between the source and drain in the off state of the transistor) are degraded.
  • an object of the present invention is to provide a transistor capable of suppressing variation in electric conductivity of an active layer and ensuring a gate dielectric strength, a method for manufacturing the transistor, and a device for manufacturing the transistor. It is in.
  • a transistor according to one embodiment of the present invention includes a gate electrode, an active layer, a gate insulating film, and a source electrode and a drain electrode.
  • the gate electrode is made of copper or an alloy material containing copper.
  • the active layer is made of an oxide semiconductor.
  • the gate insulating film includes a first insulating layer and a second insulating layer. The first insulating layer is disposed between the gate electrode and the active layer and is made of silicon nitride. The second insulating layer is disposed between the first insulating layer and the active layer and is made of silicon oxide.
  • the source electrode and the drain electrode are electrically connected to the active layer, respectively.
  • a method for manufacturing a transistor according to one embodiment of the present invention includes forming a gate electrode made of copper or an alloy material containing copper on a base material.
  • a first insulating layer made of silicon nitride is formed on the gate electrode by a CVD method.
  • a second insulating layer made of silicon oxide is formed on the first insulating layer by a sputtering method or a CVD method.
  • An active layer made of an oxide semiconductor is formed on the second insulating layer.
  • a source electrode and a drain electrode are formed on the active layer.
  • a transistor manufacturing apparatus is an apparatus for manufacturing a thin film transistor over a base material on which a gate electrode made of copper or an alloy material containing copper is formed, and includes a first CVD chamber. And a first sputtering chamber or a second CVD chamber, a second sputtering chamber, and a transport mechanism.
  • the first CVD chamber forms a first insulating layer made of silicon nitride on the base material.
  • a second insulating layer made of silicon oxide is formed on the substrate.
  • an active layer made of an oxide semiconductor is formed on the base material.
  • the transport mechanism can transport the base material in a vacuum atmosphere between the first CVD chamber, the first sputter chamber or the second CVD chamber, and the second sputter chamber.
  • a transistor according to an embodiment of the present invention includes a gate electrode, an active layer, a gate insulating film, and a source electrode and a drain electrode.
  • the gate electrode is made of copper or an alloy material containing copper.
  • the active layer is made of an oxide semiconductor.
  • the gate insulating film includes a first insulating layer and a second insulating layer. The first insulating layer is disposed between the gate electrode and the active layer and is made of silicon nitride. The second insulating layer is disposed between the first insulating layer and the active layer and is made of silicon oxide.
  • the source electrode and the drain electrode are electrically connected to the active layer, respectively.
  • the gate insulating film has a stacked structure of a first insulating layer and a second insulating layer.
  • the second insulating layer located on the active layer side is made of silicon oxide, and the film formation method may be a sputtering method or a CVD method.
  • the silicon oxide film formed by the sputtering method does not contain hydrogen. Therefore, reduction of oxygen in the active layer by the hydrogen is avoided, and an increase in off-current value between the source and drain is prevented. As a result, it is possible to obtain a transistor having stable electrical characteristics while suppressing variations in the electrical conductivity of the active layer.
  • the silicon oxide film formed by the CVD method has a lower hydrogen content than the silicon nitride film, and the same characteristics as the silicon oxide film formed by the sputtering method have been confirmed.
  • the first insulating layer formed between the gate electrode and the second insulating layer is made of silicon nitride.
  • the first insulating layer functions as a barrier layer that prevents diffusion of copper atoms constituting the gate electrode into the second insulating layer made of silicon oxide. As a result, it is possible to prevent a decrease in the breakdown voltage of the gate insulating film and obtain a highly reliable transistor.
  • the method for forming the first insulating layer is not particularly limited, and a CVD method, a sputtering method, a vapor deposition method, or the like can be employed. Due to the presence of the second insulating layer at the interface with the active layer, the gate insulating film can be formed without adversely affecting the electric conduction characteristics of the active layer even if the film forming method can contain hydrogen in the film. Because it can be done.
  • the first insulating layer can be formed of a silicon nitride CVD film.
  • the CVD method has a higher film formation rate than the sputtering method. Thereby, productivity can be improved as compared with the case where the first insulating layer is formed by sputtering.
  • the silicon nitride film contains hydrogen in the film by using a silane-based gas containing hydrogen as a source gas.
  • the second insulating layer is interposed between the first insulating layer and the active layer, the reduction reaction of the active layer due to the hydrogen contained in the first insulating layer is effectively prevented. .
  • the transistor may further include a glass substrate that supports the gate electrode, and an adhesion layer that closely contacts the substrate and the gate electrode. Thereby, a gate electrode can be supported with high adhesiveness with respect to a base material.
  • the adhesion layer can be an oxide film of an alloy material containing copper. Thereby, the adhesiveness outstanding with respect to the glass-made base materials can be obtained, preventing the oxidation of a gate electrode.
  • the oxide semiconductor constituting the active layer can be made of, for example, an oxide material of In, Ga, or Zn. Thereby, a thin film transistor with high mobility can be obtained.
  • Examples of In, Ga, or Zn oxide-based materials include ZnO, ZnO 2 , GaO, Ga 2 O, Ga 2 O 3 , InO, In 2 O 3 , In—Zn—O-based materials, and Ga—Zn—O. Material, In—Ga—O material, In—Ga—Zn—O material, and the like are included.
  • the oxide semiconductor which comprises an active layer is not limited to said example, For example, other oxide semiconductors, such as CdO, can also be used.
  • a transistor manufacturing method includes forming a gate electrode made of copper or an alloy material containing copper on a base material.
  • a first insulating layer made of silicon nitride is formed on the gate electrode by a CVD method.
  • a second insulating layer made of silicon oxide is formed on the first insulating layer by a sputtering method or a CVD method.
  • An active layer made of an oxide semiconductor is formed on the second insulating layer.
  • a source electrode and a drain electrode are formed on the active layer.
  • the second insulating layer located on the active layer side is formed by a sputtering method or a CVD method.
  • a silicon oxide sputtered film does not contain hydrogen. Therefore, reduction of oxygen in the active layer by the hydrogen is avoided, and an increase in off-current value between the source and drain is prevented. Thereby, it is possible to suppress variation in the electric conductivity of the active layer.
  • the silicon oxide film formed by the CVD method has a lower hydrogen content than the silicon nitride film, and the same characteristics as the silicon oxide film formed by the sputtering method have been confirmed.
  • the first insulating layer is formed of a silicon nitride CVD film, productivity can be improved.
  • the silicon nitride film contains hydrogen in the film by using a silane-based gas containing hydrogen as a source gas.
  • the second insulating layer is interposed between the first insulating layer and the active layer, the reduction reaction of the active layer due to the hydrogen contained in the first insulating layer is effectively prevented.
  • the first insulating layer prevents an interfacial reaction between the gate electrode made of copper or a copper alloy and the second insulating layer made of silicon oxide. Thereby, the reliability of the gate insulating film can be ensured.
  • the method for manufacturing the transistor may further include a step of forming an adhesion layer that closely contacts the base material and the gate electrode before the step of forming the gate electrode. Thereby, the oxidation of the gate electrode can be prevented and excellent adhesion between the gate electrode and the substrate can be obtained.
  • an adhesion layer for example, an oxide film of an alloy material containing copper is used.
  • the first insulating layer, the second insulating layer, and the active layer may be continuously formed in a common vacuum processing apparatus. Thereby, the film quality and productivity can be improved.
  • An apparatus for manufacturing a transistor according to an embodiment of the present invention is an apparatus for manufacturing a thin film transistor on a base material on which a gate electrode made of copper or an alloy material containing copper is formed.
  • the first CVD chamber forms a first insulating layer made of silicon nitride on the base material.
  • a second insulating layer made of silicon oxide is formed on the substrate.
  • an active layer made of an oxide semiconductor is formed on the base material.
  • the transport mechanism can transport the base material in a vacuum atmosphere between the first CVD chamber, the first sputter chamber or the second CVD chamber, and the second sputter chamber.
  • the first insulating layer made of a silicon nitride CVD film and the second insulating layer made of a silicon oxide sputtered film or a CVD film are included without exposing the base material to the atmosphere.
  • a gate insulating film can be formed on a base material.
  • FIG. 1 is a schematic cross-sectional view showing a configuration of a transistor according to an embodiment of the present invention.
  • a so-called bottom gate type field effect transistor will be described as an example.
  • the transistor 1 of this embodiment includes a gate electrode 11, an active layer 15, a gate insulating film 14, a source electrode 17S, and a drain electrode 17D.
  • the gate electrode 11 is made of a conductive film formed on the surface of the substrate 10.
  • the base material 10 is a transparent glass substrate.
  • the gate electrode 11 is made of copper (Cu) or an alloy material containing copper, and is formed by, for example, a sputtering method or a CVD method.
  • the thickness of the gate electrode 11 is not specifically limited, For example, it is 300 nm.
  • the gate electrode 11 is formed on the surface of the base material 10 via the adhesion layer 24.
  • the adhesion layer 24 is provided in order to improve the adhesion between the gate electrode 11 and the substrate 10.
  • the adhesion layer 24 can be formed of a metal single layer film such as titanium (Ti) or molybdenum (Mo) or a laminated film thereof. Further, the adhesion layer 24 can be composed of an oxide film of an alloy such as copper and magnesium or chromium. Thereby, the oxidation of the gate electrode 11 can be prevented and the low resistance value can be maintained while ensuring the adhesion between the gate electrode 11 and the glass substrate 10.
  • the active layer 15 functions as a channel layer of the transistor 1.
  • the active layer 14 is made of an oxide semiconductor and is formed by a sputtering method.
  • the active layer 15 is formed of an oxide semiconductor material having an In—Ga—Zn—O-based composition, and the thickness thereof is, for example, 50 nm to 200 nm.
  • the gate insulating film 14 is formed between the gate electrode 11 and the active layer 15.
  • the gate electrode 14 has a stacked structure of a first insulating layer 14A and a second insulating layer 14B.
  • the first insulating layer 14A is located on the gate electrode 11 side
  • the second insulating layer 14B is located on the active layer 15 side.
  • the first insulating layer 14A is composed of a silicon nitride film (SiNx).
  • the first insulating layer 14A can be manufactured by a plasma CVD method.
  • the second insulating layer 14B is formed of a sputtered film of silicon oxide (SiO 2 or SiOx).
  • the second insulating layer 14B has a function of electrically insulating between the gate electrode 11 and the active layer 15 and a function of preventing an interface reaction between the first insulating layer 14A and the active layer 15. .
  • the interfacial reaction includes a reduction reaction of the active layer 15 by hydrogen when the first insulating layer 14A contains hydrogen.
  • the reduction reaction of the active layer 15 causes a decrease in the oxygen content of the film constituting the active layer 15, and this causes the electrical conductivity of the active layer 15 to increase.
  • Lowering the resistance of the active layer can contribute to improvements in responsiveness and on-current characteristics, but can cause an increase in off-current value when the transistor is not in operation, which can contribute to lowering the transistor characteristics.
  • the material composition of the active layer is optimized according to the required transistor characteristics, and is designed and manufactured so as to obtain the required electrical conductivity.
  • the material composition of the active layer changes due to an interfacial reaction with the gate insulating film that is the base layer after film formation, the desired transistor characteristics cannot be obtained, and variations in characteristics tend to occur from element to element.
  • the first insulating layer 14A a material that does not originally require hydrogen as a constituent element is used.
  • silicon nitride is formed by plasma CVD, silane (SiH 4 ) -based gas, ammonia (NH 3 ) -based gas, or the like is used as a source gas. Therefore, the silicon nitride film formed by the plasma CVD method contains a considerable amount of hydrogen generated during the reaction process. Therefore, when an oxide semiconductor layer is formed on the surface of a silicon nitride film formed by plasma CVD, the oxide semiconductor layer is reduced due to the presence of hydrogen, and the oxygen composition of the oxide semiconductor layer is reduced. Decrease. This makes it difficult to ensure the electrical characteristics of the target oxide semiconductor layer.
  • the first insulating layer 14A by a film forming method other than the CVD method such as a sputtering method or a vacuum evaporation method.
  • a film forming method other than the CVD method such as a sputtering method or a vacuum evaporation method.
  • the sputtering method and the like have a lower film formation rate than the CVD method, and thus it takes a lot of time to secure the target film thickness. For this reason, in order to ensure industrial productivity, it is practical to employ the plasma CVD method for forming the insulating layer.
  • the first insulating layer 14A is formed by a plasma CVD method to ensure productivity. Then, in order to avoid an interfacial reaction between the silicon nitride thin film produced by the plasma CVD method and the active layer 15, the silicon oxide film formed by the sputtering method is used as the second insulating layer 14B for the first insulation. It is interposed between the layer 14A and the active layer 15.
  • the sputtered silicon oxide film can be formed by a sputtering process in an inert gas atmosphere with respect to a silicon oxide target or a reactive sputtering process in an oxygen atmosphere with respect to a silicon target.
  • the silicon oxide film manufactured by such a sputtering process can avoid mixing of hydrogen into the film. Therefore, by stacking the sputtered silicon oxide film as the second insulating layer 14B on the first insulating layer 14A, the mutual reaction between the first insulating layer 14A and the active layer 15 is effectively prevented. As a result, desired electrical characteristics of the active layer 15 can be ensured.
  • the first insulating layer 14A formed between the gate electrode 11 and the second insulating layer 14B is made of silicon nitride.
  • the first insulating layer 14B functions as a barrier layer that prevents diffusion of copper atoms constituting the gate electrode 11 into the second insulating layer 14B made of silicon oxide. As a result, it is possible to obtain a highly reliable transistor by improving the responsiveness and preventing the breakdown voltage of the gate insulating film 14 from decreasing.
  • the thickness of the gate insulating film 14 is not particularly limited and is, for example, 200 nm to 400 nm.
  • the film thicknesses of the first and second insulating layers 14A and 14B are appropriately set within the range of the film thickness of the gate insulating film 14 which is the laminated thickness thereof.
  • the first insulating layer 14A is formed by a plasma CVD method
  • the first insulating layer 14 is made thicker than the second insulating layer 14B, thereby increasing the process time of the gate insulating film 14. Can be suppressed.
  • the film thickness of the second insulating layer 14B is not particularly limited as long as the interface reaction between the first insulating layer 14A and the active layer 15 can be suppressed.
  • the source electrode 17S and the drain electrode 17D are formed on the active layer 15 so as to be separated from each other.
  • the source electrode 17S and the drain electrode 17D can be composed of, for example, a metal single layer film such as aluminum, molybdenum, copper, titanium, or a multilayer film of these metals. As will be described later, the source electrode 17S and the drain electrode 17D can be simultaneously formed by patterning a metal film.
  • the thickness of the metal film is, for example, 100 nm to 500 nm.
  • a stopper layer 16 is formed on the active layer 15.
  • the stopper layer 16 is provided to protect the active layer 15 from the etchant during pattern etching of the source electrode 17S and the drain electrode 17D.
  • the stopper layer 16 can be composed of, for example, a silicon oxide film, a silicon nitride film, or a laminated film thereof.
  • the stopper layer 16 is formed by a film formation method (for example, sputtering method) in which hydrogen is not mixed into the film in order to avoid an interface reaction with the active layer.
  • the source electrode 17S and the drain electrode 17D are covered with a protective film 19.
  • the protective film 19 is made of an electrically insulating material such as a silicon nitride film.
  • the protective film 19 is for shielding the element part including the active layer 15 from the outside air.
  • the protective film 19 is provided with interlayer connection holes for connecting the source / drain electrodes 17S, 17D to the wiring layer 21 at appropriate positions.
  • the wiring layer 21 is for connecting the transistor 1 to a peripheral circuit (not shown), and is made of a metal film such as aluminum or copper.
  • FIG. 1 is a cross-sectional views of the main part of each step for explaining the manufacturing method of the transistor 1.
  • FIG. 2 to 6 are cross-sectional views of the main part of each step for explaining the manufacturing method of the transistor 1.
  • a gate electrode film 11F is formed on the oxide film 24F.
  • the base material 10 is typically a glass substrate.
  • the oxide film 24F is composed of an oxide film of an alloy such as copper, manganese, and chromium, and is formed by, for example, a sputtering method.
  • the oxide film 24F may be oxidized after the film formation, or may be formed directly by reactive sputtering.
  • the gate electrode film 11F is made of copper or an alloy material containing copper, and is formed by, for example, a sputtering method.
  • the thickness of the adhesion layer 24F is not particularly limited, and is, for example, 50 nm to 300 nm.
  • the thickness of the gate electrode film 11F is not particularly limited, and is, for example, 300 nm.
  • a resist mask 12 for patterning the gate electrode film 11F into a predetermined shape is formed.
  • This step includes a step of forming a photoresist film 12F (FIG. 2B), an exposure step (FIG. 2C), and a development step (FIG. 2D).
  • the photoresist film 12F is formed by applying a liquid photosensitive material on the gate electrode film 11F and then drying it.
  • a dry film resist may be used as the photoresist film 12F.
  • the formed photoresist film 12F is exposed through the mask 13 and then developed. Thereby, a resist mask 12 is formed on the gate electrode film 11F.
  • the gate electrode film 11F and the oxide film 24F are etched using the resist mask 12 as a mask. Thereby, the gate electrode 11 and the adhesion layer 24 are formed on the surface of the substrate 10 (FIG. 2F).
  • the etching method of the gate electrode film 11F is not particularly limited, and may be a wet etching method or a dry etching method. After the etching, the resist mask 12 is removed.
  • the method for removing the resist mask 12 is an ashing process using oxygen gas plasma, but is not limited to this, and may be dissolved and removed using a chemical solution.
  • a gate insulating film 14 is formed on the surface of the base material 10 so as to cover the gate electrode 11.
  • the thickness of the gate insulating film 14 is, for example, 200 nm to 500 nm.
  • the step of forming the gate insulating film 14 includes a step of forming the first insulating layer 14A and a step of forming the second insulating layer 14B.
  • the first insulating layer 14A is made of a silicon nitride film and is formed so as to cover the gate electrode 11 by plasma CVD.
  • a silane-based gas such as monosilane, disilane, or tetraethoxysilane (TEOS)
  • a source gas such as ammonia or nitrogen
  • a reactive gas is used.
  • the second insulating layer 14B is made of a silicon oxide film and is formed so as to cover the first insulating layer 14A by a sputtering method.
  • the second insulating layer 14B is formed by sputtering a target made of silicon oxide in an inert gas atmosphere such as argon under reduced pressure.
  • the film is formed by sputtering a target made of silicon in a mixed gas atmosphere of argon and oxygen under reduced pressure.
  • the thickness of the first insulating layer 14A and the second insulating layer 14B can be set as appropriate.
  • the CVD method has a higher deposition rate and coverage than the sputtering method, so that the first insulating layer 14A is thicker than the second insulating layer 14B to ensure good productivity. Can do.
  • the second insulating layer 14B may have a thickness that can suppress the interface reaction between the first insulating layer 14A and the active layer 15.
  • IGZO film 15F having an In—Ga—Zn—O-based composition and a stopper layer forming film 16F are formed. Are formed in order.
  • the IGZO film 15F and the stopper layer forming film 16F are formed by, for example, a sputtering method.
  • the IGZO film 15F and the stopper layer forming film 16F can be continuously formed.
  • the sputtering target for forming the IGZO film 15F and the sputtering target for forming the stopper layer forming film 16F may be disposed in the same sputtering chamber. By switching the target to be used, the IGZO film 15F and the stopper layer forming film 16F can be formed independently.
  • the IGZO film 15F can be formed by, for example, a reactive sputtering method in which a reaction product with oxygen is deposited on the substrate 10 by sputtering a target in an oxygen gas atmosphere.
  • the discharge type may be any of DC discharge, AC discharge, and RF discharge.
  • the IGZO film 15F may be formed with the substrate 10 heated to a predetermined temperature, or may be formed without heating.
  • the degree of oxidation of the IGZO film 15F is controlled by the oxygen partial pressure in the deposition chamber. That is, as the oxygen partial pressure is higher, the IGZO film 15F having a higher degree of oxidation (higher electrical resistance) is formed.
  • each of the IGZO film 15F and the stopper layer forming film 16F is not particularly limited.
  • the thickness of the IGZO film 15F is 50 nm to 200 nm, and the thickness of the stopper layer forming film 16F is 30 nm to 300 nm.
  • the IGZO film 15F constitutes an active layer (carrier layer) 15 of the transistor.
  • the stopper layer forming film 16F is an etching protection that protects the channel region of the IGZO film from the etchant in the patterning process of the metal film constituting the source electrode and the drain electrode, which will be described later, and the process of etching away the unnecessary area of the IGZO film 15F. Acts as a layer.
  • the stopper layer forming film 16F is made of, for example, a silicon nitride film.
  • a resist mask 23 for patterning the stopper layer forming film 16F into a predetermined shape is formed, and then the stopper layer forming film 16F is interposed through the resist mask 23. Etch. Thereby, the stopper layer 16 facing the gate electrode 11 is formed with the gate insulating film 14 and the IGZO film 15F interposed therebetween.
  • a metal film 17F is formed so as to cover the IGZO film 15F and the stopper layer 16, as shown in FIG.
  • the metal film 17F is typically composed of a metal single layer film or a metal multilayer film such as molybdenum, chromium, aluminum, or copper, and is formed by, for example, a sputtering method.
  • the thickness of the metal film 17F is not particularly limited, and is, for example, 100 nm to 500 nm.
  • the metal film 17F is patterned.
  • the patterning process of the metal film 17F includes a resist mask 18 formation process (FIG. 3A) and a metal film 17F etching process (FIG. 3B).
  • the resist mask 18 has a mask pattern that opens the region immediately above the stopper layer 16 and the peripheral region of each transistor. After the formation of the resist mask 18, the metal film 17F is etched by wet etching. Thus, the metal film 17F is separated into the source electrode 17S and the drain electrode 17D that are electrically connected to the active layer 15, respectively.
  • the stopper layer 16 functions as an etching stopper layer for the metal film 17F. That is, the stopper layer 16 has a function of protecting the IGZO film 15F from an etchant (for example, phosphorous nitric acid) with respect to the metal film 17F.
  • the stopper layer 16 is formed so as to cover a region (hereinafter referred to as “channel region”) located between the source electrode 17S and the drain electrode 17D of the IGZO film 15F. Therefore, the channel region of the IGZO film 15F is not affected by the etching process of the metal film 17F.
  • the IGZO thin film 15F is etched using the resist mask 18 as a mask.
  • the etching method is not particularly limited, and may be a wet etching method or a dry etching method.
  • the IGZO film 15F is isolated in element units and an active layer 15 made of the IGZO film 15F is formed.
  • the stopper layer 16 functions as an etching protective film for the IGZO film 15F located in the channel region. That is, the stopper layer 16 has a function of protecting the channel region immediately below the stopper layer 16 from an etchant (for example, oxalic acid type) for the IGZO film 15F. Thereby, the channel region of the active layer 15 is not affected by the etching process of the IGZO film 15F.
  • an etchant for example, oxalic acid type
  • the resist mask 18 is removed from the source electrode 17S and the drain electrode 17D by ashing or the like (FIG. 4D).
  • a protective film (passivation film) is formed so as to cover the surface of the substrate 10 with the source electrode 17S, the drain electrode 17D, the stopper layer 16, the active layer 15, and the gate insulating film 14. ) 19 is formed.
  • the protective film 19 is for securing predetermined electrical and material characteristics by blocking the transistor element including the active layer 15 from the outside air.
  • the protective film 19 is typically composed of an oxide film or nitride film such as a silicon oxide film (SiO 2 ) or a silicon nitride film (SiNx), and is formed by, for example, a CVD method or a sputtering method.
  • the thickness of the protective film 19 is not particularly limited, and is, for example, 200 nm to 500 nm.
  • contact holes 19a communicating with the source / drain electrodes are formed in the protective film 19.
  • This step includes a step of forming a resist mask 20 on the protective film 19 (FIG. 5B) and a step of etching the protective film 19 exposed from the opening 20a of the resist mask 20 (FIG. 5C). And a step of removing the resist mask 20 (FIG. 5D).
  • the contact hole 19a is formed by a dry etching method, but may be a wet etching method. Although not shown, a contact hole that communicates with the source electrode 17S is also formed at an arbitrary position.
  • a transparent conductive film 21 in contact with the source / drain electrode is formed through the contact hole 19a.
  • This step includes the step of forming the transparent conductive film 21F (FIG. 6A), the step of forming the resist mask 22 on the transparent conductive film 21F (FIG. 6B), and the step of covering with the resist mask 22. It has a step (FIG. 6C) of etching the transparent conductive film 21F that has not been removed and a step of removing the resist mask 20 (FIG. 6D).
  • the transparent conductive film 21F is typically composed of an ITO film or an IZO film, and is formed by, for example, a sputtering method or a CVD method.
  • the etching of the transparent conductive film 21F employs a wet etching method, but is not limited thereto, and a dry etching method may be employed.
  • This annealing step may be performed immediately after the formation of the active layer 15 (for example, before the formation of the stopper layer 16).
  • a constant forward voltage (source-drain voltage: Vds) is applied between the source electrode 17S and the drain electrode 17D.
  • Vgs gate voltage
  • Vth threshold voltage
  • Ids source-drain current
  • the source-drain current at this time is also called an on-state current, and a larger current value is obtained as the mobility of the active layer 15 is higher.
  • the active layer 15 is made of an oxide semiconductor, the mobility is higher than that of an active layer made of amorphous silicon. Therefore, according to the present embodiment, the field effect transistor 1 having a high on-current value can be obtained.
  • the source-drain current at this time is also called an off-state current and is determined by the electric resistance value of the active layer 15 and the source-drain voltage. The smaller the off-current value, the larger the ratio between the on-current value and the off-current value (on-off current ratio), so that better characteristics as a transistor can be obtained.
  • the gate insulating film 14 includes the first insulating layer 14A made of a silicon nitride film formed by a plasma CVD method and the second insulating layer made of a silicon oxide film formed by a sputtering method.
  • 14B has a laminated structure. Since the second insulating layer 14B is interposed between the active layer 15 and the first insulating layer 14A, the reduction reaction of the active layer 15 is prevented by the influence of hydrogen contained in the first insulating layer 14A. . Thereby, fluctuations in the electrical characteristics of the active layer 15 are avoided, and excellent transistor characteristics with a high on-off current ratio can be obtained.
  • FIG. 7 and 8 show the experimental results showing the transistor characteristics of various samples manufactured by changing the structure of the gate insulating film in the transistor structure shown in FIG.
  • the configuration of the active layer and the film formation conditions for each sample were the same. Two conditions were set for the oxygen partial pressure, and each sample was produced under each condition.
  • FIG. 7 shows the experimental results when the oxygen partial pressure is 0.05 Pa
  • FIG. 8 shows the experimental results when the oxygen partial pressure is 0.15 Pa.
  • the active layer was 50 nm thick, and the annealing conditions were 15 minutes at 300 ° C. in air.
  • the configuration of the gate insulating film of each sample is as follows.
  • Sample 1 A laminated film of a silicon nitride film having a thickness of 3500 mm (angstrom) produced by the CVD method and a silicon oxide film having a thickness of 250 mm produced thereon by a sputtering method.
  • Sample 2 produced by the CVD method Laminated film of 3500 mm thick silicon nitride film and 500 mm thick silicon oxide film formed thereon by sputtering method
  • Sample 3 Silicon oxide film (single layer film) 2150 mm thick produced by sputtering method
  • Sample 4 ( ⁇ ): 3500 mm thick silicon nitride film (single layer film) produced by CVD
  • the transistor characteristics schematically show the on-current characteristics on the right side and the off-current characteristics on the left side with respect to the position of the gate voltage (Vgs) 0.
  • samples 1 to 3 have substantially the same on-current value and off-current value, whereas sample 4 has a higher off-current value than the other samples.
  • the interface between the gate insulating film and the active layer is composed of a silicon nitride CVD film. For this reason, an interface reaction occurs between the gate insulating film and the active layer, and it is considered that the electrical resistance value of the active layer has decreased due to a decrease in the oxidation degree of the active layer compared to other samples.
  • FIGS. 9 and 10 are schematic configuration diagrams of a vacuum processing apparatus for carrying out a part of the above-described transistor manufacturing process.
  • the vacuum processing apparatus 200 shown in FIG. 9 is configured as a single wafer type (cluster type) vacuum processing apparatus.
  • the vacuum processing apparatus 200 forms a transfer chamber 210, a loading chamber 211, a heat treatment chamber 212, a CVD chamber 213A for forming the first gate insulating layer 14A, and a second gate insulating layer 14B.
  • the transfer chamber 210 is evacuated to a predetermined reduced-pressure atmosphere, and a transfer robot for transferring the base material between the chambers is installed therein.
  • the second gate insulating layer 14B is formed of a silicon oxide CVD film
  • the sputtering chamber 213B is configured as a CVD chamber.
  • a vacuum processing apparatus 300 shown in FIG. 10 is configured as an in-line type vacuum processing apparatus.
  • the vacuum processing apparatus 300 includes a loading chamber 311, a heat treatment chamber 312, a CVD chamber 313A for forming the first gate insulating layer 14A, and a sputtering chamber 313B for forming the second gate insulating layer 14B.
  • the vacuum processing apparatus 300 includes a transport mechanism (not shown) for vacuum transporting the substrate from the loading chamber 311 to the unload chamber 317 via the various processing chambers 312 to 316.
  • a transport mechanism (not shown) for vacuum transporting the substrate from the loading chamber 311 to the unload chamber 317 via the various processing chambers 312 to 316.
  • the sputtering chamber 313B is configured as a CVD chamber.
  • the gate insulating film 14, the IGZO film 15F, and the stopper layer 16 can be continuously formed without exposing the base material to the atmosphere. Thereby, it is possible to prevent film quality deterioration due to adhesion of moisture and impurities in the atmosphere to the surface of each layer. In addition, since various functional layers can be formed consistently in a vacuum, the process time required for forming each layer can be shortened, and productivity can be improved.
  • the gate insulating film 14 has a stacked structure of a first insulating layer 14A made of a silicon nitride CVD film and a second insulating layer 14B made of a silicon oxide CVD film. Have. Since the other configuration is the same as that of the first embodiment, the description thereof is omitted here.
  • FIG. 11 shows another experimental result showing the transistor characteristics of various samples manufactured by changing the structure of the gate insulating film in the transistor structure shown in FIG.
  • the configuration of the active layer and the film formation conditions of each sample were common, the oxygen partial pressure was 0.05 Pa, the thickness of the active layer was 50 nm, and the annealing conditions were 15 minutes at a temperature of 400 ° C. in air.
  • the configuration of the gate insulating film of each sample is as follows.
  • sample 5 had a smaller off-current value than sample 4. This indicates that even in the same CVD method, the degree of interfacial reaction with the active layer varies depending on the type of film formed. Further, as described with reference to FIG. 7, the sample 5 has an off-current value similar to that of the silicon oxide films (samples 1 to 3) formed by the sputtering method.
  • the silicon oxide film when the silicon oxide film is formed by the CVD method, a silane-based gas is typically used as the reaction gas, as in the case of forming the silicon nitride film by the CVD method. Therefore, it is considered that the formed film contains hydrogen. Even in the same CVD method, the silicon oxide film can obtain higher transistor characteristics than the silicon nitride film because the amount of hydrogen contained in the film and the internal stress / dehydration in the heat treatment (for example, annealing treatment for the active layer 15) The degree of element is expected.
  • FIG. 12 shows an experimental result indicating transistor characteristics when the annealing temperature of the active layer is 400 ° C. and the gate insulating film is Sample 3 ( ⁇ : sputtered film of silicon oxide). Compared with the above-described sample 4 ( ⁇ ⁇ ), a high on-off current ratio can be obtained as in the example shown in FIG. On the other hand, it was confirmed that the characteristics could be further improved by increasing the annealing temperature. When FIG. 11 and FIG. 12 are compared, it was confirmed that a sputtered film can obtain a higher on-off current ratio than a CVD film even under the same annealing conditions, even with the same silicon oxide film.
  • the stopper layer 16 is constituted by a single layer, but it may be a multilayer structure like the gate insulating film.
  • the first layer constituting the interface with the active layer is a silicon oxide sputtered film, so that reduction of the active layer can be avoided and fluctuations in the electrical conductivity characteristics can be prevented.
  • the transistor 1 described above can be used as a TFT for an active matrix display panel such as a liquid crystal display or an organic EL display.
  • the transistor 1 can be used as a transistor element of various semiconductor devices or electronic devices.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
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  • Manufacturing & Machinery (AREA)
  • Thin Film Transistor (AREA)
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Abstract

L'invention concerne un transistor et son procédé de fabrication, avec lequel les variations de la conductivité électrique d'une couche active peuvent être supprimées et la sensibilité peut être améliorée tout en garantissant la tension de tenue de grille. Le transistor est doté d'un film d'isolation de grille (14) présentant une structure stratifiée, qui comprend une première couche isolante (14A) constituée d'un film de nitrure de silicium, et une seconde couche isolante (14B) constituée d'un film d'oxyde de silicium entre une électrode de grille (11) en cuivre et une couche active (15) constituée d'un semi-conducteur d'oxyde. La seconde couche isolante (14B) empêche une fluctuation de la conductivité électrique de la couche active (15) provoquée par la réaction interfaciale entre la première couche isolante (14A) et la couche active (15). La première couche isolante (14A) fonctionne comme une couche barrière pour empêcher la dispersion des atomes de cuivre qui constituent l'électrode de grille (11) dans la seconde couche isolante (14B).
PCT/JP2010/001270 2009-02-27 2010-02-25 Transistor, procédé de fabrication de transistor et dispositif de fabrication associé WO2010098101A1 (fr)

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JP2017126794A (ja) * 2012-05-10 2017-07-20 株式会社半導体エネルギー研究所 半導体装置
JP2017228800A (ja) * 2012-05-10 2017-12-28 株式会社半導体エネルギー研究所 半導体装置
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JP2017126794A (ja) * 2012-05-10 2017-07-20 株式会社半導体エネルギー研究所 半導体装置
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KR20150101404A (ko) * 2014-02-24 2015-09-03 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 이용한 표시장치
KR101679956B1 (ko) * 2014-02-24 2016-12-07 엘지디스플레이 주식회사 박막 트랜지스터 기판 및 이를 이용한 표시장치
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