WO2009005017A1 - 半導体パッケージおよびその製造方法 - Google Patents

半導体パッケージおよびその製造方法 Download PDF

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Publication number
WO2009005017A1
WO2009005017A1 PCT/JP2008/061773 JP2008061773W WO2009005017A1 WO 2009005017 A1 WO2009005017 A1 WO 2009005017A1 JP 2008061773 W JP2008061773 W JP 2008061773W WO 2009005017 A1 WO2009005017 A1 WO 2009005017A1
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WIPO (PCT)
Prior art keywords
semiconductor
semiconductor package
substrate
manufacturing
same
Prior art date
Application number
PCT/JP2008/061773
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English (en)
French (fr)
Inventor
Yuki Suto
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Fujikura Ltd.
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujikura Ltd. filed Critical Fujikura Ltd.
Priority to EP08790715A priority Critical patent/EP2164098A4/en
Priority to CN200880022659A priority patent/CN101689533A/zh
Publication of WO2009005017A1 publication Critical patent/WO2009005017A1/ja
Priority to US12/648,172 priority patent/US8330268B2/en

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Abstract

　半導体デバイスと、前記半導体デバイスが一面に配置された半導体基板と、前記半導体基板の一面に、間隔を介して対向する一面を有するキャップ基板と、前記半導体基板の一面と前記キャップ基板の一面との間に配置され、前記半導体基板と前記キャップ基板とを接合するスペーサーと、前記キャップ基板に、前記スペーサーとは重ならず、前記半導体デバイスと重なるように設けられたフィルタと、を備える半導体パッケージを提供する。本発明に拠れば、ダイシング工程でのチッピングによるフィルタの剥離を抑制することができる半導体パッケージおよびその製造方法を提供可能である。
PCT/JP2008/061773 2007-06-29 2008-06-27 半導体パッケージおよびその製造方法 WO2009005017A1 (ja)

Priority Applications (3)

Application Number Priority Date Filing Date Title
EP08790715A EP2164098A4 (en) 2007-06-29 2008-06-27 SEMICONDUCTOR PACK AND MANUFACTURING METHOD THEREFOR
CN200880022659A CN101689533A (zh) 2007-06-29 2008-06-27 半导体封装组件及其制造方法
US12/648,172 US8330268B2 (en) 2007-06-29 2009-12-28 Semiconductor package and manufacturing method thereof

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2007-171915 2007-06-29
JP2007171915A JP2009010261A (ja) 2007-06-29 2007-06-29 半導体パッケージおよびその製造方法

Related Child Applications (1)

Application Number Title Priority Date Filing Date
US12/648,172 Continuation US8330268B2 (en) 2007-06-29 2009-12-28 Semiconductor package and manufacturing method thereof

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WO2009005017A1 true WO2009005017A1 (ja) 2009-01-08

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PCT/JP2008/061773 WO2009005017A1 (ja) 2007-06-29 2008-06-27 半導体パッケージおよびその製造方法

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US (1) US8330268B2 (ja)
EP (1) EP2164098A4 (ja)
JP (1) JP2009010261A (ja)
KR (1) KR20100025538A (ja)
CN (1) CN101689533A (ja)
TW (1) TW200913239A (ja)
WO (1) WO2009005017A1 (ja)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2010095201A1 (ja) * 2009-02-20 2010-08-26 パナソニック株式会社 半導体装置及び半導体装置の製造方法
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WO2011035783A1 (de) * 2009-09-24 2011-03-31 Msg Lithoglas Ag Herstellungsverfahren eines gehäuses mit einem bauelement in einem hohlraum und entsprechendes gehäuse sowie verfahren zum herstellen eines halbzeuges und halbzeug
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