Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/01—Manufacture or treatment
  • H10D30/021—Manufacture or treatment of FETs having insulated gates [IGFET]
  • H10D30/0411—Manufacture or treatment of FETs having insulated gates [IGFET] of FETs having floating gates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/67—Thin-film transistors [TFT]
  • H10D30/6704—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device
  • H10D30/6713—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes
  • H10D30/6715—Thin-film transistors [TFT] having supplementary regions or layers in the thin films or in the insulated bulk substrates for controlling properties of the device characterised by the properties of the source or drain regions, e.g. compositions or sectional shapes characterised by the doping profiles, e.g. having lightly-doped source or drain extensions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/68—Floating-gate IGFETs
  • H10D30/681—Floating-gate IGFETs having only two programming levels
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D30/00—Field-effect transistors [FET]
  • H10D30/60—Insulated-gate field-effect transistors [IGFET]
  • H10D30/69—IGFETs having charge trapping gate insulators, e.g. MNOS transistors
  • H10D30/694—IGFETs having charge trapping gate insulators, e.g. MNOS transistors characterised by the shapes, relative sizes or dispositions of the gate electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/01—Manufacture or treatment
  • H10D64/031—Manufacture or treatment of data-storage electrodes
  • H10D64/035—Manufacture or treatment of data-storage electrodes comprising conductor-insulator-conductor-insulator-semiconductor structures
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
  • H10D64/00—Electrodes of devices having potential barriers
  • H10D64/60—Electrodes characterised by their materials
  • H10D64/66—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes
  • H10D64/68—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator
  • H10D64/681—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered
  • H10D64/685—Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes characterised by the insulator, e.g. by the gate insulator having a compositional variation, e.g. multilayered being perpendicular to the channel plane

Definitions

• the present invention relates to a semiconductor device having memory elements and a method of fabricating the semiconductor device.
• a semiconductor device in the invention refers to a device having a circuit including semiconductor elements (such as transistors and diodes).
• Memory can be broadly divided into two kinds, i.e., volatile memory and nonvolatile memory.
• Volatile memory is memory whose memory content is lost once power is turned off.
• Nonvolatile memory is memory that can retain its memory content even when power is turned off. Examples of volatile memory include DRAM (dynamic random access memory) and SRAM (static random access memory).
• DRAM dynamic random access memory
• SRAM static random access memory
• the use of volatile memory is very limited as the memory content is lost once power is turned off; however, the volatile memory is used for cache memory of computers or the like because of its advantage of a short access time.
• DRAM has small memory cells and can have a high capacity; however, a method of controlling the DRAM is complex, resulting in high power consumption. Meanwhile, methods of fabricating and controlling SRAM are easy since it has memory cells constructed from CMOS; however, the SRAM has a difficulty in having a high capacity since each memory cell requires six transistors.
• Nonvolatile memory which is memory capable of retaining its memory content even when power is turned off, can be broadly divided into three kinds, i.e., rewritable memory, write-once memory, and mask ROM (read only memory).
• Rewritable memory can be rewritten with data up to a limited number of times.
• Write-once memory can be written with data by a user only once.
• the data content of mask ROM is determined during its fabrication, and the data content cannot be rewritten.
• Examples of rewritable nonvolatile memory include EPROM, flash memory, and ferroelectric memory.
• EPROM can be written with data easily, and has a relatively low unit cost per bit.
• EPROM requires dedicated programming and erasing devices for writing and erasing data.
• flash memory and ferroelectric memory can be rewritten with data on a substrate being used, and have a short access time and low power consumption.
• a structure of flash memory there is known a structure in which a tunneling insulating film, a floating gate, a gate insulating film, and a control gate are formed over an active layer (see Reference 1: Japanese Published Patent Application No. 2006-13481).
• electrical charge is injected to the floating gate through the tunneling insulating film over the channel formation region which is formed in the active layer, so that the electrical charge is retained in the memory.
• a floating gate is formed with a metal film, for example, a titanium film
• a metal film for example, a titanium film
• titanium atoms diffuse into a tunneling insulating film depending on the temperature of heat treatment applied during a fabrication process.
• the diffusion of the titanium atoms into the tunneling insulating film will result in a reduction in thickness of the tunneling insulating film.
• an oxide film containing the material of a floating gate is formed between the floating gate and a tunneling insulating film. Accordingly, even when an element included in the floating gate is diffused by heat, it will not diffuse into the tunneling insulating film because of the presence of the oxide film. Since the oxide film originally contains the element included in the floating gate, there arises no problem when the element included in the floating gate diffuses into the oxide film.
• the invention relates to the following nonvolatile semiconductor memory device and memory element, and a method of fabricating them. [0013]
• the invention relates to a semiconductor device having an island-like semiconductor film, which is formed over an insulating surface and includes a channel formation region and a high-concentration impurity region, a tunneling insulating film formed over the island-like semiconductor film, a floating gate formed over the tunneling insulating film, a gate insulating film formed over the floating gate, a control gate formed over the gate insulating film, and a first insulating film formed between the tunneling insulating film and the floating gate.
• the first insulating film is formed of an oxide film of a material of the floating gate, so that the material of the floating gate is prevented from diffusing into the tunneling insulating film.
• a second insulating film is formed between the floating gate and the gate insulating film, and the second insulating film is formed of an oxide film of the material of the floating gate, so that the material of the floating gate is prevented from diffusing into the gate insulating film.
• the floating gate is formed of titanium, and the first insulating film is formed of titanium oxide.
• the floating gate is formed of titanium, and the second insulating film is formed of titanium oxide.
• the island-like semiconductor film is formed of a single-crystalline semiconductor layer.
• the thicknesses of the tunneling insulating film and the gate insulating film can be controlled. Accordingly, a memory element with high reliability can be provided.
• FIG 1 is a cross-sectional view of a memory element of the invention
• FIGS. 2 A to 2C are cross-sectional views illustrating the steps of fabricating a memory element of the invention.
• FIGS. 3 A to 3D are cross-sectional views illustrating the steps of fabricating a memory element of the invention.
• FIGS. 4 A to 4C are cross-sectional views illustrating the steps of fabricating a memory element of the invention.
• FIG 5 is a cross-sectional view of a memory element of the invention.
• FIG 6 is a block diagram of a semiconductor device capable of radio communication, which uses a memory element of the invention.
• FIGS. 7 A and 7B are circuit diagrams of a semiconductor device capable of radio communication, which uses a memory element of the invention
• FIGS. 8 A to 8F are views illustrating examples of the application of a semiconductor device of the invention
• FIGS. 9 A and 9B are cross-sectional views illustrating structures of a substrate with an SOI structure
• FIGS. 1OA to 1OC are cross-sectional views illustrating structures of a substrate with an SOI structure
• FIGS. HA to HC are cross-sectional views illustrating a method of fabricating a substrate with an SOI structure
• FIGS. 12A and 12B are cross-sectional views illustrating a method of fabricating a substrate with an SOI structure
• FIGS. 13 A to 13C are cross-sectional views illustrating a method of fabricating a substrate with an SOI structure
• FIGS. 14Ato 14C are cross-sectional views illustrating a method of fabricating a substrate with an SOI structure
• FIGS. 15A and 15B are cross-sectional views illustrating a method of fabricating a substrate with an SOI structure
• FIGS. 16Ato 16C are cross-sectional views illustrating a method of fabricating a substrate with an SOI structure.
• FIG 1 illustrates a cross-sectional structure of a memory ⁇ element of this embodiment mode.
• An island-like semiconductor film 102 which is an active layer is formed over an insulating surface 101.
• Formed in the island-like semiconductor film 102 are a channel formation region 103, low-concentration impurity regions 105, and high-concentration impurity regions 104 that are source and drain regions.
• a tunneling insulating film 106, an insulating film 131, a floating gate 107, an insulating film 132, a gate insulating film 108, and a control gate 109 are formed over the island-like semiconductor film 102.
• the insulating surface 101 can be a substrate or a substrate with an insulating film formed over its surface.
• the substrate include a glass substrate, a plastic substrate, and an SOI (silicon on insulator) substrate.
• the insulating film can be a silicon oxide film, a silicon nitride film, a silicon nitride film containing oxygen, or a silicon oxide film containing nitrogen.
• Silicon (Si) may be used for the island-like semiconductor film 102 which is the active layer.
• the thickness of the island-like semiconductor film 102 may be 60 nm, for example.
• silicon oxide may be used for the tunneling insulating film 106, and it is formed to a thickness of 8 to 10 nm.
• the insulating films 131 and 132 are each formed with an oxide film that includes the same material as the floating gate 107. Accordingly, even when a metal element of the floating gate 107 is diffused by heat, there is no problem because the insulating films 131 and 132 contain the same material as the floating gate 107 and, thus, the metal element will not diffuse into the tunneling insulating film 106 or the gate insulating film 108. Accordingly, the reliability of the memory element can be increased. [0027]
• the floating gate 107 is preferably formed with titanium (Ti). Besides, tantalum (Ta), tungsten (W), or the like can also be used. Therefore, the insulating films 131 and 132 are preferably formed with titanium oxide. Alternatively, when the floating gate 107 is formed with tantalum (Ta) or tungsten (W), the insulating films 131 and 132 can be formed with tantalum oxide, tungsten oxide, or the like.
• the insulating film 132 does not need to be formed if the gate insulating film 108 that will be formed in a later step is sufficiently thick such that the gate insulating film 108 remains with its insulating function intact even when the metal element of the floating gate 107 has diffused into the gate insulating film 108.
• the gate insulating film 108 and the control gate 109 are formed over the insulating film 132. When the insulating film 132 is not formed, the gate insulating film 108 and the control gate 109 are formed over the floating gate 107.
• the gate insulating film 108 may be formed with a silicon oxide film, a silicon nitride film, a silicon nitride film containing oxygen, a silicon oxide film containing nitrogen, or the like.
• the control gate 109 may be formed with tungsten (W), tantalum (Ta), titanium (Ti), aluminum (Al), or the like.
• the amorphous semiconductor film 113 is crystallized to form a crystalline semiconductor film 114.
• Crystallization may be carried out by introducing an element which promotes crystallization to the amorphous semiconductor film and applying heat treatment thereto or by irradiation with a laser beam.
• the amorphous silicon film is crystallized by irradiation with a laser beam 115, so that a crystalline silicon film is formed (see FIG 2B).
• the island-like semiconductor film 102 is formed using the crystalline semiconductor film 114 obtained (see FIG. 2C).
• the tunneling insulating film (also referred to as a tunneling oxide film) 106 is formed to a thickness of 8 to 10 nm (see FIG 3A).
• the tunneling insulating film 106 is formed to a thickness of 10 nm.
• an oxide film (a first oxide film), which includes the same material as the floating gate 107, is deposited.
• the floating gate 107 is preferably formed with titanium (Ti), but may also be formed with tantalum (Ta) or tungsten (W). Therefore, the first oxide film may be formed with titanium oxide, tantalum oxide, tungsten oxide, or the like.
• a conductive film for forming the floating gate 107 which is a titanium film here, is deposited over the first oxide film to a thickness of 20 nm by sputtering.
• a second oxide film is deposited to a thickness of, for example, 5 nm using the same material as the first oxide film, over the conductive film for forming the floating gate 107.
• the first oxide film, the conductive film, and the second oxide film are etched to form the insulating film 131, the floating gate 107, and the insulating film 132
• the insulating film 132 does not need to be formed if the gate insulating film 108 that will be formed in a later step is sufficiently thick such that the gate insulating film 108 remains with its insulating function intact even when the metal element of the floating gate 107 has diffused into the gate insulating film 108 (see FIG 5).
• the island-like semiconductor film 102 is doped with an impurity which imparts one conductivity type with the insulating film 131, the floating gate 107, and the insulating film 132 used as masks.
• phosphorus (P) is used as the impurity which imparts one conductivity type and is added at a dosage of 1.0 x 10 14 atoms/cm 2 and an accelerating voltage of 40 keV.
• low-concentration impurity regions 121 containing phosphorus at a concentration of 1 x 10 12 atoms/cm 3 are formed in regions of the island-like semiconductor film 102, which do no overlap with the insulating film 131, the floating gate 107, or the insulating film 132 (see FIG 3C).
• the gate insulating film 108 is formed to a thickness of 20 to 50 run over the insulating film 132 and the tunneling insulating film 106 or over the floating gate 107 and the tunneling insulating film 106 if the insulating film 132 is not formed (see FIG 3D).
• control gate 109 is formed over the gate insulating film 108, using a conductive film made of Ta, W, or the like (see FIG 4A).
• the control gate 109 is positioned to partially overlap with the low-concentration impurity regions 121 so that the control gate 109 is used as a mask for forming the low-concentration impurity regions 105 in a later step.
• the island-like semiconductor film 102 is doped with an impurity element which imparts one conductivity type with the control gate 109 used as a mask, so that the high-concentration impurity regions 104 that are the source and drain regions, the low-concentration impurity regions 105, and the channel formation region 103 are formed (see FIG 4B).
• phosphorus (P) is added at a dosage of 3.0 x 10 15 atoms/cm 2 and an accelerating voltage of 25 keV by doping. Note that since the impurity element which imparts one conductivity type is added with the control gate 109 used as a mask, the boundaries between the high-concentration impurity regions 104 and the low-concentration impurity regions 105 correspond to the edges of the control gate 109.
• an interlayer insulating film 118 is formed to cover the island-like semiconductor film 102 and the control gate 109. Further, contact holes, which reach the high-concentration impurity regions 104 that are the source and drain regions, are formed in the interlayer insulating film 118.
• conductive films are formed over the interlayer insulating film 118. With the conductive films, wirings 119, which are electrically connected to the high-concentration impurity regions 104 serving as the source and drain regions through the contact holes of the interlayer insulating film 118, are formed. Thus, a memory element is formed (see FIG 4C).
• the element does not diffuse into the gate insulating film 108 either.
• This embodiment mode will describe a case where a memory element of the invention is used for a semiconductor device capable of radio communication, with reference to FIGS. 6, 7A, and 7B.
• a semiconductor device 200 capable of radio communication of this embodiment mode includes an arithmetic processing circuit 201, a memory circuit 202, an antenna 203, a power supply circuit 204, a demodulation circuit 205, and a modulation circuit 206.
• the antenna 203 and the power supply circuit 204 are the essential components of the semiconductor device 200 capable of radio communication, and other components are provided as appropriate according to the use of the semiconductor device 200 capable of radio communication.
• the arithmetic processing circuit 201 based on a signal input from the demodulation circuit 205, analyzes instructions, controls the memory circuit 202, or outputs data, which is to be transmitted to the outside, to the modulation circuit 206, for example.
• the memory circuit 202 includes a circuit having memory elements and a control circuit for writing and reading data.
• the memory circuit 202 stores at least a unique identification number of the semiconductor device. The unique identification number is used for distinguishing the semiconductor device 200 from other semiconductor devices.
• the memory circuit 202 may be formed using the memory element described in Embodiment Mode 1. [0052]
• the antenna 203 converts a carrier wave, which is supplied from a reader/writer 207, to an AC electrical signal.
• the modulation circuit 206 applies load modulation.
• the power supply circuit 204 generates a power supply voltage using the AC electrical signal obtained by conversion of the carrier wave with the antenna 203, and supplies the power supply voltage to each circuit.
• the demodulation circuit 205 demodulates the AC electrical signal, which has been obtained by conversion of the carrier wave with the antenna 203, and supplies the demodulated signal to the arithmetic processing circuit 201.
• the modulation circuit 206 based on a signal supplied from the arithmetic processing circuit 201, applies load modulation to the antenna 203.
• the reader/writer 207 receives the load modulation applied to the antenna 203 as a carrier wave. In addition, the reader/writer 207 transmits a carrier wave to the semiconductor device 200 capable of radio communication. Note that a carrier wave is an electromagnetic wave transmitted to or received by the reader/writer 207, and the reader/writer 207 receives a carrier wave modulated by the modulation circuit 206.
• FIG 7A illustrates a structure in which all of the memory elements employ the memory elements of the invention
• the memory elements are not limited thereto.
• the memory circuit 202 may be mounted with a memory portion that uses the memory elements of the invention and stores a unique identification number of the semiconductor device and with another/other memory portion/portions.
• FIG 7A is a configuration example of the memory circuit 202 in which the memory elements of the invention are arranged in matrix.
• the memory circuit 202 includes a memory cell array 1023 in which memory cells 1021 are arranged in matrix; a bit line driver circuit 1024 having a column decoder 1025, a reading circuit 1026, and a selector 1027; a word line driver circuit 1029 having a row decoder 1030 and a level shifter 1031; and an interface 1028 which has a writing circuit and the like and communicates with the outside.
• the configuration of the memory circuit 202 illustrated herein is only exemplary and, thus, the memory circuit 202 may have other circuits such as a sense amplifier, an output circuit, and/or a buffer. It is also possible to provide the writing circuit in the bit line driver circuit.
• Each memory cell 1021 includes a first wiring which corresponds to a word line Wy (1 ⁇ y ⁇ n), a second wiring which corresponds to a bit line B x (1 ⁇ x ⁇ m), a
• TFT 1032 TFT 1032
• memory element 1033 TFT 1032
• Writing operation is performed by selecting the word line Wo of the memory cell 1021 and flowing a current through the bit line Bo. That is, it is acceptable as long as a memory cell to be written with data is selected by the word line W 0 and a voltage high enough to insulate the memory element 1033 is applied so that the memory element 1033 shifts from the first state to the second state. This voltage is assumed to be 10 V, for example.
• TFTs 502, 503, and 504 are turned off in order to prevent data from being written to memory elements 506, 507, and 508 of other memory cells.
• the word line W 1 and the bit line B 1 may be set at 0 V.
• the reading operation can be conducted by judging whether the memory element 1033 of the memory cell 1021 is in the first state, in which "1" is written, or in the second state, in which "0" is written. For example, a case will be described in which whether "0" or “1” is written to the memory cell 1021 is read out. The memory element 1033 is in the state in which "0" is written.
• the memory element 1033 is insulated.
• the word line Wo is selected to turn on the TFT 1032.
• a voltage higher than a predetermined voltage is applied to the bit line Bo with the TFT 1032 being in the on-state.
• the predetermined voltage is assumed to be 5 V.
• the memory element 1033 is in the second state, that is, if the memory element 1033 is insulated, the voltage of the bit line Bo is unchanged at 5 V without a current flowing through the grounded wiring within the memory cell 1021. In this way, whether "0" or "1" is written to the memory element 1033 can be judged by reading the voltage of the bit line.
• the memory element of the invention can be applied to a semiconductor device capable of radio communication.
• Embodiment Mode 3 The semiconductor device 200, which is capable of radio communication, fabricated based on Embodiment Mode 2 can be used for a variety of items and systems by utilizing its function of transmitting and receiving electromagnetic waves.
• Examples of items to which the semiconductor device 200 which is capable of radio communication can be applied are keys (see FIG. 8A), paper money, coins, securities, bearer bonds, documents (e.g., driver's licenses or resident's cards; see FIG 8B), books, containers (e.g., petri dishes; see FIG. 8C), packaging containers (e.g., wrapping paper or bottles; see FIGS. 8E and 8F), recording media (e.g., disks or video tapes), means of transportation (e.g., bicycles), personal accessories (e.g., bags or eyeglasses; see FIG.
• the semiconductor device 200 which is capable of radio communication, fabricated by applying the invention is fixed to items of a variety of forms, such as those above, by being attached to or embedded in a surface.
• a system refers to a goods management system, a system having an authentication function, a distribution system, or the like.
• a system can be made more sophisticated and multifunctional and can have higher added value.
• Embodiment Mode 4 This embodiment mode will describe a method of fabricating the island-like semiconductor film 102 of Embodiment Mode 1 with a substrate having an SOI structure with reference to FIGS. 9A and 9B, 1OA to 1OC, HA to HC, 12A and 12B,
• a supporting substrate 300 refers to an insulating substrate or a substrate having an insulating surface, and glass substrates (also referred to as "non-alkali glass substrates") that are used in the electronics industry, such as aluminosilicate glass substrates, aluminoborosilicate glass substrates, and barium borosilicate glass substrates, are used.
• glass substrates also referred to as "non-alkali glass substrates”
• a single-crystalline semiconductor layer is used for an LTSS (low-temperature single-crystalline semiconductor) layer 301, and single-crystalline silicon is typically used.
• a bonding layer 302 which has a smooth surface and forms a hydrophilic surface is provided.
• This bonding layer 302 is a layer which has a smooth surface and a hydrophilic surface.
• an insulating layer formed by a chemical reaction is preferable.
• an oxide semiconductor film formed by a thermal or chemical reaction is suitable. The main reason is that a film formed by a chemical reaction can ensure its surface smoothness.
• the bonding layer 302 which has a smooth surface and forms a hydrophilic surface is provided at a thickness of 0.2 to 500 nm. With this thickness, it is possible to smooth surface roughness of a surface on which a film is to be formed and also to ensure smoothness of a growing surface of the film.
• the bonding layer 302 may have a thickness of 0.1 to 1 nm.
• the bonding layer 302 is formed of silicon oxide that is deposited by chemical vapor deposition.
• a silicon oxide film fabricated by chemical vapor deposition using an organic silane gas is preferable.
• organic silane gases examples include silicon-containing compounds such as tetraethoxysilane (TEOS) (chemical formula: Si(OC 2 Hs) 4 ), tetramethylsilane (TMS) (chemical formula: Si(CH 3 ) 4 ), tetramethylcyclotetrasiloxane
• TEOS tetraethoxysilane
• TMS tetramethylsilane
• Si(CH 3 ) 4 tetramethylcyclotetrasiloxane
• TCTS octamethylcyclotetrasiloxane
• OCTS octamethylcyclotetrasiloxane
• HMDS hexamethyldisilazane
• SiH(OC 2 Hs) S triethoxysilane
• SiH(N(CH 3 ) 2 ) 3 trisdimethylaminosilane
• the bonding layer 302 is provided on the LTSS layer 301 side and located in contact with the surface of the supporting substrate 300, whereby a bond can be formed even at room temperature.
• the supporting substrate 300 and the LTSS layer 301 may be pressed against each other.
• the surfaces are cleaned. When the cleaned surface of the supporting substrate 300 and that of the bonding layer 302 are located in contact with each other, a bond is formed by an attracting force between the surfaces.
• the surface of the supporting substrate 300 be subjected to treatment for attaching a plurality of hydrophilic groups to the surface.
• the surface of the supporting substrate 300 it is preferable that the surface of the supporting substrate
• surfaces which are to form a bond may be cleaned by being irradiated with an ion beam obtained from an inert gas such as argon.
• an ion beam obtained from an inert gas such as argon.
• a bond between the supporting substrate 300 and the bonding layer 302 can be formed even at low temperature.
• a method of forming a bond after surface activation is preferably performed in vacuum because the surface needs to have a high degree of cleanness.
• the LTSS layer 301 is formed by slicing of a crystalline semiconductor substrate.
• the LTSS layer 301 can be formed by an ion implantation separation method in which ions of hydrogen or fluorine are implanted into the single-crystalline silicon substrate to a predetermined depth and then heat treatment is performed to separate a superficial single-crystalline silicon layer.
• LTSS layer 301 is 5 to 500 tun, preferably, 10 to 200 nm.
• FIG. 9B shows a structure in which the supporting substrate 300 is provided with a barrier layer 303 and the bonding layer 302.
• the barrier layer 303 By provision of the barrier layer 303, the LTSS layer 301 can be prevented from being contaminated by a mobile ion impurity like alkali metal or alkaline earth metal that is diffused from a glass substrate that is used as the supporting substrate 300.
• the bonding layer 302 is preferably provided.
• the barrier layer 303 which prevents impurity diffusion and the bonding layer 302 which ensures bonding strength that is, a plurality of layers with different functions over the supporting substrate 300
• the bonding layer 302 be provided also on the LTSS layer 301 side. That is, in bonding the LTSS layer 301 to the supporting substrate 300, it is preferable that one or both of surfaces that are to form a bond be provided with the bonding layer 302, whereby bonding strength can be increased.
• FIG 1OA shows a structure in which an insulating layer 304 is provided between the LTSS layer 301 and the bonding layer 302.
• the insulating layer 304 be a nitrogen-containing insulating layer.
• the insulating layer 304 can be formed by using a single film or a plurality of stacked films selected from a silicon nitride film, a silicon nitride film containing oxygen, and a silicon oxide film containing nitrogen.
• a stacked-layer film can be used which is obtained by stacking a silicon oxide film containing nitrogen and a silicon nitride film containing oxygen from the LTSS layer 301 side.
• the bonding layer 302 functions to form a bond with the supporting substrate 300, whereas the insulating layer 304 prevents the LTSS layer 301 from being contaminated by an impurity.
• the silicon oxide film containing nitrogen here means a film that contains more oxygen than nitrogen and includes oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 55 at.% to 65 at.%, 1 at.% to 20 at.%, 25 at.% to 35 at.%, and 0.1 at.% to 10 at.%, respectively.
• the silicon nitride film containing oxygen means a film that contains more nitrogen than oxygen and includes oxygen, nitrogen, silicon, and hydrogen at concentrations ranging from 15 at.% to 30 at.%, 20 at.% to 35 at.%, 25 at.% to 35 at.%, and 15 at.% to 25 at.%, respectively.
• FIG 1OC shows another structure in which the supporting substrate 300 is provided with the bonding layer 302. Between the supporting substrate 300 and the bonding layer 302, the barrier layer 303 is provided. [0088]
• the barrier layer 303 is formed of a single layer or a plurality of layers.
• a silicon nitride film or a silicon nitride film containing oxygen which is highly effective in blocking ions of sodium or the like is used as a first layer, and a silicon oxide film or a silicon oxide film containing nitrogen is provided thereover as a second layer.
• the first layer of the barrier layer 303 is an insulating film and is a dense film with a purpose to prevent impurity diffusion, whereas one of purposes of the second layer is to relax stress so that internal stress of the film of the first layer does not affect the upper layer.
• the bonding layer 302 is formed to fix the supporting substrate 300 and the LTSS layer 301.
• Methods of fabricating the substrates with an SOI structure shown in FIGS. 9A and 9B, and 1OA to 1OC are described with reference to FIGS. HA to HC, 12A and 12B, 13Ato 13C, 14Ato 14C, 15Aand 15B, and 16Ato 16C.
• Ions that are accelerated by an electric field are implanted to a predetermined depth from a cleaned surface of a semiconductor substrate 306, thereby forming a separation layer 307 (see FIG HA).
• the depth at which the separation layer 307 is formed in the semiconductor substrate 306 is controlled by ion accelerating energy and ion incident angle.
• the separation layer 307 is formed in a region at a depth close to the average penetration depth of the ions from the surface of the semiconductor substrate 306.
• the thickness of an LTSS layer is 5 to 500 nm, preferably, 10 to 200 nm, and the accelerating voltage at the time of implanting ions is determined in consideration of such a thickness.
• Ion implantation is preferably performed using an ion doping apparatus. That is, doping is used, by which a plurality of ion species that is generated from a plasma of a source gas is implanted without any mass separation being performed.
• Ion doping may be performed with an accelerating voltage of 10 to 100 keV, preferably, 30 to 80 keV, at a dosage of 1 x 10 16 to 4 x 10 16 /cm 2 , and with a beam current density of 2 ⁇ A/cm 2 or more, preferably, 5 ⁇ A/cm or more, more preferably, 10 ⁇ A/cm or more.
• the hydrogen ions preferably include H + , H 2 + , and H 3 + ions with a high proportion of H 3 + ions.
• the hydrogen ions when the hydrogen ions are made to include H + , H 2 + , and H 3 + ions with a high proportion of H 3 + ions, implantation efficiency can be increased and implantation time can be shortened. Accordingly, the separation layer 307 formed in the semiconductor substrate 306 can be made to contain hydrogen at 1 x 10 20 /cm 3
• a crystal structure is disordered and microvoids are formed, whereby the separation layer 307 can be made to have a porous structure.
• heat treatment at relatively low temperature a change occurs in the volume of the microvoids formed in the separation layer 307, which enables cleavage to occur along the separation layer 307 and enables a thin LTSS layer to be formed.
• deuterium or an inert gas such as helium, as well as hydrogen can be selected.
• an ion beam with a high proportion of He + ions can be obtained.
• implantation of such ions into the semiconductor substrate 306 microvoids can be formed and the separation layer 307 similar to that described above can be formed in the semiconductor substrate 306.
• a surface, through which ions are implanted may be provided with a dense film.
• a protective film against ion implantation which is made of a silicon nitride film, a silicon nitride film containing oxygen, or the like, may be provided at a thickness of 50 to 200 nm.
• a silicon oxide film is formed as a bonding layer 302 on a surface which is to form a bond with a supporting substrate 300 (see FIG HB).
• the thickness of the silicon oxide film may be 10 to 200 nm, preferably, 10 to 100 nm, more preferably, 20 to 50 nm.
• silicon oxide film a silicon oxide film formed by chemical vapor deposition using an organic silane gas as described above is preferable.
• a silicon oxide film formed by chemical vapor deposition using a silane gas can be used.
• Film formation by chemical vapor deposition is performed at a temperature, for example, 350 0 C or lower, at which degassing of the separation layer 307 that is formed in a single-crystalline semiconductor substrate does not occur.
• heat treatment for separation of an LTSS layer from a single-crystalline or polycrystalline semiconductor substrate is performed at a temperature higher than the temperature at which the silicon oxide film is formed.
• a bond is formed by making the supporting substrate 300 and the surface of the semiconductor substrate 306 where the bonding layer 302 is formed face each other and be in contact with each other (see FIG. HC). A surface which is to form a bond is cleaned sufficiently. Then, the supporting substrate 300 and the bonding layer 302 are located in contact with each other, whereby a bond is formed. It can be considered that
• Van der Waals forces act at the initial stage of bonding and that a strong bond due to hydrogen bonding can be formed by pressure bonding of the supporting substrate 300 and the semiconductor substrate 306.
• a surface may be activated.
• the surface which is to form a bond is irradiated with an atomic beam or an ion beam.
• an atomic beam or an ion beam an inert gas neutral atom beam or inert gas ion beam of argon or the like can be used.
• plasma irradiation or radical treatment is performed. Such surface treatment makes it possible to increase bonding strength between different kinds of materials even at a temperature of 200 to
• First heat treatment is performed in a state where the semiconductor substrate
• the first heat treatment is preferably performed at a temperature equal to or higher than the temperature at which the bonding layer 302 is formed, preferably at equal to or higher than 400 0 C to lower than 600 0 C.
• a change occurs in the volume of the microvoids formed in the separation layer 307, which allows a semiconductor layer to be cleaved along the separation layer 307. Because the bonding layer 302 is bonded to the supporting substrate 300, an LTSS layer 301 having the same crystallinity as that of the semiconductor substrate 306 is fixed to the supporting substrate 300 in this mode.
• second heat treatment is performed in a state where the LTSS layer 301 is bonded to the supporting substrate 300 (see FIG 12B). It is preferable that the second heat treatment be performed at a temperature higher than the temperature of the first heat treatment and lower than the strain point of the supporting substrate 300. Alternatively, even if the first heat treatment and the second heat treatment are performed at the same temperature, it is preferable that the second heat treatment be performed for a longer period of treatment time.
• the heat treatment may be performed so that the supporting substrate 300 and/or the LTSS layer 301 are/is heated by thermal conduction heating, convection heating, radiation heating, or the like.
• a heat treatment apparatus an electrically heated oven, a lamp annealing furnace, or the like can be used.
• the second heat treatment may be performed with multilevel changes of temperature.
• a rapid thermal annealing (RTA) apparatus may be used. If the heat treatment is performed using an RTA apparatus, heating up to near a substrate strain point or a temperature slightly higher than the substrate strain point is also possible.
• the second heat treatment Through the second heat treatment, residual stress of the LTSS layer 301 can be relaxed. That is, the second heat treatment can relax thermal distortion caused by a difference in coefficient of expansion between the supporting substrate 300 and the LTSS layer 301. In addition, the second heat treatment is effective in recovering the crystallinity of the LTSS layer 301, which is impaired by ion implantation. Furthermore, the second heat treatment is also effective in recovering damage of the
• LTSS layer 301 which is caused when the semiconductor substrate 306 is bonded to the supporting substrate 300 and then divided by the first heat treatment. Moreover, by the first heat treatment and the second heat treatment, hydrogen bonds can be changed into stronger covalent bonds.
• a chemical mechanical polishing (CMP) process may be performed.
• the CMP process can be performed after the first heat treatment or the second heat treatment. Note that, when the CMP process is performed before the second heat treatment, it is possible to planarize the surface of the LTSS layer 301 by the CMP process and recover a damaged layer on the surface which is formed due to the CMP process by the second heat treatment.
• a crystalline semiconductor layer with excellent crystallinity can be provided over a supporting substrate which is weak against heat, such as a glass substrate.
• FIGS. 15Aand 15B A method of forming the substrate with an SOI structure shown in FIG 9B is described with reference to FIGS. 15Aand 15B.
• a separation layer 307 is formed in a semiconductor substrate 306, and a bonding layer 302 is formed on a surface of the semiconductor substrate 306 which is to form a bond with a supporting substrate 300.
• the supporting substrate 300 provided with a barrier layer 303 and a bonding layer 302 and the bonding layer 302 of the semiconductor substrate 306 are located in contact with each other, thereby forming a bond (see FIG. 15A).
• first heat treatment is performed.
• the first heat treatment is preferably performed at a temperature equal to or higher than the temperature at which the bonding layer 302 is formed, preferably at equal to or higher than 400 0 C to lower than 600 0 C. Accordingly, a change occurs in the volume of the microvoids formed in the separation layer 307, which can cause cleavage in the semiconductor substrate 306.
• an LTSS layer 301 having the same crystallinity as that of the semiconductor substrate 306 is formed (see FIG 15B).
• second heat treatment is performed in a state where the LTSS layer 301 is bonded to the supporting substrate 300. It is preferable that the second heat treatment be performed at a temperature higher than the temperature of the first heat treatment and lower than the strain point of the supporting substrate 300. Alternatively, even if the first heat treatment and the second heat treatment are performed at the same temperature, it is preferable that the second heat treatment be performed for a longer period of treatment time.
• the heat treatment may be performed so that the supporting substrate 300 and/or the LTSS layer 301 are/is heated by thermal conduction heating, convection heating, radiation heating, or the like. Through the second heat treatment, residual stress of the LTSS layer 301 can be relaxed, and the second heat treatment is also effective in recovering the damage of the LTSS layer 301 caused by division through the first heat treatment.
• a separation layer 307 is formed in a semiconductor substrate 306.
• an insulating layer 304 is formed on the surface of the semiconductor substrate 306. It is preferable that the insulating layer 304 be a nitrogen-containing insulating layer.
• the insulating layer 304 can be formed using a single film or a plurality of stacked films selected from a silicon nitride film, a silicon nitride film containing oxygen, and a silicon oxide film containing nitrogen.
• a silicon oxide film is formed as a bonding layer 302 over the insulating layer 304 (see FIG 16A).
• a bond is formed by making a supporting substrate 300 and the surface of the semiconductor substrate 306 where the bonding layer 302 is formed face each other and be in contact with each other (see FIG. 16B).
• first heat treatment is performed.
• the first heat treatment is preferably performed at a temperature equal to or higher than the temperature at which the bonding layer 302 is formed, preferably at equal to or higher than 400 0 C to lower than 600 0 C. Accordingly, a change occurs in the volume of the microvoids formed in the separation layer 307, which can cause cleavage in the semiconductor substrate 306.
• an LTSS layer 301 having the same crystallinity as that of the semiconductor substrate 306 is formed (see FIG. 16C).
• second heat treatment is performed in a state where the LTSS layer 301 is bonded to the supporting substrate 300. It is preferable that the second heat treatment be performed at a temperature higher than the temperature of the first heat treatment and lower than the strain point of the supporting substrate 300. Alternatively, even if the first heat treatment and the second heat treatment are performed at the same temperature, it is preferable that the second heat treatment be performed for a longer period of treatment time.
• the heat treatment may be performed so that the supporting substrate 300 and/or the LTSS layer 301 are/is heated by thermal conduction heating, convection heating, radiation heating, or the like. Through the second heat treatment, residual stress of the LTSS layer 301 can be relaxed, and the second heat treatment is also effective in recovering the damage of the LTSS layer 301 caused by division through the first heat treatment.
• the insulating layer 304 When the insulating layer 304 is formed over the semiconductor substrate 306 as shown in FIGS. 16 A to 16C, the insulating layer 304 prevents an impurity from being mixed into the LTSS layer 301; accordingly, the LTSS layer 301 can be prevented from being contaminated. [0123]
• FIGS. 13A to 13C show steps of providing a bonding layer on a supporting substrate side and fabricating a substrate with an SOI structure having an LTSS layer.
• ions that are accelerated by an electric field are implanted into a semiconductor substrate 306, which is provided with a silicon oxide layer 305, to a predetermined depth, thereby forming a separation layer 307 (see FIG. 13A).
• the silicon oxide layer 305 may be formed over the semiconductor substrate 306 by sputtering or CVD, or when the semiconductor substrate 306 is a single-crystalline silicon substrate, the silicon oxide layer 305 may be formed by thermal oxidation of the semiconductor substrate 306.
• the semiconductor substrate 306 is a single-crystalline silicon substrate, and the silicon oxide layer 305 is formed by thermal oxidation of the single-crystalline silicon substrate.
• the implantation of ions into the semiconductor substrate 306 is performed in a similar manner to the case of FIG. HA.
• the silicon oxide layer 305 on the surface of the semiconductor substrate 306, the surface can be prevented from being damaged by ion implantation and losing its planarity.
• a supporting substrate 300 provided with a barrier layer 303 and a bonding layer 302 and the surface of the semiconductor substrate 306 where the silicon oxide layer 305 is formed are located in contact with each other, thereby forming a bond (see FIG 13B).
• first heat treatment is performed.
• the first heat treatment is preferably performed at a temperature equal to or higher than the temperature at which the bonding layer 302 is formed, preferably at equal to or higher than 400 0 C to lower than 600 0 C. Accordingly, a change occurs in the volume of the microvoids formed in the separation layer 307, which can cause cleavage in the semiconductor substrate 306.
• an LTSS layer 301 having the same crystallinity as that of the semiconductor substrate 306 is formed (see FIG 13C).
• second heat treatment is performed in a state where the LTSS layer 301 is bonded to the supporting substrate 300. It is preferable that the second heat treatment be performed at a temperature higher than the temperature of the first heat treatment and lower than the strain point of the supporting substrate 300. Alternatively, even if the first heat treatment and the second heat treatment are performed at the same temperature, it is preferable that the second heat treatment be performed for a longer period of treatment time.
• the heat treatment may be performed so that the supporting substrate 300 and/or the LTSS layer 301 are/is heated by thermal conduction heating, convection heating, radiation heating, or the like.
• the second heat treatment Through the second heat treatment, residual stress of the LTSS layer 301 can be relaxed, and the second heat treatment is also effective in recovering the damage of the LTSS layer 301 caused by division through the first heat treatment. [0129] hi the above-described manner, the SOI substrate shown in FIG 1OB is formed. [0130]
• FIGS. 14A to 14C show another example in the case where a bonding layer is provided on a supporting substrate side to bond an LTSS layer.
• a separation layer 307 is formed in a semiconductor substrate 306 (see FIG 14A).
• the implantation of ions for formation of the separation layer 307 is performed using an ion doping apparatus, hi this step, the semiconductor substrate 306 is irradiated with ions with different masses which are accelerated by a high electric field.
• a silicon oxide layer 305 be provided as a protective film because the planarity of the surface of the semiconductor substrate 306 may be impaired by ion irradiation.
• the silicon oxide layer 305 may be formed by thermal oxidation or by using a chemical oxide.
• a chemical oxide can be formed by immersion of the semiconductor substrate 306 in an oxidizing chemical solution. For example, by treatment of the semiconductor substrate 306 with an ozone-containing aqueous solution, a chemical oxide is formed on the surface.
• a silicon oxide film containing nitrogen or a silicon nitride film containing oxygen formed by plasma CVD, or a silicon oxide film formed using TEOS may be used.
• a supporting substrate 300 be provided with a barrier layer
• the barrier layer 303 is formed of a single layer or a plurality of layers. For example, a silicon nitride film or a silicon nitride film containing oxygen which is highly effective in blocking ions of sodium or the like is used as a first layer, and a silicon oxide film or a silicon oxide film containing nitrogen is provided thereover as a second layer. [0136]
• the first layer of the barrier layer 303 is an insulating film and is a dense film with a purpose to prevent impurity diffusion, whereas one of purposes of the second layer is to relax stress so that internal stress of the film of the first layer does not affect the upper layer.
• the supporting substrate 300 provided with a bonding layer 302 over the barrier layer 303 and the semiconductor substrate 306 are bonded together (see FIG 14B).
• the surface of the semiconductor substrate 306 is exposed by removal of the silicon oxide layer 305, which has been provided as a protective film, with a hydrofluoric acid.
• the outermost surface of the semiconductor substrate 306 may be in a state where the surface is terminated with hydrogen by treatment with a hydrofluoric acid solution.
• hydrogen bonds are formed by surface-terminating hydrogen, and a favorable bond can be formed.
• irradiation with ions of an inert gas may be performed so that dangling bonds are exposed on the outermost surface of the semiconductor substrate 306, and a bond may be formed in vacuum.
• first heat treatment is performed.
• the first heat treatment is preferably performed at a temperature equal to or higher than the temperature at which the bonding layer 302 is formed, preferably, at equal to or higher than 400 0 C to lower than 600 0 C. Accordingly, a change occurs in the volume of the microvoids formed in the separation layer 307, which can cause cleavage in the semiconductor substrate 306.
• an LTSS layer 301 having the same crystallinity as that of the semiconductor substrate 306 is formed (see FIG 14C).
• second heat treatment is performed in a state where the LTSS layer 301 is bonded to the supporting substrate 300. It is preferable that the second heat treatment be performed at a temperature higher than the temperature of the first heat treatment and lower than the strain point of the supporting substrate 300. Alternatively, even if the first heat treatment and the second heat treatment are performed at the same temperature, it is preferable that the second heat treatment be performed for a longer period of treatment time.
• the heat treatment may be performed so that the supporting substrate 300 and/or the LTSS layer 301 are/is heated by thermal conduction heating, convection heating, radiation heating, or the like. Through the second heat treatment, residual stress of the LTSS layer 301 can be relaxed, and the second heat treatment is also effective in recovering the damage of the LTSS layer 301 caused by division through the first heat treatment.
• the LTSS layer 301 which has a strong bonding force in a bonding portion can be obtained.
• the supporting substrate 300 it is possible to use any of a variety of glass substrates that are used in the electronics industry and that are referred to as non-alkali glass substrates, such as aluminosilicate glass substrates, aluminoborosilicate glass substrates, and barium borosilicate glass substrates.
• the island-like semiconductor film 102 described in Embodiment Mode 1 can be obtained by patterning the LTSS layer 301 into an island shape.
• the LTSS layer 301 obtained in this embodiment mode is a single-crystalline semiconductor layer; thus, a semiconductor device with high response speed can be fabricated.

Landscapes

• Semiconductor Memories (AREA)
• Thin Film Transistor (AREA)
• Non-Volatile Memory (AREA)
• Recrystallisation Techniques (AREA)

Priority Applications (2)

Applications Claiming Priority (2)

Publications (1)

Family

ID=40135566

Family Applications (1)

Country Status (5)

Families Citing this family (15)

Citations (6)

Family Cites Families (28)

• 2008
  • 2008-06-12 KR KR1020107001655A patent/KR101520284B1/ko not_active Expired - Fee Related
  • 2008-06-12 WO PCT/JP2008/061167 patent/WO2009001733A1/en not_active Ceased
  • 2008-06-12 CN CN200880021052XA patent/CN101681885B/zh not_active Expired - Fee Related
  • 2008-06-16 JP JP2008156353A patent/JP5384038B2/ja active Active
  • 2008-06-20 US US12/143,472 patent/US8319269B2/en not_active Expired - Fee Related

Patent Citations (6)

Also Published As

Similar Documents

Legal Events