JP4909552B2 - 電荷保持特性に優れた不揮発性半導体記憶素子の製造方法 - Google Patents
電荷保持特性に優れた不揮発性半導体記憶素子の製造方法 Download PDFInfo
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- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/401—Multistep manufacturing processes
- H01L29/4011—Multistep manufacturing processes for data storage electrodes
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L29/40—Electrodes ; Multistep manufacturing processes therefor
- H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
- H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
- H01L29/42312—Gate electrodes for field effect devices
- H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
- H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
- H01L29/42324—Gate electrodes for transistors with a floating gate
- H01L29/42332—Gate electrodes for transistors with a floating gate with the floating gate formed by two or more non connected parts, e.g. multi-particles flating gate
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- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
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- H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
- H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
- H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
- H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
- H01L21/02181—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing hafnium, e.g. HfO2
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- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/31645—Deposition of Hafnium oxides, e.g. HfO2
Description
図1は、本発明の実施の形態に係る不揮発性半導体記憶素子の断面構造の一例を概念的に示す説明図である。図1において、不揮発性半導体記憶素子100は、半導体基板1上に形成され、素子分離2によって素子分離されている。なお、図1での半導体基板1はp型の半導体基板であり、素子分離2はSTI(Shallow Trench Isolation)技術を用いて形成されたものである。
「例1」
図3は、例1に係る不揮発性半導体記憶素子の製造方法を説明するための工程フロー図である。本発明の例では、素子選択トランジスタや信号増幅回路などの周辺回路に関わる部位の製造工程は省略し、記憶素子の製造に関わる製造工程のみを示す。
図17は、例2に係る不揮発性半導体記憶素子の断面構造の一例を概念的に示す説明図である。まず、例1において説明したものと同様に、p型不純物がドープされた単結晶Siからなる半導体基板1の表面に、素子分離2を形成し(S101。図4参照)、しきい値電圧調節のためのイオン注入を行った(S102。図5参照)。
図24は、本発明の例3に係る不揮発性半導体記憶素子の断面構造の一例を概念的に示す説明図である。まず、本発明の例1および例2において説明したものと同様に、p型不純物がドープされた単結晶Siからなる半導体基板1の表面に、STI型の素子分離2を形成し(S101。図4参照)、しきい値電圧調節のためのイオン注入を行った(S102)。
次に、例1において説明したものと同様に、保護膜としてNSGとPSGを堆積し(S116)、コンタクトホールを形成し(S117)、Al配線を形成し(S118)、Al配線とSi基板との電気的接触を良好にすべくH2アニールを行った(S119)。
2 素子分離
3、23、33 トンネル絶縁膜
4、24、34 電荷保持層
4a1、24a1、34a1 超微粒子
4b 母相絶縁体
4c、5b、34c 酸素欠乏型欠陥
4d、5c、34d 未結合手
4e、5d OH基
5、5a、25、35 ゲート絶縁膜
6 制御ゲート
7 ソース領域
7a、8a 浅い接合領域
7b、8b コンタクト領域
8 ドレイン領域
9 サイドウォール
10 ハローイオン注入領域
21 スクリーン酸化膜
24f 酸化部位
34b SiO2母相絶縁体
100、200、300 不揮発性半導体記憶素子
Claims (6)
- 酸化物生成に係るギブスの生成自由エネルギーが、1気圧かつ摂氏0度から摂氏1200度の範囲内において、同一温度条件でのSiの酸化物生成に係るギブスの生成自由エネルギーよりも高い元素である難酸化性元素で構成される難酸化性物質と、
酸化物生成に係るギブスの生成自由エネルギーが、1気圧かつ摂氏0度から摂氏1200度の範囲内において、同一温度条件でのSiの酸化物生成に係るギブスの生成自由エネルギーよりも低い元素、およびSiからなる易酸化性元素で構成される易酸化性物質の酸化物と、が混在または積層した構造を有する電荷保持特性に優れた不揮発性半導体記憶素子の製造方法において、
前記難酸化性物質からなる部分と、前記易酸化性物質の酸化物からなる部分とが、いずれも物理的形成法を用いて形成され、
酸化剤として機能する酸化用気体と還元剤として機能する還元用気体との混合気体中で、摂氏0度から摂氏1200度までの温度範囲内において前記難酸化性物質が還元されかつ前記易酸化性物質の酸化物が酸化されるように、前記酸化用気体と前記還元用気体との混合比および温度を制御して熱処理を行うことを特徴とする電荷保持特性に優れた不揮発性半導体記憶素子の製造方法。 - 酸化物生成に係るギブスの生成自由エネルギーが、1気圧かつ摂氏0度から摂氏1200度の範囲内において、同一温度条件でのSiの酸化物生成に係るギブスの生成自由エネルギーよりも高い元素である難酸化性元素で構成される難酸化性物質と、
酸化物生成に係るギブスの生成自由エネルギーが、1気圧かつ摂氏0度から摂氏1200度の範囲内において、同一温度条件でのSiの酸化物生成に係るギブスの生成自由エネルギーよりも低い元素、およびSiからなる易酸化性元素で構成される易酸化性物質の酸化物と、が混在または積層した構造を有する電荷保持特性に優れた不揮発性半導体記憶素子の製造方法において、
前記難酸化性物質からなる部分が物理的形成法を用いて形成され、前記易酸化性物質の酸化物からなる部分が化学的形成法を用いて形成され、
酸化剤として機能する酸化用気体と還元剤として機能する還元用気体との混合気体中で、摂氏0度から摂氏1200度までの温度範囲内において前記難酸化性物質が還元されかつ前記易酸化性物質の酸化物が酸化されるように、前記酸化用気体と前記還元用気体との混合比および温度を制御して熱処理を行うことを特徴とする電荷保持特性に優れた不揮発性半導体記憶素子の製造方法。 - 酸化物生成に係るギブスの生成自由エネルギーが、1気圧かつ摂氏0度から摂氏1200度の範囲内において、同一温度条件でのSiの酸化物生成に係るギブスの生成自由エネルギーよりも高い元素である難酸化性元素で構成される難酸化性物質と、
酸化物生成に係るギブスの生成自由エネルギーが、1気圧かつ摂氏0度から摂氏1200度の範囲内において、同一温度条件でのSiの酸化物生成に係るギブスの生成自由エネルギーよりも低い元素、およびSiからなる易酸化性元素で構成される易酸化性物質の酸化物と、が混在または積層した構造を有する電荷保持特性に優れた不揮発性半導体記憶素子の製造方法において、
前記難酸化性物質の部分が、前記難酸化性物質と第1の前記易酸化性物質の酸化物とが混在または積層する暫定形成層を物理的形成法を用いて形成した後に、前記暫定形成層中の第1の前記易酸化性物質の酸化物を選択的に除去して形成され、
前記易酸化性物質の酸化物の部分が、前記暫定形成層中の第1の前記易酸化性物質の酸化物が選択的に除去された後に、物理的形成法または化学的形成法を用いて、第1の前記易酸化性物質の酸化物と同一または異なる第2の前記易酸化性物質の酸化物を堆積することによって形成され、
酸化剤として機能する酸化用気体と還元剤として機能する還元用気体との混合気体中で、摂氏0度から摂氏1200度までの温度範囲内において前記難酸化性物質が還元されかつ第2の前記易酸化性物質の酸化物が酸化されるように、前記酸化用気体と前記還元用気体との混合比および温度を制御して熱処理を行うことを特徴とする電荷保持特性に優れた不揮発性半導体記憶素子の製造方法。 - 前記酸化用気体が、摂氏0度から摂氏1200度の範囲内で、前記易酸化性物質との酸化反応に係るギブスの自由エネルギーの変化量が負となる気体であり、
前記還元用気体が、摂氏0度から摂氏1200度の範囲内で、前記難酸化性物質の酸化物との還元反応に係るギブスの自由エネルギーの変化量が負かつ、前記易酸化性物質の酸化物との還元反応に係るギブスの自由エネルギーの変化量が正となる気体である請求項1から3までのいずれか1項に記載の電荷保持特性に優れた不揮発性半導体記憶素子の製造方法。 - 前記酸化用気体がH2Oを含み、前記還元用気体がH2を含む請求項1から4までのいずれか1項に記載の電荷保持特性に優れた不揮発性半導体記憶素子の製造方法。
- 前記酸化用気体と前記還元用気体との混合気体中で、前記難酸化性物質が還元されかつ前記易酸化性物質の酸化物が酸化されるように前記熱処理を行った後に、所定の不活性雰囲気中または減圧中でさらに熱処理を行う請求項1から5までのいずれか1項に記載の電荷保持特性に優れた不揮発性半導体記憶素子の製造方法。
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TW095133678A TWI390677B (zh) | 2005-09-12 | 2006-09-12 | And a method of manufacturing a nonvolatile semiconductor memory device excellent in charge retention characteristics |
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