WO2021046734A1 - 开关元件和显示面板 - Google Patents

开关元件和显示面板 Download PDF

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Publication number
WO2021046734A1
WO2021046734A1 PCT/CN2019/105266 CN2019105266W WO2021046734A1 WO 2021046734 A1 WO2021046734 A1 WO 2021046734A1 CN 2019105266 W CN2019105266 W CN 2019105266W WO 2021046734 A1 WO2021046734 A1 WO 2021046734A1
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Prior art keywords
layer
electrode
substrate
switching element
source electrode
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PCT/CN2019/105266
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English (en)
French (fr)
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蔡奇哲
张怡欣
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咸阳彩虹光电科技有限公司
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Priority to PCT/CN2019/105266 priority Critical patent/WO2021046734A1/zh
Publication of WO2021046734A1 publication Critical patent/WO2021046734A1/zh

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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film

Definitions

  • This application relates to the field of electronic devices and display technologies, and in particular to a switching element and a display panel.
  • Oxide TFTs with ⁇ -IGZO (amorphous indium gallium zinc oxide) as the active layer have the characteristics of high mobility, good uniformity in a large area, and low manufacturing process temperature. They are used in the switching and driving of flat panel displays. Outstanding performance in terms of performance has become the current TFT research hotspot.
  • the active layer of ⁇ -IGZO is very sensitive to the process and environment. In the process of preparing oxide thin film transistors, its structure, the preparation conditions of each layer of film, photolithography, etching technology, etc. will all affect the type of defects in the active layer and its The density of states and the density of charge defect states at the interface between the active layer and the insulating layer.
  • Common oxide thin film transistor structures include Back Channel Etching (BCE) thin film transistors, Etch Stop Layer (ESL) thin film transistors, and Self-Align Type Top-Gate.
  • BCE Back Channel Etching
  • ESL Etch Stop Layer
  • Type thin film transistor Compared with ESL-type thin-film transistors, BCE-type thin-film transistors have fewer masks and low cost.
  • the active layer is in direct contact with the source and drain, the etching process to form the source and drain will damage the active layer, thereby affecting the stability of the thin film transistor
  • the active layer of the BCE thin film transistor is close to the ambient atmosphere.
  • the active layer In order to avoid the influence of environmental factors on the active layer, the thickness of the passivation layer needs to be increased, but this is not conducive to the miniaturization of the device; in addition, the active layer generally uses sputtering It is formed by a deposition method, which causes unevenness on the surface of the active layer, which increases the contact resistance between the source and drain electrodes and the active layer and reduces the mobility.
  • the gate insulating layer is a low-temperature process, hydrogen (H) in the gate insulating layer easily diffuses into the channel region of the active layer to make it a conductor, which reduces the stability of the device .
  • the embodiments of the present application provide a switching device such as an oxide thin film transistor to achieve the technical effect of improving the stability of the device.
  • a switching element provided by an embodiment of the present application includes: a substrate and a gate electrode, a gate insulating layer, a multilayer structure, a source electrode, a drain electrode, and a passivation layer disposed on the substrate; wherein, the The multilayer structure includes an active layer and an interface layer located on the side of the active layer away from the substrate, the active layer includes an oxide semiconductor material, and the interface layer includes a polyhydroxy transition metal complex; the gate The insulating layer is located on one side of the multilayer structure, and the gate electrode is located on the side of the gate insulating layer away from the multilayer structure; the source electrode and the drain electrode are located far from the multilayer structure.
  • One side of the substrate is electrically connected to the multilayer structure; and the passivation layer covers a side of the source electrode and the drain electrode away from the interface layer.
  • the polyhydroxy transition metal complex has a transition metal as a core and a hydroxyl group as a ligand.
  • the thickness of the interface layer is several nanometers (nm), for example, in the range of 1 nm-10 nm.
  • the oxide semiconductor material is indium gallium zinc oxide
  • the base includes a semiconductor substrate and a buffer layer formed on the semiconductor substrate.
  • the gate electrode is located between the gate insulating layer and the substrate, the active layer is located between the interface layer and the gate insulating layer, and the source electrode and The drain electrode is located between the passivation layer and the interface layer.
  • the interface layer includes: a peripheral portion sandwiched between the source electrode and the drain electrode and the active layer, and a peripheral portion located between the source electrode and the drain electrode. And sandwiched between the passivation layer and the active layer.
  • the thickness of the peripheral portion is greater than the thickness of the middle portion.
  • the interface layer includes portions sandwiched between the source electrode and the drain electrode and the active layer, and the active layer is located between the source electrode and the active layer. The area between the drain electrodes is not provided with the interface layer.
  • the active layer is located between the interface layer and the substrate
  • the gate insulating layer is located between the gate electrode and the interface layer
  • the switching element further includes a layer
  • the interlayer insulating layer is located on the side of the interface layer away from the substrate and covers the gate electrode and the gate insulating layer, and the source electrode and the drain electrode are located between the layers
  • the insulating layer is away from the side of the interface layer and penetrates the interlayer insulating layer to form an electrical connection with the active layer
  • the passivation layer is located between the source electrode, the drain electrode and the layer
  • the insulating layer is away from the side of the interface layer.
  • the interface layer includes: a middle portion located directly under the gate electrode and peripheral portions located on both sides of the gate electrode; the source electrode and the drain electrode pass through the The peripheral part is electrically connected to the active layer.
  • the thickness of the middle portion is greater than the thickness of the peripheral portion.
  • the source electrode and the drain electrode respectively contact the active layer to form an electrical connection.
  • an embodiment of the present application also provides a display panel, including: an array substrate, including an active switch array layer and a pixel electrode layer, wherein the active switch array layer includes a plurality of switching elements of any of the aforementioned types ,
  • the pixel electrode layer includes a plurality of pixel electrodes arranged in rows and columns, and each of the pixel electrodes is electrically connected to a corresponding switching element in the active switch array layer; an opposite substrate; and a display medium layer sandwiched between Between the array substrate and the opposite substrate.
  • the display medium layer includes an organic light-emitting material layer
  • the pixel electrode is an anode of a light-emitting diode
  • the counter substrate includes a cathode of the light-emitting diode
  • the display medium layer includes a liquid crystal material layer
  • the opposite substrate includes a common electrode layer
  • this embodiment introduces the interface layer on the upper surface of the active layer of the switching element, and its hydroxyl-based defect repair effect can improve the active layer.
  • the corrosion resistance and compactness of the surface based on the fact that when the thickness of the interface layer is a few nm, the metal ions can diffuse through the tunneling effect so that the contact work function of the active layer and the source electrode and the drain electrode may not be affected
  • the interface layer located between the active layer and the gate insulating layer can inhibit H from diffusing into the channel region of the active layer to make it a conductor; therefore, this embodiment does not increase the photomask
  • the device stability of switching elements such as back channel etched thin film transistors or self-aligned top gate thin film transistors is improved.
  • the quality of the display panel using the switching element can also be improved correspondingly.
  • FIG. 1 is a schematic cross-sectional structure diagram of a switching element according to the first embodiment of the application.
  • FIG. 2 is a schematic cross-sectional structure diagram of the switching element shown in FIG. 1 before the source electrode and the drain electrode are formed.
  • FIG. 3 is a schematic cross-sectional structure diagram of another switching element according to the first embodiment of the application.
  • FIG. 4 is a schematic cross-sectional structure diagram of still another switching element according to the first embodiment of the application.
  • FIG. 5 is a schematic cross-sectional structure diagram of a switching element according to a second embodiment of the application.
  • FIG. 6 is a schematic diagram of a cross-sectional structure of the switching element shown in FIG. 5 before forming a gate insulating layer and a gate electrode.
  • FIG. 7 is a schematic cross-sectional structure diagram of another switching element according to the second embodiment of the application.
  • FIG. 8 is a schematic cross-sectional structure diagram of still another switching element according to the second embodiment of the application.
  • FIG. 9 is a schematic structural diagram of a display panel according to the third embodiment of the application.
  • a switching element 10 provided by the first embodiment of the present application is, for example, a back-channel etched oxide thin film transistor, and includes a substrate 11, and a gate electrode GE and a gate insulating substrate 11 disposed on the substrate 11.
  • the layer 13, the multilayer structure, the source electrode SE, the drain electrode DE and the passivation layer 19; and the multilayer structure includes an active layer 15 and an interface layer 17 located on the side of the active layer 15 away from the substrate 11.
  • the gate insulating layer 13 is located on one side of the multilayer structure, and the gate electrode GE is located on the side of the gate insulating layer 13 away from the multilayer structure, so that the gate electrode GE is located on the side of the multilayer structure.
  • the active layer 15 is specifically located between the interface layer 17 and the gate insulating layer 13.
  • the source electrode SE and the drain electrode DE are located on the side of the multilayer structure away from the substrate 11 and are electrically connected to the multilayer structure, respectively. More specifically, the source electrode SE and the drain electrode DE are located on a side of the interface layer 17 away from the active layer 15 and are in contact with the interface layer 17.
  • the passivation layer 19 covers the side of the source electrode SE and the drain electrode DE away from the interface layer 17. More specifically, the passivation layer 19 is located on the side of the source electrode SE and the drain electrode DE away from the interface layer 17 and extends into the area between the source electrode SE and the drain electrode DE To contact the interface layer 17.
  • the base 11 includes, for example, a substrate 111 and a buffer layer 113 formed on the substrate 111.
  • the substrate 111 is, for example, a silicon (Si) substrate or a glass substrate or even a polymer material substrate, and the material of the buffer layer 113 is, for example, silicon oxide (SiOx).
  • the material of the gate electrode GE, the source electrode SE, and the drain electrode DE is, for example, molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti); the material of the gate insulating layer 13 is, for example, silicon oxide.
  • the active layer 15 includes, for example, indium gallium zinc oxide and other oxide semiconductor materials, such as amorphous indium gallium zinc oxide;
  • the interface layer 17 includes, for example, a polyhydroxy transition metal complex, which is typically The transition metal is the core and the hydroxyl group is the ligand, wherein the transition metal is, for example, titanium, zinc, etc.;
  • the material of the passivation layer 19 is, for example, silicon oxide, silicon nitride, or a combination thereof. It should be noted here that the materials of each layer listed above are only examples, and are not used to limit the embodiments of the present application.
  • the interface layer 17 can repair defects on the surface of the active layer 15 and exhibit good film-forming properties, thereby improving the active layer The surface density of 15.
  • the polyhydroxy transition metal complex not only has a higher mobility, but when the film thickness is reduced to a single layer, it still maintains excellent electrical properties. Therefore, the interface layer 17 is in contact with the source electrode SE and the drain electrode DE think of it as an ohmic contact.
  • the thickness of the interface layer 17 is only a few nanometers, for example, the thickness is in the range of 1 nm-10 nm. Metal ions can diffuse through the tunneling effect. Therefore, the introduction of the interface layer 17 will not reduce the source electrode SE and the drain electrode DE. Contact work function with active layer 15.
  • the interface layer 17 includes: a peripheral portion 17P sandwiched between the source electrode SE and the drain electrode DE and the active layer 15 respectively, and a peripheral portion 17P located between the source electrode SE and the active layer 15 The area between the drain electrodes DE is sandwiched between the passivation layer 19 and the active layer 15 in the middle portion 17C.
  • FIG. 2 is a schematic diagram of the structure before forming the source electrode SE and the drain electrode DE. Comparing FIG. 1 and FIG. 2, it can be seen that during the etching process of forming the source electrode SE and the drain electrode DE, the interface layer 17 is not Was etched and still remains.
  • an etching solution with different etching ratios for the source and drain electrode materials and the interface layer material can be selected to control the etching rate, so as to achieve the The protection of the active layer 15 is described.
  • the optional source and drain electrode material etching solutions are, for example, oxalic acid, phosphoric acid, aqua regia, etc., and different effects can be achieved by adjusting the ratio of the source and drain electrode material etching solutions to the interface layer material etching solution, as shown in Figure 1
  • the interface layer 17 shown is not etched but still remains, or the part of the interface layer 17 shown in FIG.
  • FIG. 4 Between the source electrode SE and the drain electrode DE is partially etched away, or it is shown in FIG. 4 The portion of the interface layer 17 shown between the source electrode SE and the drain electrode DE is completely etched away. In FIG. 3, the thickness of the peripheral portion 17P of the interface layer 17 is greater than the thickness of the middle portion 17C. In FIG. 4, because the area between the source electrode SE and the drain electrode DE is not provided with the interface layer 17, in the area between the source electrode SE and the drain electrode DE, the passivation layer 19 and The active layer 15 is in contact.
  • the present embodiment introduces the interface layer 17 between the active layer 15 of the switching element 10 and the source electrode SE and drain electrode DE, and its hydroxyl-based defect repair function can improve the corrosion resistance and density of the surface of the active layer 15 Because the thickness of the interface layer 17 is a few nanometers, the metal ions can diffuse through the tunneling effect, so that the contact work function of the active layer 15 and the source electrode SE and the drain electrode DE is not affected; therefore, this embodiment does not increase the photomask Based on this, the device stability of the switching element 10, such as a back-channel etched thin film transistor, is improved.
  • a switching element 50 provided by the second embodiment of the present application is, for example, a self-aligned top-gate oxide thin film transistor, and includes a substrate 51 and a multilayer structure disposed on the substrate 51, The gate insulating layer 53, the gate electrode GE, the source electrode SE, the drain electrode DE, the interlayer insulating layer 58, and the passivation layer 59; and the multilayer structure includes an active layer 55 and an active layer 55 located far from the substrate 51
  • the interface layer 57 on the side of, specifically the active layer 55 is located between the interface layer 57 and the substrate 51.
  • the gate insulating layer 53 is located on one side of the multilayer structure, and the gate electrode GE is located on the side of the gate insulating layer 53 away from the multilayer structure; specifically, the gate insulating layer 53 Located between the gate electrode GE and the interface layer 57.
  • the interlayer insulating layer 58 is located on a side of the interface layer 57 away from the substrate 51 and covers the gate electrode GE and the gate insulating layer 53.
  • the source electrode SE and the drain electrode DE are located on the side of the multilayer structure away from the substrate 51 and are electrically connected to the multilayer structure, respectively. More specifically, the source electrode SE and the drain electrode DE are located on the side of the interlayer insulating layer 58 away from the interface layer 57, and penetrate the interlayer insulating layer 58 to pass through the interface layer 57 and The active layer 55 forms an electrical connection.
  • the passivation layer 59 covers a side of the source electrode SE and the drain electrode DE away from the interface layer 57. More specifically, the passivation layer 59 is located on a side of the source electrode SE, the drain electrode DE, and the interlayer insulating layer 58 away from the interface layer 57.
  • the base 51 includes, for example, a substrate 511 and a buffer layer 513 formed on the substrate 511.
  • the substrate 511 is, for example, a silicon (Si) substrate or a glass substrate or even a polymer material substrate
  • the material of the buffer layer 513 is, for example, silicon oxide (SiOx).
  • the material of the gate electrode GE, the source electrode SE, and the drain electrode DE is, for example, molybdenum (Mo), aluminum (Al), copper (Cu) or titanium (Ti), etc.
  • the material of the gate insulating layer 53 is, for example, silicon oxide.
  • the active layer 55 includes, for example, indium gallium zinc oxide and other oxide semiconductor materials, such as amorphous indium gallium zinc oxide;
  • the interface layer 57 includes, for example, a polyhydroxy transition metal complex, which is typically The transition metal is the core and the hydroxyl group is the ligand, where the transition metal is, for example, titanium, zinc, etc.;
  • the material of the interlayer insulating layer 58 is, for example, silicon oxide, silicon nitride, or a combination thereof;
  • the material of the passivation layer 59 is, for example, Silicon oxide, silicon nitride, or a combination thereof. It should be noted here that the materials of each layer listed above are only examples, and are not used to limit the embodiments of the present application.
  • the interface layer 57 can repair defects on the surface of the active layer 55, exhibiting good film-forming properties, and thereby improve the active layer.
  • the polyhydroxy transition metal complex not only has a higher mobility, but when the film thickness is reduced to a single layer, it still maintains excellent electrical properties. Therefore, the interface layer 57 is in contact with the source electrode SE and the drain electrode DE think of it as an ohmic contact.
  • the thickness of the interface layer 57 is only a few nm, for example, the thickness is in the range of 1nm-10nm. Metal ions can diffuse through the tunneling effect. Therefore, the introduction of the interface layer 57 will not reduce the source electrode SE and drain electrode DE and the active layer 55.
  • the interface layer 57 includes: a middle portion 57C located directly under the gate electrode GE and a peripheral portion 57P located on both sides of the gate electrode GE; the source electrode SE and the drain electrode DE
  • the active layer 55 is electrically connected through the peripheral portion 57P, respectively.
  • 6 is a schematic diagram of the structure before forming the gate electrode GE and the gate insulating layer 53. Comparing FIG. 5 and FIG. 6, it can be seen that in the process of forming the gate electrode GE and the gate insulating layer 53, the interface layer 57 It is not etched but remains.
  • the active layer 55 on both sides of the gate electrode GE is H-doped by the H diffusion method to form the active layer 55 source and drain regions, and then select an etching solution with different etching ratios for the gate insulating layer material and the interface layer material, and use the gate electrode GE as a mask to etch the gate insulating layer material and even the interface layer material, and then sequentially
  • the interlayer insulating layer 58 and the source electrode SE and the drain electrode DE are formed, and the source electrode SE and the drain electrode DE are electrically connected to the source region and the drain region of the active layer 55.
  • the interface layer 57 shown in FIG. 5 is not etched but still remains, or it is shown in FIG. 7
  • the portion of the interface layer 57 shown on both sides of the gate electrode GE is partially etched away, or the portion of the interface layer 57 shown in FIG. 8 on both sides of the gate electrode GE is completely etched away.
  • the thickness of the middle portion 57C of the interface layer 57 is greater than the thickness of the peripheral portion 57P.
  • the source electrode SE and the drain electrode DE respectively directly contact the active layer 55 to form an electrical connection.
  • the above-mentioned etching process may not be performed on the gate insulating layer material, but the source and drain electrode contacts are opened.
  • RIE Reactive Ion Etching
  • this embodiment introduces the interface layer 57 on the upper surface of the active layer 55 of the switching element 50, and its hydroxyl-based defect repair effect can improve the corrosion resistance and compactness of the active layer 55, and is based on the interface layer 57
  • the thickness is a few nm
  • the metal ions can diffuse through the tunneling effect so that the contact work function between the active layer 55 and the source electrode SE and the drain electrode DE is not affected, and the interface layer 57 is located between the active layer 55 and the gate insulating layer 53
  • this embodiment improves the device stability of the switching element 50, such as a self-aligned top-gate thin film transistor, without adding a mask. Sex.
  • a display panel 90 provided by the third embodiment of the present application includes: an array substrate 91, a display medium layer 93 and an opposite substrate 95, and the display medium layer 93 is sandwiched on the array substrate 91 And the opposite substrate 95.
  • the array substrate 91 includes an active switch array layer 911 and a pixel electrode layer 913.
  • the active switch array layer 911 includes a plurality of switching elements 10 described in the foregoing first embodiment and these switching elements 10 share the same substrate, or includes a plurality of switching elements 50 described in the foregoing second embodiment and these The switching elements 50 share the same substrate, and the specific structure will not be repeated here.
  • the pixel electrode layer 913 includes a plurality of pixel electrodes, for example, the pixel electrodes are arranged in rows and columns, and each of the pixel electrodes is electrically connected to a corresponding switching element in the active switch array layer 911, for example, is electrically connected to an active switch.
  • the drain electrode DE of the corresponding switching element in the array layer 911 see FIG. 1, FIG. 3-5, FIG. 7 and FIG. 8).
  • the display panel 90 is a liquid crystal display (LCD) panel, and each pixel electrode in the pixel electrode layer 913 on the array substrate 91 is, for example, ITO. Electrodes or other transparent electrodes, the display medium layer 93 includes a liquid crystal material layer, and the counter substrate 95 includes, for example, a glass substrate and a common electrode layer (as a counter electrode) disposed on the side of the glass substrate adjacent to the display medium layer 93. Other layer structures such as color filter (CF) layer, PI (Polyimide, polyimide) alignment layer, etc. Of course, for a COA (Color Filter On Array) type liquid crystal display panel, the color filter layer is disposed on the array substrate 91 and is typically located on the side of the pixel electrode layer 913 adjacent to the active switch array layer 911 .
  • COA Color Filter On Array
  • the display panel 90 is, for example, an OLED (Organic Light Emitting Diode) display panel, and each pixel electrode in the pixel electrode layer 913 on the array substrate 91 is, for example, It is the anode of an organic light-emitting diode, and its material can be a transparent material such as ITO, or a highly reflective metal material; the display medium layer 93 includes an organic light-emitting material layer, and the counter substrate 95 includes, for example, a metal layer (as the cathode of the light-emitting diode). Counter electrode) or even other layer structures such as thin film encapsulation layer.
  • the display panel 90 of this embodiment may also be other types of display panels, such as a Quantum Dot Light Emitting Diode (Quantum Dot Light Emitting Diode) display panel.

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Abstract

一种开关元件（10）及相应的显示面板，开关元件（10）例如包括：基底（11）以及设置在基底（11）上的栅电极（GE）、栅绝缘层（13）、多层结构、源电极（SE）、漏电极（DE）和钝化层（19）。多层结构包括主动层（15）和位于主动层（15）远离基底的一侧的界面层（17），主动层（15）包含氧化物半导体材料，且界面层（17）包含多羟基过渡金属络合物；栅绝缘层（13）位于多层结构的一侧，且栅电极（GE）位于栅绝缘层（13）远离多层结构的一侧；源电极（SE）和漏电极（DE）位于多层结构远离基底（11）的一侧、且分别电连接多层结构；以及钝化层（19）覆盖源电极（SE）和漏电极（DE）远离界面层（17）的一侧。藉由在主动层（15）远离基底（11）的一侧设置界面层（17），可以提高开关元件（10）的器件稳定性。

Description

开关元件和显示面板 技术领域
本申请涉及电子器件和显示技术领域，尤其涉及一种开关元件以及一种显示面板。
背景技术
以α-IGZO(非晶铟镓锌氧化物)作为主动层的氧化物薄膜晶体管(Oxide TFT)具有迁移率高、大面积均匀性好、制备工艺温度低等特点，在平板显示的开关和驱动方面表现优异，成为目前TFT研究热点。但是α-IGZO主动层对工艺和环境非常敏感，在制备氧化物薄膜晶体管的过程中，其结构、各层薄膜的制备条件、光刻、蚀刻技术等都会影响到主动层中的缺陷类型及其态密度和主动层与绝缘层界面的电荷缺陷态密度。
常见的氧化物薄膜晶体管结构包括背沟道蚀刻(Back Channel Etching，BCE)型薄膜晶体管、蚀刻阻挡层(EtchStop Layer，ESL)型薄膜晶体管和自对准顶栅(Self-Align Type Top-Gate)型薄膜晶体管。相比ESL型薄膜晶体管，BCE型薄膜晶体管光罩数量少、成本低，但由于主动层与源漏极直接接触，形成源漏极的蚀刻工艺会使主动层受损，进而影响薄膜晶体管的稳定性；再者，BCE型薄膜晶体管的主动层接近环境气氛，为避免环境因素对主动层的影响，钝化层厚度需增加，但这样不利于器件的小型化；此外，主动层一般采用溅射沉积的方法形成，造成主动层表面的不平整会增大源漏电极与主动层的接触电阻，降低迁移率。对于自对准顶栅型薄膜晶体管来说，由于栅绝缘层的形成为低温制程，栅绝缘层的氢(H)易扩散到主动层的沟道区使其变成导体，降低器件的稳定性。
申请内容
有鉴于此，本申请实施例提供了一种开关元件例如氧化物薄膜晶体管，以达成提升器 件稳定性之技术效果。
具体地，本申请实施例提供的一种开关元件，包括：基底以及设置在所述基底上的栅电极、栅绝缘层、多层结构、源电极、漏电极和钝化层；其中，所述多层结构包括主动层和位于所述主动层远离所述基底的一侧的界面层，所述主动层包含氧化物半导体材料，且所述界面层包含多羟基过渡金属络合物；所述栅绝缘层位于所述多层结构的一侧，且所述栅电极位于所述栅绝缘层远离所述多层结构的一侧；所述源电极和所述漏电极位于所述多层结构远离所述基底的一侧、且分别电连接所述多层结构；以及所述钝化层覆盖所述源电极和所述漏电极远离所述界面层的一侧。
在本申请的一个实施例中，所述多羟基过渡金属络合物以过渡金属为核、且以羟基为配位体。
在本申请的一个实施例中，所述界面层的厚度为数纳米(nm)，例如位于1nm-10nm范围内。
在本申请的一个实施例中，所述氧化物半导体材料为铟镓锌氧化物，以及所述基底包括半导体衬底和形成在所述半导体衬底上的缓冲层。
在本申请的一个实施例中，所述栅电极位于所述栅绝缘层和所述基底之间，所述主动层位于所述界面层和所述栅绝缘层之间，以及所述源电极和所述漏电极位于所述钝化层和所述界面层之间。
在本申请的一个实施例中，所述界面层包括：分别夹设于所述源电极及所述漏电极与所述主动层之间的周边部分，以及位于所述源电极和所述漏电极之间的区域且夹设于所述钝化层和所述主动层之间的中间部分。
在本申请的一个实施例中，所述周边部分的厚度大于所述中间部分的厚度。
在本申请的一个实施例中，所述界面层包括分别夹设于所述源电极及所述漏电极与所述主动层之间的部分，且所述主动层位于所述源电极和所述漏电极之间的区域未设置所述界面层。
在本申请的一个实施例中，所述主动层位于所述界面层和所述基底之间，所述栅绝缘层位于所述栅电极和所述界面层之间，所述开关元件还包括层间绝缘层、且所述层间绝缘层位于所述界面层远离所述基底的一侧并覆盖所述栅电极及所述栅绝缘层，所述源电极和所述漏电极位于所述层间绝缘层远离所述界面层的一侧、且贯穿所述层间绝缘层以与所述主动层形成电连接，以及所述钝化层位于所述源电极、所述漏电极和所述层间绝缘层远离所述界面层的一侧。
在本申请的一个实施例中，所述界面层包括：位于所述栅电极正下方的中间部分和位于所述栅电极两侧的周边部分；所述源电极和所述漏电极分别通过所述周边部分电连接所述主动层。
在本申请的一个实施例中，所述中间部分的厚度大于所述周边部分的厚度。
在本申请的一个实施例中，所述源电极和所述漏电极分别与所述主动层接触以形成电连接。
另一方面，本申请实施例还提供的一种显示面板，包括：阵列基板，包括主动开关阵列层和像素电极层，其中所述主动开关阵列层包括多个如前所述任意一种开关元件，所述像素电极层包括呈行列方式排列的多个像素电极，且每个所述像素电极电连接所述主动开关阵列层中相应的开关元件；对向基板；以及显示介质层，夹设在所述阵列基板与所述对向基板之间。
在本申请的一个实施例中，所述显示介质层包括有机发光材料层，所述像素电极为发 光二极管的阳极，以及所述对向基板包括所述发光二极管的阴极。
在本申请的一个实施例中，所述显示介质层包括液晶材料层，以及所述对向基板包括公共电极层。
上述一个或多个技术方案具有如下一个或多个优点或有益效果：本实施例在开关元件的所述主动层上表面引入所述界面层，其基于羟基的缺陷修补作用可以提高所述主动层表面的抗蚀性及致密性，基于所述界面层的厚度为数nm时金属离子可通过隧穿效应来扩散从而可以不影响所述主动层与所述源电极及所述漏电极的接触功函数，再者位于所述主动层与所述栅绝缘层之间的所述界面层可以抑制H扩散到所述主动层的沟道区使其变成导体；因此本实施例在不增加光罩的基础上提高了开关元件比如背沟道蚀刻型薄膜晶体管或自对准顶栅型薄膜晶体管的器件稳定性。再者，归功于开关元件的器件稳定性提升，采用该种开关元件的显示面板的质量也能够得到相应改进。
附图说明
为了更清楚地说明本申请实施例的技术方案，下面将对实施例描述中所需要使用的附图作简单地介绍，显而易见地，下面描述中的附图仅仅是本申请的一些实施例，对于本领域普通技术人员来讲，在不付出创造性劳动的前提下，还可以根据这些附图获得其他的附图。
图1为本申请第一实施例的一种开关元件的剖面结构示意图。
图2为图1所示开关元件在形成源电极和漏电极之前的剖面结构示意图。
图3为本申请第一实施例的另一种开关元件的剖面结构示意图。
图4为本申请第一实施例的再一种开关元件的剖面结构示意图。
图5为本申请第二实施例的一种开关元件的剖面结构示意图。
图6为图5所示开关元件在形成栅绝缘层及栅电极之前的剖面结构示意图。
图7为本申请第二实施例的另一种开关元件的剖面结构示意图。
图8为本申请第二实施例的再一种开关元件的剖面结构示意图。
图9为本申请第三实施例的一种显示面板的结构示意图。
具体实施方式
下面将结合本申请实施例中的附图，对本申请实施例中的技术方案进行清楚、完整地描述，显然，所描述的实施例仅仅是本申请一部分实施例，而不是全部的实施例。基于本申请中的实施例，本领域普通技术人员在没有作出创造性劳动前提下所获得的所有其他实施例，都属于本申请保护的范围。
【第一实施例】
如图1所示，本申请第一实施例提供的一种开关元件10例如是背沟道蚀刻型氧化物薄膜晶体管，包括：基底11以及设置在所述基底11上的栅电极GE、栅绝缘层13、多层结构、源电极SE、漏电极DE和钝化层19；且所述多层结构包括主动层15和位于所述主动层15远离所述基底11的一侧的界面层17。
其中，所述栅绝缘层13位于所述多层结构的一侧，且所述栅电极GE位于所述栅绝缘层13远离所述多层结构的一侧，从而所述栅电极GE位于所述栅绝缘层13与所述基底11之间。再者，主动层15具体地位于所述界面层17和所述栅绝缘层13之间。
所述源电极SE和所述漏电极DE位于所述多层结构远离所述基底11的一侧、且分别电连接所述多层结构。更具体地，所述源电极SE和所述漏电极DE位于所述界面层17远离所述主动层15的一侧且与所述界面层17接触。
所述钝化层19覆盖所述源电极SE和所述漏电极DE远离所述界面层17的一侧。更具 体地，所述钝化层19位于所述源电极SE和所述漏电极DE远离所述界面层17的一侧、并伸入所述源电极SE和所述漏电极DE之间的区域以接触所述界面层17。
承上述，基底11例如包括衬底111和形成在所述衬底111上的缓冲层113。所述衬底111例如是硅(Si)衬底或玻璃衬底甚至高分子材料衬底，缓冲层113的材料例如是硅氧化物(SiOx)。再者，栅电极GE、源电极SE和漏电极DE的材料例如是钼(Mo)、铝(Al)、铜(Cu)或钛(Ti)等；栅绝缘层13的材料例如是硅氧化物、硅氮化物或其组合；主动层15例如包含铟镓锌氧化物等氧化物半导体材料，比如是非晶铟镓锌氧化物；界面层17例如包含多羟基过渡金属络合物，其典型地以过渡金属为核且以羟基为配位体，其中过渡金属例如是钛、锌等；钝化层19的材料例如是硅氧化物、硅氮化物或其组合。此处需要说明的是，以上所列的各个层的材料仅为举例，并非用来限制本申请的实施例。
此外，由于界面层17中的羟基与主动层15的氧结构均为亲水基团，因此界面层17在主动层15的表面可以进行缺陷修补，表现出良好的成膜性，进而提升主动层15的表面致密性。再者，多羟基过渡金属络合物不仅有较高的迁移率，而且当其薄膜厚度减到单层，仍然保持着优异的电学特性，因此界面层17与源电极SE及漏电极DE的接触认为是欧姆接触。另外，界面层17的厚度仅数nm例如其厚度位于1nm-10nm范围内，金属离子可通过隧穿效应(tunneling effect)来扩散，因此界面层17的引入不会降低源电极SE及漏电极DE与主动层15的接触功函数。
再者，从图1可知，界面层17包括：分别夹设于所述源电极SE及所述漏电极DE与所述主动层15之间的周边部分17P，以及位于所述源电极SE和所述漏电极DE之间的区域且夹设于所述钝化层19和所述主动层15之间的中间部分17C。图2为形成所述源电极SE和所述漏电极DE之前的结构示意图，比较图1和图2可知，在蚀刻形成所述源电极SE和所 述漏电极DE的过程中，界面层17未被蚀刻而仍然保留。
对于本实施例的开关元件10，在形成所述源电极SE和所述漏电极DE时，可以选择对源漏电极材料与界面层材料具有不同蚀刻比的蚀刻液来控制蚀刻速率，达到对所述主动层15的保护。具体地，可选用的源漏电极材料的蚀刻液例如是草酸、磷酸、王水等，通过调配源漏电极材料的蚀刻液与界面层材料的蚀刻液的比例可以达到不同的效果，例如图1所示的界面层17未被蚀刻而仍然保留，或者是图3所示的界面层17位于所述源电极SE和所述漏电极DE之间的部分被部分蚀刻掉，又或者是图4所示的界面层17位于所述源电极SE和所述漏电极DE之间的部分完全被蚀刻掉。在图3中，所述界面层17的周边部分17P的厚度大于中间部分17C的厚度。在图4中，因为所述源电极SE和所述漏电极DE之间的区域未设置界面层17，因此在所述源电极SE和所述漏电极DE之间的区域，钝化层19与主动层15接触。
综上所述，本实施例在开关元件10的主动层15和源电极SE及漏电极DE之间引入界面层17，其基于羟基的缺陷修补作用可以提高主动层15表面的抗蚀性及致密性，并且基于界面层17的厚度为数nm时金属离子可通过隧穿效应来扩散从而可以不影响主动层15与源电极SE及漏电极DE的接触功函数；因此本实施例在不增加光罩的基础上提高了开关元件10比如背沟道蚀刻型薄膜晶体管的器件稳定性。
【第二实施例】
参见如图5所示，本申请第二实施例提供的一种开关元件50例如是自对准顶栅型氧化物薄膜晶体管，包括：基底51以及设置在所述基底51上的多层结构、栅绝缘层53、栅电极GE、源电极SE、漏电极DE、层间绝缘层58和钝化层59；且所述多层结构包括主动层55和位于所述主动层55远离所述基底51的一侧的界面层57，具体为所述主动层55位于 所述界面层57和所述基底51之间。
其中，所述栅绝缘层53位于所述多层结构的一侧，且所述栅电极GE位于所述栅绝缘层53远离所述多层结构的一侧；具体地，所述栅绝缘层53位于所述栅电极GE与所述界面层57之间。
所述层间绝缘层58位于所述界面层57远离所述基底51的一侧、并覆盖所述栅电极GE及所述栅绝缘层53。
所述源电极SE和所述漏电极DE位于所述多层结构远离所述基底51的一侧、且分别电连接所述多层结构。更具体地，所述源电极SE和所述漏电极DE位于所述层间绝缘层58远离所述界面层57的一侧、且贯穿所述层间绝缘层58以通过所述界面层57与所述主动层55形成电连接。
所述钝化层59覆盖所述源电极SE和所述漏电极DE远离所述界面层57的一侧。更具体地，所述钝化层59位于所述源电极SE、所述漏电极DE和所述层间绝缘层58远离所述界面层57的一侧。
承上述，基底51例如包括衬底511和形成在所述衬底511上的缓冲层513。所述衬底511例如是硅(Si)衬底或玻璃衬底甚至高分子材料衬底，缓冲层513的材料例如是硅氧化物(SiOx)。再者，栅电极GE、源电极SE和漏电极DE的材料例如是钼(Mo)、铝(Al)、铜(Cu)或钛(Ti)等；栅绝缘层53的材料例如是硅氧化物、硅氮化物或其组合；主动层55例如包含铟镓锌氧化物等氧化物半导体材料，比如是非晶铟镓锌氧化物；界面层57例如包含多羟基过渡金属络合物，其典型地以过渡金属为核且以羟基为配位体，其中过渡金属例如是钛、锌等；层间绝缘层58的材料例如是硅氧化物、硅氮化物或其组合；钝化层59的材料例如是硅氧化物、硅氮化物或其组合。此处需要说明的是，以上所列的各个层的材料仅为举例， 并非用来限制本申请的实施例。
此外，由于界面层57中的羟基与主动层55的氧结构均为亲水基团，因此界面层57在主动层55的表面可以进行缺陷修补，表现出良好的成膜性，进而提升主动层55的表面致密性。再者，多羟基过渡金属络合物不仅有较高的迁移率，而且当其薄膜厚度减到单层，仍然保持着优异的电学特性，因此界面层57与源电极SE及漏电极DE的接触认为是欧姆接触。另外，界面层57的厚度仅数nm例如其厚度位于1nm-10nm范围内，金属离子可通过隧穿效应来扩散，因此界面层57的引入不会降低源电极SE及漏电极DE与主动层55的接触功函数。
再者，从图5可知，界面层57包括：位于所述栅电极GE正下方的中间部分57C和位于所述栅电极GE两侧的周边部分57P；所述源电极SE和所述漏电极DE分别通过所述周边部分57P电连接所述主动层55。图6为形成所述栅电极GE和所述栅绝缘层53之前的结构示意图，比较图5和图6可知，在形成所述栅电极GE和所述栅绝缘层53的过程中，界面层57未被蚀刻而仍然保留。
对于本实施例的开关元件50，在图6所示层结构上形成所述栅电极GE之后，例如通过H扩散法对栅电极GE两侧的主动层55进行H掺杂以形成所述主动层55的源极区和漏极区，然后选择对栅绝缘层材料和界面层材料具有不同蚀刻比的蚀刻液以栅电极GE为掩膜对栅绝缘层材料甚至界面层材料进行蚀刻，之后再依次形成所述层间绝缘层58和所述源电极SE及漏电极DE、并使所述源电极SE及漏电极DE电连接所述主动层55的所述源极区及所述漏极区。此处，通过调配不同蚀刻比的蚀刻液对栅绝缘层材料甚至界面层材料进行蚀刻可以得到不同的蚀刻效果，例如图5所示的界面层57未被蚀刻而仍然保留，或者是图7所示的界面层57位于所述栅电极GE两侧的部分被部分蚀刻掉，又或者是图8所示的界 面层57位于所述栅电极GE两侧的部分被完全蚀刻掉。在图7中，所述界面层57的中间部分57C的厚度大于周边部分57P的厚度。在图8中，因为栅电极GE两侧的部分未设置界面层57，因此所述源电极SE和所述漏电极DE分别直接与所述主动层55接触以形成电连接。另外，值得一提的是，在其他具体实施方式中，形成所述主动层55的源极区和漏极区之后也可以不对栅绝缘层材料进行上述蚀刻工艺，而是在开设源漏电极接触孔时利用RIE(Reactive Ion Etching，反应离子蚀刻)对层间绝缘层材料连同栅绝缘层材料进行蚀刻以便于所述源电极SE及漏电极DE与所述主动层55形成电连接。
综上所述，本实施例在开关元件50的主动层55上表面引入界面层57，其基于羟基的缺陷修补作用可以提高主动层55表面的抗蚀性及致密性，并且基于界面层57的厚度为数nm时金属离子可通过隧穿效应来扩散从而可以不影响主动层55与源电极SE及漏电极DE的接触功函数，再者位于主动层55与栅绝缘层53之间的界面层57可以抑制H扩散到主动层55的沟道区(Channel)使其变成导体；因此本实施例在不增加光罩的基础上提高了开关元件50比如自对准顶栅型薄膜晶体管的器件稳定性。
【第三实施例】
参见如图9所示，本申请第三实施例提供的一种显示面板90，包括：阵列基板91、显示介质层93和对向基板95，且显示介质层93夹设在所述阵列基板91和所述对向基板95之间。
其中，所述阵列基板91包括主动开关阵列层911和像素电极层913。所述主动开关阵列层911例如包含多个前述第一实施例所述的开关元件10且这些开关元件10共用同一个衬底、或者包含多个前述第二实施例所述的开关元件50且这些开关元件50共用同一个衬底，具体结构在此不再赘述。所述像素电极层913包含多个像素电极，这些像素电极例如 呈行列方式排列，且每个所述像素电极与所述主动开关阵列层911中相应的开关元件形成电连接，例如电连接主动开关阵列层911中相应的开关元件的漏电极DE(参见图1、图3-5、图7及图8)。
承上述，在一个具体实施方式中，所述显示面板90为一种液晶显示(Liquid Crystal Display,LCD)面板，所述阵列基板91上的所述像素电极层913中的各个像素电极例如是ITO电极或其他透明电极，显示介质层93包括液晶材料层，对向基板95例如包括玻璃基板和设置在玻璃基板的邻近所述显示介质层93的一侧的公共电极层(作为对向电极)甚至其他层结构比如滤色器(Color Filter,CF)层、PI(Polyimide，聚酰亚胺)配向层等。当然，对于COA(Color Filter On Array)型液晶显示面板而言，则滤色器层设置在所述阵列基板91上且典型地位于像素电极层913的邻近所述主动开关阵列层911的一侧。
在其他实施方式中，所述显示面板90例如是一种OLED(Organic Light Emitting Diode,有机电致发光二极管)显示面板，所述阵列基板91上的所述像素电极层913中的各个像素电极例如是有机发光二极管的阳极，其材料可以是ITO等透明材料，也可以是高反射金属材料；显示介质层93包括有机发光材料层，对向基板95例如包括作为发光二极管的阴极的金属层(作为对向电极)甚至其他层结构比如薄膜封装层。此外，本实施例的显示面板90还可以是其他类型的显示面板，例如量子点电致发光二极管(Quantum Dot Light Emitting Diode)显示面板。
此外，可以理解的是，前述各个实施例仅为本申请的示例性说明，在技术特征不冲突、结构不矛盾、不违背本申请的发明目的前提下，各个实施例的技术方案可以任意组合、搭配使用。
最后应说明的是：以上实施例仅用以说明本申请的技术方案，而非对其限制；尽 管参照前述实施例对本申请进行了详细的说明，本领域的普通技术人员应当理解：其依然可以对前述各实施例所记载的技术方案进行修改，或者对其中部分技术特征进行等同替换；而这些修改或者替换，并不使相应技术方案的本质脱离本申请各实施例技术方案的精神和范围。

Claims (15)

  1. 一种开关元件，其特征在于，包括：基底以及设置在所述基底上的栅电极、栅绝缘层、多层结构、源电极、漏电极和钝化层；其中，
    所述多层结构包括主动层和位于所述主动层远离所述基底的一侧的界面层，所述主动层包含氧化物半导体材料，且所述界面层包含多羟基过渡金属络合物；
    所述栅绝缘层位于所述多层结构的一侧，且所述栅电极位于所述栅绝缘层远离所述多层结构的一侧；
    所述源电极和所述漏电极位于所述多层结构远离所述基底的一侧、且分别电连接所述多层结构；以及
    所述钝化层覆盖所述源电极和所述漏电极远离所述界面层的一侧。
  2. 根据权利要求1所述的开关元件，其特征在于，所述多羟基过渡金属络合物以过渡金属为核、且以羟基为配位体。
  3. 根据权利要求1所述的开关元件，其特征在于，所述界面层的厚度位于1nm-10nm范围内。
  4. 根据权利要求1所述的开关元件，其特征在于，所述氧化物半导体材料为铟镓锌氧化物，以及所述基底包括半导体衬底和形成在所述半导体衬底上的缓冲层。
  5. 根据权利要求1所述的开关元件，其特征在于，所述栅电极位于所述栅绝缘层和所述基底之间，所述主动层位于所述界面层和所述栅绝缘层之间，以及所述源电极和所述漏电极位于所述钝化层和所述界面层之间。
  6. 根据权利要求5所述的开关元件，其特征在于，所述界面层包括：分别夹设于所述源电极及所述漏电极与所述主动层之间的周边部分，以及位于所述源电极和所述漏电极之 间的区域且夹设于所述钝化层和所述主动层之间的中间部分。
  7. 根据权利要求6所述的开关元件，其特征在于，所述周边部分的厚度大于所述中间部分的厚度。
  8. 根据权利要求5所述的开关元件，其特征在于，所述界面层包括分别夹设于所述源电极及所述漏电极与所述主动层之间的部分，且所述主动层位于所述源电极和所述漏电极之间的区域未设置所述界面层。
  9. 根据权利要求1所述的开关元件，其特征在于，所述主动层位于所述界面层和所述基底之间，所述栅绝缘层位于所述栅电极和所述界面层之间，所述开关元件还包括层间绝缘层、且所述层间绝缘层位于所述界面层远离所述基底的一侧并覆盖所述栅电极及所述栅绝缘层，所述源电极和所述漏电极位于所述层间绝缘层远离所述界面层的一侧、且贯穿所述层间绝缘层以与所述主动层形成电连接，以及所述钝化层位于所述源电极、所述漏电极和所述层间绝缘层远离所述界面层的一侧。
  10. 根据权利要求9所述的开关元件，其特征在于，所述界面层包括：位于所述栅电极正下方的中间部分和位于所述栅电极两侧的周边部分；所述源电极和所述漏电极分别通过所述周边部分电连接所述主动层。
  11. 根据权利要求10所述的开关元件，其特征在于，所述中间部分的厚度大于所述周边部分的厚度。
  12. 根据权利要求9所述的开关元件，其特征在于，所述源电极和所述漏电极分别与所述主动层接触以形成电连接。
  13. 一种显示面板，其特征在于，包括：
    阵列基板，包括主动开关阵列层和像素电极层，其中所述主动开关阵列层包括多个如 权利要求1至12任意一项所述的开关元件，所述像素电极层包括呈行列方式排列的多个像素电极，且每个所述像素电极电连接所述主动开关阵列层中相应的开关元件；
    对向基板；以及
    显示介质层，夹设在所述阵列基板与所述对向基板之间。
  14. 根据权利要求13所述的显示面板，其特征在于，所述显示介质层包括有机发光材料层，所述像素电极为发光二极管的阳极，以及所述对向基板包括所述发光二极管的阴极。
  15. 根据权利要求13所述的显示面板，其特征在于，所述显示介质层包括液晶材料层，以及所述对向基板包括公共电极层。
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