WO2008087015A2 - Integrierter schaltkreis - Google Patents
Integrierter schaltkreis Download PDFInfo
- Publication number
- WO2008087015A2 WO2008087015A2 PCT/EP2008/000282 EP2008000282W WO2008087015A2 WO 2008087015 A2 WO2008087015 A2 WO 2008087015A2 EP 2008000282 W EP2008000282 W EP 2008000282W WO 2008087015 A2 WO2008087015 A2 WO 2008087015A2
- Authority
- WO
- WIPO (PCT)
- Prior art keywords
- reference potential
- signal
- integrated circuit
- input
- terminal
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
- H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
- H03K19/003—Modifications for increasing the reliability for protection
- H03K19/0033—Radiation hardening
- H03K19/00338—In field effect transistor circuits
Definitions
- the present invention relates to an integrated circuit having at least one terminal for coupling and / or decoupling electrical signals, in particular digital signals, and having integrated reference potential means associated with the terminal for providing an electrical reference potential to the terminal.
- An integrated circuit known from the market is realized as a semiconductor device and has a multiplicity of internal and external connections.
- the internal terminals are formed as nodes of electrical conductors between individual realized in the circuit circuit components such as resistors, capacitors or transistors.
- the external terminals are realized as electromechanical interfaces, which usually via bonding wire connections or Lötkugeleducationen an electrical connection of the integrated circuit with a printed circuit or other electrical components.
- each terminal be at a defined electrical potential at all times. As a result, an interference of electrical signals, which rest for example on adjacent terminals and can be transmitted via inductive or capacitive couplings can be avoided.
- the known integrated circuit has, for this purpose, connections at which no permanent and unambiguous electrical potential or a corresponding associated payload signal, reference potential means on.
- the reference potential means set the terminal in the absence of the useful signal to a defined electrical potential.
- Known reference potential means are realized as pull-up circuits or as pull-down circuits. In this case, a connection is connected via a high-ear resistance with a higher or lower voltage potential, so that the connection is in the absence of a useful signal at the corresponding voltage potential. As soon as a useful signal is applied to the terminal, the electrical potential at the terminal is determined by the high-coherent coupling of the pull-up circuit or the pull-down circuit by the useful signal. Due to the high-resistance resistor, reference potential means designed in this way require a certain area on the integrated circuit and are not suitable for all types of connections.
- the object of the invention is to provide an integrated circuit with reference potential means that can be used for different connections.
- Switchable reference potential means can be switched at least between a first and a second switching state.
- the reference potential means can be provided in the first switching state that the reference potential means provide a predeterminable electrical potential, in particular a constant supply voltage, to the terminal, so that it is protected against irradiation or coupling in of interference signals.
- the reference potential means In the second switching state, it may be provided that the reference potential means provide no electrical potential to the terminal, since the useful signal applied to the terminal ensures that the terminal is at a defined electrical potential. In this case, the useful signal may have a constant, periodically or irregularly changing signal level.
- the useful signal is generated by a useful signal source, which can be specified Operating states of the integrated circuit provides no useful signal.
- a useful signal source which can be specified Operating states of the integrated circuit provides no useful signal.
- the reference potential means it should be provided with the aid of the reference potential means that, instead of the useful signal, the electrical potential provided by the reference potential means is present at the connection in order to prevent radiation or coupling in of undesired interference radiation.
- the reference potential means have a control input, which is designed for coupling a control signal which is provided for the switching of the reference potential means for providing the reference potential to the terminal.
- the control input With the control input, the reference potential means can be switched in the absence of a useful signal such that the terminal is applied to a specifiable electrical potential.
- the control signal can be coupled into the integrated circuit from the outside, advantageously the control signal is generated internally in the integrated circuit.
- the reference potential means are arranged so that only a short electrical pulse is needed to cause switching to provide a reference potential.
- the reference potential means are arranged so that no or at least almost no electrical current flow is necessary to effect a changeover.
- the reference potential means comprise switching means which are designed for an alternative provision of the reference potential or a useful signal to a signal output as a function of a level of the useful signal.
- the switching means are designed for switching between the useful signal and the reference potential as a function of a level of the useful signal.
- the switching means have a signal input which is connected in particular to the useful signal source.
- the switching means may provide the wanted signal at the terminal.
- the switching means are arranged such a useful signal applied to the signal input causes the switching over of the reference potential means, so that the useful signal is provided at the signal output.
- the switching means are designed so that the useful signal can also be used as a control or switching signal for the switching means and can trigger the switching process by overriding the present logic state in the reference potential means. A switchover from the reference potential to the useful signal can thus take place without an additional control signal.
- an automated switching to the reference potential takes place without the need for a control signal to be applied to the signal input of the reference potential means.
- the switching means for the reference potential are formed self-holding.
- the switching means are thus arranged such that even a short switching pulse of a control signal is sufficient to cause a switching of the switching means. From the time when a switchover took place, the control signal is no longer necessary. Rather, the switching means are arranged so that with the switching a stable internal state is taken, in which the reference potential is provided to the terminal. Only when the reference potential is overridden by the useful signal, a new switchover takes place in order to enable the provision of the useful signal to the connection.
- the switching means have at least one field-effect transistor having a control terminal with a width-length ratio of less than 1, preferably less than 1/2, more preferably less than 1/5.
- the control terminal of the field effect transistor which is also referred to as a gate terminal, can be used as a polysilicon layer area in a semiconductor layer structure between a first current connection (source terminal) and a second electrical connection (Gate connection) be realized.
- the distance between the source terminal and the gate terminal is equal to or greater than the width of the control terminal.
- the switching means have a NAND gate which has at least one field-effect transistor having a control terminal with a width-length ratio smaller than 1, preferably smaller than 1/2, more preferably smaller than 1/5 ,
- a first input of the NAND gate is connected to the signal input and a second input of the NAND gate is connected to the control input.
- the NAND gate thus provides a logic "Iow” signal only when all inputs are at a logic "high” level.
- the NAND gate whose output is connected to an input of the NAND gate to ensure the latching potential of the reference potential means can already be output from the low-level useful signal Provision of a reference potential at the terminal to be switched to the useful signal at the terminal.
- the useful signal for an advantageous adaptation to the logical structure of the switching means is first inverted before it is made available to the NAND gate.
- the signal output is connected to a node between the first inverter and the first input of the NAND gate, wherein a second inverter is arranged between the node and the signal output. This ensures that the useful signal supplied to the signal input at the signal output is present without inversion. If no useful signal is fed in at the signal input, the inverted electrical potential of the node is present at the signal output between the first inverter and the first input of the NAND gate.
- 1 is a schematic block diagram of an integrated circuit with a terminal, the reference potential means are assigned,
- 3 is a schematic representation of a field effect transistor with a width / length ratio less than 1,
- FIG. 1 shows a schematic block diagram of an integrated circuit 10, which is realized as a layer structure on a semiconductor crystal, not shown. By structuring different layers on the semiconductor crystal are different functional areas realized, which are shown in a greatly simplified representation in FIG. The selected representation serves exclusively to explain functional relationships and is not to be understood as an image of a semiconductor layout.
- the integrated circuit 10 has a number of bond pads 16, which are provided as contact surfaces for the attachment of bonding wires, not shown. With the bonding wires, an electrical coupling of the integrated circuit 10 to a printed circuit board / printed circuit, not shown, can be realized.
- a plurality of reference potential means 12 are provided, which are provided for providing electrical reference potentials at terminals 18.
- the terminals 18 are realized as internal electrical nodes between a bonding pad 16 and a circuit part, not shown, or between a symbolically represented internal connection point 30 and a circuit part (not shown).
- the reference potential means 12 have, in addition to the signal input 24, a signal output 26, a supply connection 20 and a ground connection 22.
- the signal output 26 is connected to the terminal 18.
- the supply terminal 20 is connected to a voltage source, not shown.
- the ground terminal 22 is at a ground potential.
- a control device 14th is provided, which can provide a control signal to a control input 28 of the reference potential means 12.
- the reference potential means 12 are arranged such that in the absence of a useful signal at the signal input 24, a defined electrical potential at the terminal 18 can be provided.
- a control signal to the control input 28 of the reference potential means 12 is provided by the control device 14.
- the control signal fed to the control terminal 28 as a short-time electrical pulse effects a switching over of the reference potential means 12 so that they can provide a defined electrical (reference) potential at the terminal 18 in the absence of the useful signal. Due to the self-holding design of the reference potential means 12 only a short pulse of the control signal is required to effect the switching of the reference potential means 12. From the time of switching to the reference potential, the reference potential means 12 no further electrical signal must be supplied to ensure the provision of the reference potential at the terminal 18. When a useful signal is supplied to the signal input 24, the reference potential means 12 is automatically switched over so that the useful signal is supplied to the terminal 18 as of this point in time.
- the switching means provided in the reference potential means 12 are represented symbolically as a logic circuit.
- the signal input 24, the signal output 26 and the control input 28 are provided as logic interfaces in the reference potential means 12.
- the signal input 24 may be connected to a bond pad or to an internal connection point, from where a useful signal can be provided.
- the control input 28 is connected to the control device, from where a control signal can be provided.
- the signal output 26 is connected to the terminal and is provided for the provision of the reference potential to the terminal.
- a first inverter 32 is connected between the signal input 24 and a NAND gate 36 (NAND gate or NOT-AND gate) in a Nutzsignal horr 52.
- a first node 44 is connected, which is connected to a gate output 42 of the NAND gate 36, whereby a feedback loop 54 is formed.
- the signal applied to the first node 44 is inverted.
- a first connecting line 48 extends to a first gate input 38 of the NAND gate 36, while a second connecting line 50 is connected to an input terminal of a second inverter 34.
- An output terminal of the second inverter 34 is connected to the signal output 28.
- the NAND gate 36 always outputs an output signal with a logical "high” Level, when at least one of the gate inputs is at a logic “Iow” level, the "Iow” level of the control signal causes a high logic level output by NAND gate 36 to its gate output 42 This "high” level is fed back via the feedback loop 54 to the first node 44, so that the signal input 24 is at the "high” level, whereas the first gate input 38 is due to the inversion of the node " high "levels through the first inverter 32 at a logical" Iow “level and thus ensures that regardless of the control signal at the second gate input 40, the gate output 42 at the logic" high "level ve rsammlungt. This is in the absence of one
- Useful signal at the signal input 24 ensures a self-holding function of the reference potential means 12, since it no longer plays any role, which logical state is applied to the control input 28.
- the "Iow" level present at the second node 46 and the second inverter 34 ensure that the signal output 26 is at a logic "high” level. This represents the preferred signal level for the terminal connected to the signal output 26 in the absence of a useful signal, that is, the terminal is at the desired reference potential.
- the NAND gate 36 is weakly dimensioned, that is to say the corresponding transistors have a width / length ratio smaller than 1, as shown schematically in FIG. 3, a switching of the reference potential means 12 can be reliably achieved by applying a useful signal to the signal input 24 be brought about, by which the useful signal can be forwarded to the signal output 26 and there the connection is made available.
- FIG. 3 shows a schematically represented section of a field-effect transistor.
- the control connection G (gate terminal) of the field-effect transistor designed as a polysilicon layer region is realized between a first current terminal S (source terminal) and a second current terminal D (drain terminal).
- a distance between the power terminals and thus a length of the control terminal G is chosen so that a width / length ratio smaller 1 is guaranteed.
- the width W is approximately 1/6 of the length L of the control connection G (width to length 1, 6/10).
- FIG. 4 shows a circuit diagram for a reference potential means 12. Dashed frames delimit the function blocks known from FIG. 2, that is to say the first inverter 32, the second inverter 34 and the NAND gate 36 from one another.
- the two inverters 32, 34 each have a plurality of field effect transistors 56, 58, 60, 70 and 72 designed with a width / length ratio greater than 1.
- the NAND gate 36 has four Field effect transistors 62, 64, 66, 68 with weak interpretation, which are realized with a width / length ratio less than 1.
- the control input 28 is connected to a control terminal G (gate terminal) of the N MOS transistor 68 and a control terminal G of the PMOS transistor 62.
- the PMOS transistor 62 switches the supply voltage applied to the supply terminal 20 to the first node 44.
- the first node 44 is at a logic "high”. -Level. If no useful signal is present at the signal input 24, thereby the control terminal G of the N-MOS transistor 60 is set to a "high” level and switches through (that is, the resistance between the current terminal S (source terminal) and the Since the control terminal G of the NMOS transistor 58 is permanently at the electrical potential of the supply terminal 20 and thus also through-connected, the first gate input 38 and thus the control terminals G of the PMOS T ransistors 64 and the NMOS transistor 66 to ground, that is set to an "Iow” level, since the PMOS transistor 56 is disabled because of the voltage applied to the signal input 24.
- Transistor 64 is turned off while NMOS transistor 66 is turned off. Thus, even without the control signal, first node 44 is at a “high” level, and it is latched Reference potential means 12 ensures.
- the logical “Iow” level applied to the first gate input 38 is forwarded as an input signal to the second inverter 34 and inverted there, so that an output signal present at the signal output 26 is at a logic "high” level.
- NAND gate 38 first gate input
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- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Computing Systems (AREA)
- General Engineering & Computer Science (AREA)
- Mathematical Physics (AREA)
- Semiconductor Integrated Circuits (AREA)
- Logic Circuits (AREA)
Abstract
Description
Claims
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE112008000041.7T DE112008000041B4 (de) | 2007-01-16 | 2008-01-16 | Integrierter Schaltkreis |
Applications Claiming Priority (4)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US88037707P | 2007-01-16 | 2007-01-16 | |
US60/880,377 | 2007-01-16 | ||
DE102007002502 | 2007-01-17 | ||
DE102007002502.7 | 2007-01-17 |
Publications (2)
Publication Number | Publication Date |
---|---|
WO2008087015A2 true WO2008087015A2 (de) | 2008-07-24 |
WO2008087015A3 WO2008087015A3 (de) | 2008-09-18 |
Family
ID=39539559
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
PCT/EP2008/000282 WO2008087015A2 (de) | 2007-01-16 | 2008-01-16 | Integrierter schaltkreis |
Country Status (3)
Country | Link |
---|---|
US (1) | US7683655B2 (de) |
DE (1) | DE112008000041B4 (de) |
WO (1) | WO2008087015A2 (de) |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3018604A1 (de) * | 1979-05-17 | 1980-11-20 | Rca Corp | Integrierte klemmschaltung |
EP0085991A2 (de) * | 1982-02-10 | 1983-08-17 | Nec Corporation | Logische Schaltung |
JPS58175324A (ja) * | 1982-04-07 | 1983-10-14 | Nec Corp | 入力回路 |
US5216292A (en) * | 1990-11-06 | 1993-06-01 | Mitsubishi Denki Kabushiki Kaisha | Pullup resistance control input circuit and output circuit |
US5952850A (en) * | 1996-09-25 | 1999-09-14 | Kabushiki Kaisha Toshiba | Input/output circuit and a method for controlling an input/output signal |
US6285209B1 (en) * | 1998-09-16 | 2001-09-04 | Nec Corporation | Interface circuit and input buffer integrated circuit including the same |
Family Cites Families (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2837882C2 (de) * | 1978-08-30 | 1984-03-29 | Siemens AG, 1000 Berlin und 8000 München | Taktformer für integrierte Halbleiter-Digitalschaltungen |
DE2845379C2 (de) * | 1978-10-18 | 1983-09-01 | Siemens AG, 1000 Berlin und 8000 München | Digitale integrierte Halbleiterschaltung |
US5283479A (en) * | 1991-04-30 | 1994-02-01 | Microunity Systems Engineering, Inc. | BiCMOS logic gate having plural linearly operated load FETs |
JPH06209252A (ja) * | 1992-09-29 | 1994-07-26 | Siemens Ag | Cmos入力段 |
JP2001060667A (ja) | 1999-08-24 | 2001-03-06 | Nec Corp | 半導体集積回路 |
-
2008
- 2008-01-16 WO PCT/EP2008/000282 patent/WO2008087015A2/de active Application Filing
- 2008-01-16 DE DE112008000041.7T patent/DE112008000041B4/de active Active
- 2008-01-16 US US12/015,497 patent/US7683655B2/en active Active
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE3018604A1 (de) * | 1979-05-17 | 1980-11-20 | Rca Corp | Integrierte klemmschaltung |
EP0085991A2 (de) * | 1982-02-10 | 1983-08-17 | Nec Corporation | Logische Schaltung |
JPS58175324A (ja) * | 1982-04-07 | 1983-10-14 | Nec Corp | 入力回路 |
US5216292A (en) * | 1990-11-06 | 1993-06-01 | Mitsubishi Denki Kabushiki Kaisha | Pullup resistance control input circuit and output circuit |
US5952850A (en) * | 1996-09-25 | 1999-09-14 | Kabushiki Kaisha Toshiba | Input/output circuit and a method for controlling an input/output signal |
US6285209B1 (en) * | 1998-09-16 | 2001-09-04 | Nec Corporation | Interface circuit and input buffer integrated circuit including the same |
Also Published As
Publication number | Publication date |
---|---|
US7683655B2 (en) | 2010-03-23 |
DE112008000041A5 (de) | 2009-09-17 |
WO2008087015A3 (de) | 2008-09-18 |
DE112008000041B4 (de) | 2023-11-16 |
US20080197875A1 (en) | 2008-08-21 |
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