DE112008000041A5 - Integrierter Schaltkreis - Google Patents

Integrierter Schaltkreis Download PDF

Info

Publication number
DE112008000041A5
DE112008000041A5 DE112008000041T DE112008000041T DE112008000041A5 DE 112008000041 A5 DE112008000041 A5 DE 112008000041A5 DE 112008000041 T DE112008000041 T DE 112008000041T DE 112008000041 T DE112008000041 T DE 112008000041T DE 112008000041 A5 DE112008000041 A5 DE 112008000041A5
Authority
DE
Germany
Prior art keywords
integrated circuit
integrated
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
DE112008000041T
Other languages
English (en)
Other versions
DE112008000041B4 (de
Inventor
Anton Dipl.-Ing. Koch
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Atmel Corp
Original Assignee
Atmel Germany GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Germany GmbH filed Critical Atmel Germany GmbH
Publication of DE112008000041A5 publication Critical patent/DE112008000041A5/de
Application granted granted Critical
Publication of DE112008000041B4 publication Critical patent/DE112008000041B4/de
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/00346—Modifications for eliminating interference or parasitic voltages or currents
    • H03K19/00361—Modifications for eliminating interference or parasitic voltages or currents in field effect transistor circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K19/00—Logic circuits, i.e. having at least two inputs acting on one output; Inverting circuits
    • H03K19/003—Modifications for increasing the reliability for protection
    • H03K19/0033—Radiation hardening
    • H03K19/00338—In field effect transistor circuits
DE112008000041.7T 2007-01-16 2008-01-16 Integrierter Schaltkreis Active DE112008000041B4 (de)

Applications Claiming Priority (5)

Application Number Priority Date Filing Date Title
US88037707P 2007-01-16 2007-01-16
US60/880,377 2007-01-16
DE102007002502 2007-01-17
DE102007002502.7 2007-01-17
PCT/EP2008/000282 WO2008087015A2 (de) 2007-01-16 2008-01-16 Integrierter schaltkreis

Publications (2)

Publication Number Publication Date
DE112008000041A5 true DE112008000041A5 (de) 2009-09-17
DE112008000041B4 DE112008000041B4 (de) 2023-11-16

Family

ID=39539559

Family Applications (1)

Application Number Title Priority Date Filing Date
DE112008000041.7T Active DE112008000041B4 (de) 2007-01-16 2008-01-16 Integrierter Schaltkreis

Country Status (3)

Country Link
US (1) US7683655B2 (de)
DE (1) DE112008000041B4 (de)
WO (1) WO2008087015A2 (de)

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2837882C2 (de) * 1978-08-30 1984-03-29 Siemens AG, 1000 Berlin und 8000 München Taktformer für integrierte Halbleiter-Digitalschaltungen
DE2845379C2 (de) * 1978-10-18 1983-09-01 Siemens AG, 1000 Berlin und 8000 München Digitale integrierte Halbleiterschaltung
US4307306A (en) 1979-05-17 1981-12-22 Rca Corporation IC Clamping circuit
JPS58137331A (ja) 1982-02-10 1983-08-15 Nec Corp インバ−タ回路
JPS58175324A (ja) 1982-04-07 1983-10-14 Nec Corp 入力回路
JP2628942B2 (ja) 1990-11-06 1997-07-09 三菱電機株式会社 プルアップ抵抗コントロール入力回路及び出力回路
US5283479A (en) * 1991-04-30 1994-02-01 Microunity Systems Engineering, Inc. BiCMOS logic gate having plural linearly operated load FETs
JPH06209252A (ja) * 1992-09-29 1994-07-26 Siemens Ag Ｃｍｏｓ入力段
JP3234778B2 (ja) 1996-09-25 2001-12-04 株式会社東芝 入出力回路及びこの入出力回路への信号の入出力方法
JP2000091902A (ja) 1998-09-16 2000-03-31 Nec Corp インタフェース回路及びこれを含む入力バッファ集積回路
JP2001060667A (ja) 1999-08-24 2001-03-06 Nec Corp 半導体集積回路

Also Published As

Publication number Publication date
DE112008000041B4 (de) 2023-11-16
WO2008087015A3 (de) 2008-09-18
US20080197875A1 (en) 2008-08-21
WO2008087015A2 (de) 2008-07-24
US7683655B2 (en) 2010-03-23

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Legal Events

Date Code Title Description
OP8 Request for examination as to paragraph 44 patent law
8127 New person/name/address of the applicant

Owner name: ATMEL AUTOMOTIVE GMBH, 74072 HEILBRONN, DE

R016 Response to examination communication
R081 Change of applicant/patentee

Owner name: ATMEL CORP., US

Free format text: FORMER OWNER: ATMEL AUTOMOTIVE GMBH, 74072 HEILBRONN, DE

Effective date: 20130529

Owner name: ATMEL CORP., SAN JOSE, US

Free format text: FORMER OWNER: ATMEL AUTOMOTIVE GMBH, 74072 HEILBRONN, DE

Effective date: 20130529

R082 Change of representative

Representative=s name: GRUENECKER, KINKELDEY, STOCKMAIR & SCHWANHAEUS, DE

Effective date: 20130529

Representative=s name: GRUENECKER PATENT- UND RECHTSANWAELTE PARTG MB, DE

Effective date: 20130529

R016 Response to examination communication
R016 Response to examination communication
R018 Grant decision by examination section/examining division