Classifications

• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L25/00—Baseband systems
  • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
  • H04L25/40—Transmitting circuits; Receiving circuits
  • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
  • H04L25/4902—Pulse width modulation; Pulse position modulation
• • H—ELECTRICITY
  • H03—ELECTRONIC CIRCUITRY
  • H03C—MODULATION
  • H03C1/00—Amplitude modulation
  • H03C1/36—Amplitude modulation by means of semiconductor device having at least three electrodes
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/69—Spread spectrum techniques
  • H04B1/7163—Spread spectrum techniques using impulse radio
  • H04B1/717—Pulse-related aspects
  • H04B1/7174—Pulse generation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04B—TRANSMISSION
  • H04B1/00—Details of transmission systems, not covered by a single one of groups H04B3/00 - H04B13/00; Details of transmission systems not characterised by the medium used for transmission
  • H04B1/69—Spread spectrum techniques
  • H04B1/7163—Spread spectrum techniques using impulse radio
  • H04B1/7176—Data mapping, e.g. modulation
• • H—ELECTRICITY
  • H04—ELECTRIC COMMUNICATION TECHNIQUE
  • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
  • H04L27/00—Modulated-carrier systems
  • H04L27/02—Amplitude-modulated carrier systems, e.g. using on-off keying; Single sideband or vestigial sideband modulation
  • H04L27/04—Modulator circuits; Transmitter circuits

Definitions

• the present invention relates to a pulse modulation circuit and a pulse modulation method for intermittently generating an AC wave signal according to transmission data.
• FIG. 1 shows a main configuration of a pulse modulation circuit that intermittently operates an oscillation circuit (see Patent Document 1).
• the pulse modulation circuit 10 shown in FIG. 1 is roughly divided into two parts: a short pulse control generation circuit 11 that generates a pulse-like control signal, and an oscillation circuit 12 that oscillates for a short pulse time.
• the input signal that determines the intermittent operation cycle is divided into two signals by a distribution circuit 21 composed of resistors in the short pulse control generation circuit 11, and one signal is directly input to the base end of the transistor 23 and the other signal Is delayed by a predetermined time by the delay circuit 22 and then input to the emitter end of the transistor 23.
• a short pulse control signal is generated in which the input signal power input to the base end of the transistor 23 is also shortened by a time corresponding to the delay of the delay circuit 22.
• the short pulse control signal is input to the oscillation circuit 12, and the oscillator composed of the feedback circuit 32 and the transistor 33 is operated intermittently.
• 31 and 34 are amplifiers, and 35 is a current source.
• Non-Patent Document 1 discloses a technique for differentially operating an oscillation circuit in pairs.
• Figure 2 shows the configuration.
• Patent Document 1 Japanese Patent Laid-Open No. 2005-49200
• Non-Patent Document 1 ELECTRONICS LETTERS 28th April 2005 Vol.41 No.9 "Residua ⁇ carrier— free burst oscillator for automotive UWB radar applications
• intermittent operation is performed by charging and discharging a DC blocking capacitor for individually applying a voltage to each transistor and a stabilization circuit for preventing unnecessary oscillation.
• a DC blocking capacitor for individually applying a voltage to each transistor and a stabilization circuit for preventing unnecessary oscillation.
• the charging state of the DC blocking capacitor and the stabilization circuit changes depending on the interval of intermittent operation, that is, the interval where the pulse signal is not output.
• the oscillation start time and oscillation stop time vary depending on the transmission data string, and the transmission
• a short pulse signal with a uniform pulse width and pulse position cannot be output regardless of the data string.
• a pulse for performing OOK (On Off Keying) modulation in which an AC pulse is output when transmission data is "1" and an AC pulse is not output when transmission data is "0".
• OOK On Off Keying
• the waveform of this AC pulse depends on the immediately preceding transmission data string. In other words, as ⁇ 0 '' continues as the immediately preceding transmission data string, the charge amount of the DC blocking capacitor and the stabilization circuit decreases, and as a result, the rising edge of the AC pulse immediately after that becomes less steep or rises. The timing is slow.
• An object of the present invention is to provide a pulse modulation circuit and a pulse modulation method capable of forming a pulse modulation signal having a desired pulse waveform regardless of a transmission data signal sequence.
• a pulse modulation circuit includes an intermittent operation circuit that intermittently outputs a transmission signal according to a control signal, and the intermittent operation circuit according to transmission data.
• a control circuit that performs switching control between a transmission state in which the first transmission signal is output and an idling state in which the second transmission signal having a lower amplitude or lower frequency than the first transmission signal is output.
• the transmission state is set.
• the parasitic capacitance of the intermittent operation circuit at this time is charged almost uniformly depending on the idling state even if the immediately preceding state is not the transmitting state.
• the Nose waveform of the first transmission signal can be made independent of the immediately preceding transmission data string.
• the first transmission signal having a desired pulse width and abruptly generated at a desired timing can be generated without being influenced by the transmission data string. It is possible to obtain good reception quality by suppressing the degradation of reception performance due to the fluctuation of the tatum and timing jitter.
• the intermittent operation circuit is operated so as to generate a second transmission signal having a low amplitude or a low frequency, so that a desired pulse waveform can be generated while minimizing power consumption.
• a pulse modulation signal having the same can be generated.
• a pulse modulated signal having a desired pulse waveform can be formed without being influenced by a transmission data signal sequence.
• FIG. 1 is a block diagram showing a main configuration of a conventional pulse modulation circuit.
• FIG. 2 is a block diagram showing the main configuration of a conventional pulse modulation circuit
• FIG. 3 is a block diagram showing a main part configuration of a pulse modulation circuit according to the first embodiment of the present invention.
• FIG. 4 is a block diagram showing a main part configuration of a control signal generation unit according to the first embodiment.
• FIG. 5 is a diagram showing signal waveforms of a control signal and a transmission signal in the first embodiment
• FIG. 6 is a block diagram showing a main configuration of the intermittent operation circuit according to the first embodiment.
• FIG. 7 is a block diagram showing another main configuration of the intermittent operation circuit according to the first embodiment.
• FIG. 8 is a block diagram showing another main configuration of the intermittent operation circuit according to the first embodiment.
• FIG. 9 is a block diagram showing another main configuration of the control signal generation unit in the above embodiment.
• FIG. 10 is a diagram showing signal waveforms of a control signal and a transmission signal in the first embodiment
• FIG. 11 is a block diagram showing a main configuration of a control signal generation section according to Embodiment 2 of the present invention.
• FIG. 12 is a block diagram showing a main configuration of a variable band limiting circuit according to Embodiment 2.
• FIG. 13 is a diagram showing signal waveforms of a control signal and a transmission signal in the second embodiment
• FIG. 14 is a block diagram showing a main configuration of an additional signal generation unit according to Embodiment 3 of the present invention.
• FIG. 15 is a block diagram showing a main configuration of an AND circuit according to the third embodiment.
• FIG. 16 is a diagram showing signal waveforms of a control signal and a transmission signal in the third embodiment
• FIG. 17 is a block diagram showing a main configuration of a pulse modulation circuit according to Embodiment 4 of the present invention.
• FIG. 18 is a diagram showing signal waveforms of a control signal and a transmission signal in the fourth embodiment.
• OOK On Off Keying modulation is performed so that an AC pulse is output when the transmission data is ⁇ 1 '' and no AC pulse is output when the transmission data is ⁇ 0 ''.
• OOK On Off Keying
• FIG. 3 shows the main configuration of the pulse modulation circuit according to Embodiment 1 of the present invention.
• the pulse modulation circuit 100 shown in FIG. 3 includes a control signal generation unit 110 and an intermittent operation circuit 120.
• FIG. 4 shows a main configuration of the control signal generation unit 110.
• the control signal generation unit 110 shown in FIG. 4 includes a transmission data determination unit 1101, a delay adjustment unit 1102, an amplitude adjustment unit 1103, and a synthesis unit 1104.
• the control signal generation unit 110 adds transmission data S11 to the transmission data S11.
• the control signal S 12 is generated and output to the intermittent operation circuit 120.
• each part of the control signal generation unit 110 will be described with reference to a timing chart of signal waveforms in FIG.
• Transmission data determination unit 1101 determines whether transmission data SI 1 (FIG. 5 (a)) is “1” or “0”, and outputs when transmission data S11 is “1”.
• a first control signal S14 (Fig. 5 (b)) that rises at the same timing as the start timing of the transmission pulse signal and has a pulse width equal to the pulse width of the transmission pulse signal is generated and sent to the synthesis unit 1104. Output.
• the transmission data S11 is “0”, if the transmission data S11 is “1”, it rises at the same timing as the start timing of the output transmission pulse signal, and the pulse of the transmission pulse signal
• a control signal S 15 (Fig. 5 (c)) having a pulse width equal to the width is generated and output to the delay adjustment unit 1102.
• a 1-input 2-output logic circuit is used for the transmission data determination unit 1101, and one of the outputs is inverted according to the transmission data S11 to generate the first control signal S14 and the control signal S15. You may do it.
• transmission data determination section 1101 transmits transmission pulses within a pulse period.
• the first control signal S14 and the control signal S15 are generated according to the presence or absence of the signal.
• the delay adjustment unit 1102 delays the start timing of the control signal S15 output from the transmission data determination unit 1101 by a predetermined time, and the delayed control signal S16 (FIG. 5 (d)) is an amplitude adjustment unit 1103. Output to.
• the delay time of the control signal S16 will be described later.
• Amplitude adjustment section 1103 reduces the amplitude of control signal S16 output from delay adjustment section 1102, and uses control signal S17 (FIG. 5 (e)) after amplitude adjustment as a second control signal as a second control signal. Output to 1104. That is, when the transmission data S11 is “0”, the second control signal S17 having an amplitude level smaller than the amplitude level of the first control signal S14 generated when the transmission data S11 is “1”. Is generated. The amplitude level of the control signal S17 will be described later.
• the combining unit 1104 combines the first control signal S14 and the second control signal S17, and outputs the combined control signal S12 (FIG. 5 (f)) to the intermittent operation circuit 120.
• FIG. 6 shows a main configuration of the intermittent operation circuit 120.
• the intermittent operation circuit 120 shown in FIG. 6 includes an oscillator 1200 having a resonator 1201, a transistor 1202, a noise terminal 1203, and a DC (Direct Current) capacitor 1204, and operates intermittently according to a control signal S12. To generate a pulse signal S13.
• a control signal S12 To generate a pulse signal S13.
• each part of the intermittent operation circuit 120 will be described with reference to the timing chart of the signal waveform in FIG. 5 again.
• the output side of the resonator 1201 is connected to the gate end side of the transistor 1202, and one terminal of the noisy terminal 1203 and the DC cut capacitor 1204 are connected to the drain end side of the transistor 1202.
• the control signal S12 output from the control signal generator 110 is output to the gate terminal of the transistor 1202.
• a voltage is applied to the gate terminal while the voltage value of the control signal S12 is on, and accordingly, a current flows between the source and drain.
• the parasitic capacitance of the transistor 1202 is charged by the current flowing between the source and drain.
• a circuit current flows along with the source / drain current, the oscillation signal is amplified by this circuit current, and the amplified oscillation signal force S pulse signal S13 (FIG. 5 (g)) is output.
• the first oscillation signal (FIG. 5 (i)) is output from the oscillator 1200 (hereinafter “oscillation”).
• the second control signal causes the oscillator 1200 to output the second oscillation signal (Fig. 5 (j)) when the transmission data S11 is "0".
• the first and second oscillation signals are output as the pulse signal S13.
• the voltage is applied to the gate terminal by the control signal S12 obtained by combining the first control signal and the second control signal, so that the transistor 120 2 parasitic capacitance is charged.
• the parasitic capacitance of the transistor 1202 is precharged due to the idling state, so that it is generated immediately after the state where the first oscillation signal is not generated continues.
• the rise of the first oscillation signal can be made steep (Fig. 5 (i)).
• the transistor 1202 is operated in an oscillation state only while the first control signal S14 generated when the transmission data S11 is “1” is on.
• the transistor 1202 depends on whether or not the previous transistor 1202 is in an oscillating state, that is, depending on whether the transmission data S11 is “0” or “1”. Since the amount of charge of the parasitic capacitance of 1202 is different, the start timing and pulse width of the pulse signal S13 will vary (Fig. 5 (h)).
• the transmission data S11 is “0”
• a voltage is applied to the gate terminal of the transistor 1202 by the second control signal, and the transistor 1202 is turned on. Since the parasitic capacitance is charged in the idling state, the parasitic capacitance of the transistor 1202 can be charged almost uniformly without being influenced by the transmission data S11. Instead, the first oscillation signal with a steep rise can be generated (Fig. 5 (i)).
• the transmission data Sl l is output to the transmission data determination unit 1101 of the control signal generation unit 110.
• OOK modulation is performed as the data string “0100001110010” force transmission data S 11 will be described.
• the transmission data determination unit 1101 rises at a timing that coincides with the start timing of the transmission pulse signal to be output, and is equal to the pulse width of the transmission pulse signal.
• a first control signal S 14 having a pulse width (FIG. 5 (b)) is generated and output to the synthesis unit 1104.
• transmission data S11 is “0”
• transmission data S11 is “1”
• the pulse width of the transmission pulse signal A control signal S15 (FIG. 5 (c)) having a pulse width equal to is generated and output to the delay adjustment unit 1102.
• the control signal S15 is further delayed by a predetermined time by the delay adjusting unit 1102, and the delayed control signal S16 (FIG. 5 (d)) is output to the amplitude adjusting unit 1103. Then, the amplitude level of the control signal S16 is adjusted by the amplitude adjusting unit 1103, and the control signal after the level adjustment is output to the synthesizing unit 1104 as the second control signal S17 (FIG. 5 (e)).
• the first control signal S14 and the second control signal S17 are combined by the combining unit 1104, and the combined control signal S12 (Fig. 5 (f)) is the transistor of the intermittent operation circuit 120. Output to the gate end of 1202. As a result, a voltage is applied to the gate terminal of the transistor 1202 only when the control signal S12 is on, a source-drain current starts flowing, and the parasitic capacitance of the transistor 1202 is charged. Then, a circuit current starts flowing along with the source / drain current, the oscillation signal is amplified by this circuit current, and the amplified oscillation signal is output as a pulse signal S 13 (FIG. 5 (g)).
• the first control signal S14 causes the transistor 1202 to oscillate and output the first oscillation signal (FIG. 5 (i))
• the second control signal S17 causes the transistor 1202 to idle.
• the second oscillation signal (FIG. 5 (j)) is output in the state, and the first oscillation signal and the second oscillation signal are output from the oscillator 1200 as the pulse signal S13 (FIG. 5 (g)).
• the control signal S17 When the control signal S17 is turned off, the parasitic capacitance of the charged transistor 1202 is discharged.
• the timing at which the parasitic capacitance starts to be charged and the timing at which the charged parasitic capacitance starts to be discharged are determined by the ON / OFF timing of the control signal S 17, that is, the delay time adjusted by the delay adjusting unit 1102.
• the start timing of the control signal S17 is not necessarily delayed. There is no need.
• the control signal S17 is turned off, the parasitic capacitance of the transistor 1202 starts to discharge, so that the earlier the start timing of the control signal S17 is, the earlier the timing at which discharge starts. Therefore, it is necessary to fully charge the parasitic capacitance of the transistor 1202 while the amplitude level of the control signal S 17 is increased and the control signal S 17 is turned on.
• the start timing of the control signal S17 is delayed.
• the timing at which the transistor 1202 starts to charge and the timing at which it starts to discharge are both delayed. Therefore, as compared with the case where the control signal S17 is not delayed, the transistor 1202 can be charged to the same extent even when the amplitude level of the control signal S17 is low, so that power consumption can be reduced.
• the parasitic capacitance of the transistor 1202 after discharging only needs to be charged by an amount that can make the rising edge of the first oscillation signal steep at the start timing of the transmission pulse signal to be output.
• the amount of charge required depends on the characteristics of the transistor 1202. Note that the amount of charge of the transistor 1202 after discharging is the timing at which the transistor 1202 starts to charge, That is, it depends on the timing at which the transistor 1202 is switched to the idling state. The amount of charge of the transistor 1202 after discharging further depends on the amplitude level applied to the gate terminal of the transistor 1202.
• the required charge amount is calculated based on the characteristics of the transistor 1202, and the timing for switching the transistor 1202 to the idling state based on the required charge amount, that is, the delay time in the delay adjustment unit 1102 and the amplitude adjustment.
• Part 1 103 sets the amplitude adjustment amount.
• the delay time and voltage are adjusted to generate the control signal S 17 when the transmission data S 11 is “0”, and the pulse width of the control signal S 17 is not adjusted.
• the delay width may be further adjusted in the delay adjustment unit 1102 so that the control signal S 17 has a narrower width.
• the control signal S 17 has a narrower pulse width, the period during which the intermittent operation circuit is idling when the transmission data S11 is "0". Force The intermittent operation circuit is in the oscillation state when the transmission data S11 is "1". Since it is shorter than the period, power consumption can be reduced.
• the adjustment of the pulse width can be realized, for example, by using an AND logic circuit.
• the voltage is applied to the gate terminal by the second control signal S17, so that as shown in FIG. 5 (j).
• the second oscillation signal which is essentially unnecessary as a transmission pulse signal, is generated at this time.
• the second oscillation signal can be eliminated by providing a switch or the like after the intermittent operation circuit 120. wear.
• FIG. 7 shows an example of a main configuration of the intermittent operation circuit 120 in which a switch is provided at the subsequent stage of the oscillator in order to remove the second oscillation signal.
• the intermittent operation circuit 120 shown in FIG. 7 has a configuration in which a switch 1210 and a terminal load 1211 are added to FIG. One terminal is connected to the buffer amplifier 130, and the other terminal is connected to the termination load 1211.
• Transmission data determination unit 1101 of control signal generation unit 110 outputs control signal S14 to combining unit 1104 and outputs control signal S14 to switch 1210 of intermittent operation circuit 120.
• the combining unit 1104 of the control signal generating unit 110 outputs the control signal S12 to the gate terminal of the transistor 1202 of the intermittent operation circuit 120 as described above.
• the switch 1210 switches the output destination of the oscillation signal to either the termination load 1211 or the buffer amplifier 130 according to the control signal S14 output from the transmission data determination unit 1101 of the control signal generation unit 110. Specifically, when the control signal S14 is on, the switch 1210 switches the output destination of the oscillation signal to the buffer amplifier 130, and when the control signal S14 is off, the switch 1210 selects the output destination of the oscillation signal. Switch to terminal load 1211.
• the first oscillation signal (FIG. 5 (i)) output from the transistor 1202 is amplified by the buffer amplifier 130 only when the control signal S14 is on, and when the control signal S14 is off, the switch 1210 is switched to the termination load 1211, and the amplitude level of the second oscillation signal (FIG. 5 (j)) can be reduced.
• the signal power ratio between the second oscillation signal output when transmission data S11 is "0" and the first oscillation signal output when transmission data S11 is "1" is the switch 1210 Determined by isolation. Therefore, by providing a switch having an isolation that increases the signal power ratio, it is possible to easily remove the unnecessary second oscillation signal on the receiving side by threshold determination.
• the impedance of the termination load 1211 is smaller than the impedance of the buffer amplifier 130, or to set the loop gain of the transistor 1202 to be small, the power of the second oscillation signal is reduced.
• the signal power ratio described above may be decreased to increase the above-mentioned signal power ratio so that the second oscillation signal unnecessary on the receiving side can be easily removed by threshold determination or the like.
• FIG. 8 shows an example of a main configuration of the intermittent operation circuit 120 in which a multiplier is provided at the subsequent stage of the oscillator in order to remove the second oscillation signal.
• the intermittent operation circuit 120 shown in FIG. 8 has a configuration in which a multiplier 1220 is added to FIG. 6, and the multiplier 1220 includes matching circuits 1221-1, 1221-2 and a transistor 1222. And a noise terminal 1223 and a DC cut capacitor 1224.
• the matching circuit 1221-1 is connected to the input end side of the transistor 1222, and the matching circuit 1221-2 is connected to the output end side of the transistor 1222.
• Matching circuits 1221-1 and 1221-2 are matched to different frequencies. For example, matching circuit 1221-1 matching at 13 GHz is used at the input terminal of transistor 1222, and the output terminal of transistor is open at 13 GHz or 13 GHz. When the matching circuit 1221-2 that is short-circuited at is used, a 26 GHz transmission signal S 18 is generated.
• the amplitude level of the second oscillation signal can be lowered by switching the operation state of the transistor 1222 of the multiplier 1220 in accordance with the control signal S14 and changing the conversion efficiency.
• the control signal S14 is output to the gate terminal of the transistor 1222, and the gate bias is changed only for the time when the control signal S14 is turned off, the drain current flowing through the transistor 1222 is reduced, the amplification factor is lowered, and the second oscillation.
• the oscillator 1200 is provided, the intermittent operation circuit 120 that intermittently outputs the oscillation signal S13 according to the control signal S12, and the transmission data S11, A control signal generator 110 that controls switching of the intermittent operation circuit 120 between an oscillation state in which the first oscillation signal is output and an idling state in which the second oscillation signal having a lower amplitude than the first oscillation signal is output;
• the parasitic capacitance of the intermittent operation circuit when the oscillation state is set is almost uniformly charged by idling even if the immediately preceding state is not the oscillation state.
• the pulse waveform of the first oscillation signal can be made independent of the immediately preceding transmission data string.
• the first oscillation signal having a desired pulse width and generated steeply at a desired timing can be generated without being influenced by the transmission data string. It is possible to suppress the degradation of reception performance due to fluctuations in timing and timing jitter, and to obtain good reception quality.
• the intermittent operation circuit is operated so as to generate the second oscillation signal with a low amplitude, so that a pulse modulation signal having a desired pulse waveform is generated while minimizing power consumption. can do.
• the intermittent operation circuit 120 when the transmission data S11 is “0”, the intermittent operation circuit 120 is operated to output the second oscillation signal having a lower amplitude than the first oscillation signal.
• the transmission data S11 is “0”
• the second oscillation signal having a frequency lower than that of the first oscillation signal is generated.
• the intermittent operation circuit 120 may be operated. In this case, an unnecessary second oscillation signal can be easily removed by providing a band limiting filter in the subsequent stage of the missing operation circuit 120.
• the oscillator 1200 is used as the intermittent operation circuit 120 .
• the intermittent operation circuit 120 is configured by combining the oscillator and the amplifier, and only the amplifier is intermittently generated by the control signal S12. You may make it operate.
• the oscillator oscillates continuously without any intermittent operation.
• a PLL Phase lock Loop
• a dielectric resonator is used as the oscillator, the oscillation frequency and the oscillation output can be stabilized.
• the current switch 45-1 is generated by the short pulse signal output from the short pulse control generation circuit 43 to the multivibrator 44.
• 45-2 causes the current flowing from constant current source 46 to flow alternately to transistors 41-1, 1, 41-2, so that transistors 41-1, 1, 2 2 operate intermittently and operate as differential oscillators. Since the terminals 40-1 and 40-2 are configured to output signals with opposite phases, the oscillation frequency changes greatly due to individual differences in the current switches 45-1 and 45-2 and impedance variations due to temperature.
• the oscillator oscillates continuously without intermittent operation, so that the oscillation frequency can be stabilized. It is out.
• the intermittent operation circuit 120 includes an oscillator and an amplifier, it is possible to intermittently operate both the oscillator and the amplifier according to the control signal S12. In this case, only the amplifier is used as the control signal. Compared with intermittent operation according to S12, intermittent operation circuit 12 0 The overall power consumption can be reduced, and the signal power ratio can be further increased by the amplifier, so that the power of the unnecessary second oscillation signal can be kept small. Further, only the oscillator may be intermittently operated by the control signal S12 and the amplifier may be intermittently operated by the control signal S14.In this case, the signal power ratio between the first oscillation signal and the second oscillation signal is set. This makes it possible to make the signal larger, and the receiving side can reliably demodulate the desired first oscillation signal by threshold determination.
• the operating state of the intermittent operation circuit 120 including a modulation unit that generates an ASK (Amplitude Shift Keying) modulation signal or a PPM modulation signal may be controlled.
• the intermittent operation circuit 120 can generate a pulse signal with a steep rise, so that when the transmission data is assigned to the generation position of the pulse signal as in the PPM method, the intermittent operation circuit 120 is not connected to the reception side. ⁇ ⁇ This is particularly useful because it makes it possible to reliably identify the pulse generation position.
• the control signal generation unit 110A includes a transmission data determination unit 1101, a delay adjustment unit 1105, a branch circuit 1106, a synthesis unit 1104, a logic (NOR) circuit 1107, a delay adjustment unit 1102, and an amplitude adjustment unit 1103. Configured.
• NOR logic
• Transmission data determination unit 1101 determines whether transmission data SI 1 (Fig. 10 (a)) is “1” or “0”, and outputs when transmission data S11 is "1"
• a first control signal S14 (Fig. 10 (b)) that rises at the same timing as the start timing of the transmission pulse signal and has a pulse width equal to the pulse width of the transmission pulse signal is generated, and the delay adjustment unit 1105 Output to.
• the transmission data S11 is “0”, if the transmission data S11 is “1”, it rises at a timing that coincides with the start timing of the output transmission pulse signal.
• a control signal S 15 (FIG. 10 (d)) having a pulse width equal to the pulse width of the transmission pulse signal is generated and output to the logic (NOR) circuit 1107.
• a 1-input 2-output logic circuit is used for the transmission data determination unit 1101 and one of the outputs is inverted according to the transmission data S11 to generate the control signal S14 and the control signal S15. May be.
• transmission data determination section 1101 When applied to pulse position modulation (PPM) that changes the generation timing position of a transmission pulse signal according to transmission data, transmission data determination section 1101 transmits transmission pulses within a pulse period. Control signal S14 and control signal S15 should be generated according to the presence or absence of the signal.
• PPM pulse position modulation
• Delay adjustment section 1105 delays the start timing of control signal S14 output from transmission data determination section 1101 by one pulse, and branches delayed control signal S14A (Fig. 10 (c)) to a branch circuit. Output to 1106.
• the branch circuit 1106 branches the control signal S14A into two branches, outputs one to the synthesis unit 1104 as the first control signal, and outputs the other to the logic (NOR) circuit 1107.
• the logic (NOR) circuit 1107 includes a control signal S14B based on the control signal S14A and the control signal S15.
• the delay adjustment unit 1102 delays the start timing of the control signal S14B output from the logic (NOR) circuit 1107 by a predetermined time, and amplitude-adjusts the delayed control signal S16A (FIG. 10 (f)). Part 1103. Since the delay time of the control signal S16A is the same as that of the control signal S16, the description thereof is omitted.
• Amplitude adjustment section 1103 reduces the amplitude of control signal S16A output from delay adjustment section 1102, and uses control signal S17A (FIG. 10 (g)) after amplitude adjustment as a second control signal for combining section 1104. Output to.
• control signal S17A FOG. 10 (g)
• the amplitude level is smaller than the amplitude level of the first control signal S14A generated when the transmission data S11 is “1”.
• a second control signal S17A is generated. Note that the amplitude level of the control signal S17A is the same as that of the control signal S17, and thus the description thereof is omitted.
• Synthesizer 1104 synthesizes first control signal S14A and second control signal S17A, and synthesizes them. By outputting the subsequent control signal S12A (FIG. 10 (h)) to the intermittent operation circuit 120, S13A (FIG. 10 (i)) is output from the intermittent operation circuit 120 as a pulse signal.
• the intermittent operation circuit can be idled only in the case of “0” immediately before the transmission data becomes “1”. As a result, the rising edge of the first oscillation signal output in the oscillation state can be clarified, and the start timing of the pulse signal can be reliably acquired on the reception side.
• the intermittent operation circuit is controlled to the idling state only when the transmission data immediately after becomes “1”, the operation time of the intermittent operation circuit is suppressed, and the power consumption of the intermittent operation circuit is further reduced. be able to.
• FIG. 11 is a block diagram showing a configuration example of the pulse modulation circuit according to the second embodiment of the present invention.
• a pulse modulation circuit 200 shown in FIG. 11 includes a control signal generation unit 210 and an intermittent operation circuit 120.
• the control signal generation unit 210 includes a branch circuit 2101, a waveform shaping unit 2102, and an additional signal generation unit 2103.
• the control signal generation unit 210 generates a control signal D9 according to a control signal D1 (first data signal) output from a generation circuit (not shown), and outputs the control signal D9 to the intermittent operation circuit 120.
• a generation circuit not shown
• a signal other than a pulse may be generated.
• the branch circuit 2101 branches the control signal D1 from the generation circuit (not shown), and the control signal D2
• the waveform shaping unit 2102 shapes the control signal D2 so that an output signal D7 described later is added to a predetermined data signal sequence of the control signal D2.
• the predetermined data signal sequence refers to, for example, a signal sequence when “1” is followed by “0” (the same applies hereinafter).
• the waveform shaping unit 2102 includes a pulse modulation unit 2104, a variable band limiting circuit 2105, and a limiter circuit 2106.
• the pulse modulation unit 2104 is controlled by the branch circuit 2101.
• Control signal D2 is pulse modulated.
• the pulse modulation unit 2104 when the pulse width of the control signal Dl (D2), which is transmission data, is T, the pulse modulation unit 2104 generates a control signal D4 having a pulse width that is narrower than the pulse width T by a predetermined time.
• variable band limiting circuit 2105 irregularly limits the band of the output signal D4 of the pulse modulation unit 2104 based on a control signal D7 described later, as will be described later.
• Limiter circuit 2106 limits the amplitude of control signal D8, which is the output of variable band limiting circuit 2105, and outputs the limited control signal D9 to intermittent operation circuit 120.
• the additional signal generation unit 2103 generates a control signal D7 (second data signal) in synchronization with a predetermined data signal sequence set in advance among the control signals D1 from the control signal generation unit 210.
• the additional signal generation unit 2103 includes an inverter circuit 2107, a delay circuit 2108,
• the inverter circuit 2107 inverts the control signal D3 from the branch circuit 2101 and outputs it to the delay circuit 2108.
• the delay circuit 2108 delays the control signal D5, which is the output of the inverter circuit 2107, by a predetermined time, and outputs the delayed signal to the pulse modulation unit 2109.
• Pulse modulation section 2109 performs pulse modulation on control signal D6, which is the output of delay circuit 2108, and provides control signal D7 (second data signal) after the pulse modulation to variable band limiting circuit 210.
• the pulse modulation unit 2109 when the pulse width of the control signal Dl (D2) that is transmission data is T, the pulse modulation unit 2109 pulses a width narrower by a predetermined time than the pulse width T. Generate control signal D7 for width.
• the intermittent operation circuit 120 inputs the control signal D9 waveform-shaped by the waveform shaping unit 2102 to charge the input capacitance, and intermittently oscillates the control signal D9 when a predetermined input capacitance value is reached. Output a modulation signal.
• the intermittent operation circuit 120 includes, for example, an FET, and when the input capacity of the FET (capacitance of the input terminal of the FET) reaches a predetermined value, the FET is intermittently operated. on
• the intermittent operation circuit 120 oscillates intermittently, and the control signal D9 is modulated and output as the modulation signal D10.
• FIG. 12 is a diagram illustrating a circuit example of the variable band limiting circuit 2105.
• a variable band limiting circuit 2105 includes a resistor 2 at one end of an inductance 2110. 11 1 and varactor diode (variable diode) 2112 are connected in parallel. In the inductor diode 2112, one end of a resistor and a cathode of a diode are commonly connected to one end of a capacitor. The anode of the diode is grounded.
• the capacitance of the varactor diode 2112 changes according to the reverse voltage applied to the anode of the diode of the varactor diode 2112. Therefore, the circuit impedance of the variable band limiting circuit 2105 including the varactor diode 2112, the inductor 2110, and the resistor 2111 changes. Therefore, the cutoff frequency power of the variable band limiting circuit 2105 changes according to the values of the output signals D4 and D7 of the pulse modulation units 2104 and 2109.
• FIG. 13 is a diagram showing an example of an output waveform of each part of the pulse modulation circuit 200.
• the delay time such as the transmission time and the processing time is neglected.
• synchronization is achieved by a delay circuit not shown (the same applies to other embodiments). .
• control signal D 1 that is transmission data is input to control signal generation section 210.
• the control signal D1 in FIG. 13 (a) is, for example, a pulse signal having a pulse width T.
• the branch circuit 2101 branches the control signal D1 and outputs two control signals D2 and D3. These output characteristics (amplitude and period) are the same as the control signal D1 in Fig. 13 (a) (see Fig. 13 (b) and (c)).
• pulse modulation section 2104 performs pulse modulation on control signal D 2 from branch circuit 2101, and outputs control signal D 4 shown in FIG. 13 (d) to variable band limiting circuit 2105.
• the pulse width of the control signal D4 is narrower than the pulse width T by a predetermined time (for example, oc).
• the inverter circuit 2107 inverts the control signal D3 from the branch circuit 2101 and outputs the control signal D5 shown in FIG. 13 (e) to the delay circuit 2108. Then, the delay circuit 2108 delays the control signal D5 in FIG. 13 (e) by a predetermined time (for example, T), and outputs the control signal D6 shown in FIG. 13 (f) to the pulse modulation unit 2109. At this time, the control signal D6 rises at the timing of rising when the control signal D3 in FIG. 13 (c) changes from “0” to “1”.
• the control signal D6 has a pulse width of T.
• pulse modulation section 2109 performs pulse modulation on control signal D6 in FIG. 13 (f), and outputs control signal D7 shown in FIG. 13 (g) to variable band limiting circuit 2105.
• control signal D7 Is narrower than the pulse width T by a predetermined time (for example, ⁇ ). That is, the pulse width of the control signal D7 is equal to the pulse width of the control signal D4 in FIG.
• variable band limiting circuit 2105 limits the band of the control signal D4 in FIG. 13 (d) in synchronization with the control signal D7 in FIG. 13 (g), and the control signal shown in FIG. 13 (h) D8 is output to limiter circuit 21 06.
• the control signal D7 in FIG. 13 (g) is input to the varactor diode 2112 (see FIG. 12) of the variable band limiting circuit 2105, the timing at which the signal level of the control signal D7 changes (“0” ⁇ “1 “,“ 1 ” ⁇ “ 0 ”), the circuit impedance of the variable band limiting circuit 2105 changes, and the cut-off frequency becomes lower.
• control signal D8 in FIG. 13 (h) is output from the variable band limiting circuit 2105.
• the control signal D8 in FIG. 13 (h) is formed by overshooting the ringing signal at the rising portion of the control signal D7 (the portion in which “1” is followed by “0”). .
• the circuit impedance is set so that the frequency component of the ringing signal is preliminarily specified.
• the frequency component of the ringing signal is the same as or approximately the same (substantially the same) as the oscillation frequency of the intermittent operation circuit 120.
• the limiter circuit 2106 receives the control signal D8 in FIG. 13 (h), and limits the negative amplitude of the control signal D8. Then, the limiter circuit 2106 outputs the control signal D9 shown in FIG. 13 (i) to the intermittent operation circuit 120. At this time, as shown in FIG. 13 (i), the amplitude of the rising edge of the control signal D9 (the portion in which the “1” signal follows “0”) is represented by the overshooting ringing signal. 13 It is larger than the control signal D2 in (b).
• the intermittent operation circuit 120 receives the control signal D9 shown in FIG. 13 (i), intermittently oscillates, and outputs the modulation signal D10 shown in FIG. 13 (j). At this time, the modulation signal D10 rises substantially uniformly regardless of the order of the data signal sequence. This is based on the following reasons. That is, in the control signal D9 in FIG. 13 (i) input to the intermittent operation circuit 120, when “1” follows “0”, the ringing signal is overshot at the rising edge of “1”. Is selected.
• the charging time of the input capacity of the intermittent operation circuit 120 to which the overshooted control signal D9 is input (the time required to reach a predetermined input capacity value) is the same as in the case of other data signal sequences. Therefore, the communication quality can be maintained regardless of the data signal sequence.
• the pulse modulation circuit 200 includes a predetermined data signal string (for example, “0” ⁇ “1”) that is set in advance among the generated control signal D1.
• the control signal D7 is generated in synchronization with Further, the pulse modulation circuit 200 shapes the waveform of the control signal D1 so that the control signal D7 is added to a predetermined data signal sequence of the control signal D1. Then, the pulse modulation circuit 200 inputs the waveform-shaped control signal D9 to charge the input capacitance, and when the predetermined input capacitance value is reached, the control signal D9 is intermittently oscillated to generate the modulation signal D10. Output. For this reason, since the waveform of the control signal D1 is formed for a predetermined data signal string, the input capacity of the intermittent operation circuit 120 reaches the predetermined input capacity value accordingly.
• the charging time of the input capacitor is constant regardless of the data signal sequence, and the rising edge of the modulation signal D10 is performed at a substantially constant timing. Therefore, communication quality can be maintained regardless of the data signal sequence.
• variable band limiting circuit 2105 has been described as including the varactor diode 2112.
• the present invention is not limited to this as long as the cutoff frequency can be varied.
• the variable band limiting circuit 2105 may be configured by combining variable resistors and variable inductances.
• predetermined data signal sequence described above may be applied to other data signal sequences, for example, in the case of “0” ⁇ “1”.
• the modulator in the third embodiment is different from the second embodiment in that it has an additional signal generation unit 310 shown in FIG. 14 instead of the additional signal generation unit 2103 in the second embodiment.
• the other entire configuration of the pulse modulation circuit is the same as that of the second embodiment. So in the following Will be described in detail the configuration of the additional signal generation unit 310.
• FIG. 14 is a block diagram showing a configuration example of the additional signal generation unit 310 included in the pulse modulation circuit in the third embodiment. Note that the same parts as those of the second embodiment are denoted by the same reference numerals, and redundant description is appropriately omitted.
• the additional signal generation unit 310 branches the control signal D3 from the branch circuit 2101 and pulse-modulates the control signal D31 and the branch circuit 3101 that outputs the control signals D31 and D32.
• a pulse modulation unit 3102 and a delay circuit 3103 that delays a control signal D33 that is an output of the pulse modulation unit 3102 are included.
• the additional signal generation unit 310 includes an inverter circuit 31 that inverts the control signal D32.
• pulse modulation unit 3105 that performs pulse modulation on the control signal D35 that is the output of the inverter circuit 3104.
• the additional signal generation unit 310 outputs a logical product (AND) circuit 3106 that outputs a logical product of the control signal D34 output from the delay circuit 3103 and the control signal D36 output from the pulse modulation unit 3105. And a delay circuit 3107 for delaying and outputting the control signal D37, which is the output of the AND circuit 3106.
• a logical product (AND) circuit 3106 that outputs a logical product of the control signal D34 output from the delay circuit 3103 and the control signal D36 output from the pulse modulation unit 3105.
• a delay circuit 3107 for delaying and outputting the control signal D37, which is the output of the AND circuit 3106.
• FIG. 15 is a diagram showing a circuit example of the logical product circuit 3106.
• the AND circuit 3106 includes two diodes 3108 and 3109 and a resistor 3110. Specifically, the force sword of the diode 3108 is connected to the input terminal T2 of the AND circuit 3106, and the force sword of the diode 3109 is connected to the input terminal T1 of the AND circuit 3106.
• the anode of each of the diodes 3108 and 3109 and one end of the resistor 3110 are commonly connected to the output terminal T1 of the AND circuit 3106.
• FIG. 16 is a diagram illustrating an example of an output waveform of each unit of the additional signal generation unit 310.
• branch circuit 3101 branches control signal D3 (see FIG. 13 (c)) and outputs two control signals D31 and D32. These output characteristics are the same as the control signal D3 in Fig. 13 (c) ( Figure 16 (a) (b)).
• pulse modulating section 3102 performs pulse modulation on control signal D31 from branch circuit 3101 and outputs control signal D33 shown in FIG. 16 (c) to delay circuit 3103.
• the pulse width of the control signal D 33 is narrower than the pulse width T by a predetermined time (for example, a).
• the delay circuit 3103 delays the control signal D33 in FIG. 16C by a predetermined time (for example, T), and outputs the control signal D34 shown in FIG. 16D to the AND circuit 3106.
• inverter circuit 3104 inverts control signal D32 from branch circuit 3101 and outputs control signal D35 shown in FIG. 16 (e) to pulse modulation section 3105. Then, the pulse modulation unit 3105 performs pulse modulation on the control signal D35 shown in FIG. 16 (e) and outputs the control signal D36 shown in FIG. 16 (f) to the AND circuit 3106. At this time, the control signal D36 rises at the timing when it rises when the control signal D32 in FIG. 16 (b) changes from 0 to 1.
• the control signal D 36 has a pulse width of T.
• the AND circuit 3106 receives the control signal D34 in FIG. 16 (d) and the control signal D36 in FIG. 16 (f), and sends the control signal D37 shown in FIG. 16 (g) to the delay circuit 3107. Output to.
• the AND circuit 3106 outputs to the delay circuit 3107 a control signal D37 (see FIG. 16 (g)) that becomes 1 when the two pulse signals D34 and D36 are given as inputs.
• the delay circuit 3107 delays the control signal D37 in FIG. 16 (g) for a predetermined time (eg, T).
• a predetermined time eg, T
• the control signal D7 (see FIG. 16 (h)) having the same characteristics as the control signal D7 shown in FIG. 13 (g) is obtained as the output of the delay circuit 3107.
• delay circuit 3107 outputs control signal D7 in FIG. 16 (h) to variable band limiting circuit 2105, whereby the same effect as in the second embodiment can be obtained. That is, communication quality can be maintained regardless of the data signal sequence of the control signal D1.
• the control signal generation unit 410 in the fourth embodiment is different from the waveform shaping unit 2102 and the additional signal generation unit 2103 in the second embodiment in that it includes a waveform shaping unit 411 and an attached calo signal generation unit 412 shown in FIG. This is different from the second embodiment.
• the overall configuration of the other pulse modulation circuits is the same as that of the second embodiment. Therefore, hereinafter, the configuration of the waveform shaping unit 411 and the additional signal generation unit 412 will be mainly described.
• FIG. 17 is a block diagram showing a configuration example of the pulse modulation circuit 400 according to the fourth embodiment. Note that the same parts as those in Embodiments 2 and 3 are given the same reference numerals, and redundant description is omitted.
• a pulse modulation circuit 400 includes the above-described waveform shaping unit 411 and additional signal generation unit 412 in addition to the branch circuit 2101 and the intermittent operation circuit 120 in the second embodiment.
• the waveform shaping unit 411 includes a pulse modulation unit 2104 and a waveform synthesis circuit 4111. Among these, the pulse modulation unit 2104 performs pulse modulation on the control signal D2 from the branch circuit 2101 and outputs it to the waveform synthesis circuit 4111.
• the waveform synthesis circuit 4111 synthesizes a control signal D72, which is the output of a limiter circuit 4122, which will be described later, with the control signal D4, which is the output of the pulse modulation unit 2104.
• the additional signal generation unit 412 further includes a band limiting circuit 4121 and a limiter circuit 4122 in addition to the inverter circuit 2107, the delay circuit 2108, and the pulse modulation unit 2109 in the second embodiment.
• the band limiting circuit 4121 band-limits the control signal D7 output from the pulse modulation unit 2109 and outputs the control signal D7 to the limiter circuit 4122.
• the limiter circuit 4122 limits the amplitude of the control signal D71, which is the output of the band limiting circuit 4121.
• FIG. 18 is a diagram illustrating an example of an output waveform of each part of the pulse modulation circuit 400.
• 18 (a) to 18 (e) and 18 (h) are the same as FIGS. 13 (a) to 13 (g) and 13 (i).
• the control signal D71 shown in Fig. 18 (f) represents the output waveform of the band limiting circuit 4121, and band limitation is applied to the control signal D7 (see Fig. 18 (e)) which is the output of the pulse modulation unit 2109. ing.
• the control signal D71 emphasizes the ringing that occurs at the rise and fall of the pulse.
• the impedance value of the band limiting circuit 4121 is preliminarily set so that the frequency component of the ringing signal is, for example, the same as or approximately the same (substantially the same) as the oscillation frequency of the intermittent operation circuit 120.
• the control signal D72 shown in Fig. 18 (g) represents the output waveform of the limiter circuit 4122, and only the frequency component of the positive ringing signal remains among the frequency components of the control signal D71 of Fig. 18 (f). Bandwidth is limited to! /
• the control signal D9 (see Fig. 18 (h)), which is superimposed (synthesized) on the control signal D4 in (d) and has the same characteristics as the control signal D9 shown in Fig. 13 (i), is intermittently operated from the waveform synthesis circuit 4111. Output to circuit 120.
• the control signal D9 in FIG. 18 (h) is intermittently oscillated, and the modulation signal D10 in FIG. 18 (i) is output.
• the present invention is not limited to the first to fourth embodiments, and may be changed without departing from the gist of the present invention.
• Embodiments 2 to 4 the case where the branch circuit 2101 branches the control signal D1 has been described. You may make it input.
• the intermittent operation circuit 120 outputs an oscillation signal
• the intermittent operation circuit 120 is an oscillator as an example.
• the present invention is not limited to this.
• a multiplier, an amplifier, and a composite circuit thereof may be used as the intermittent operation circuit.
• the gate (emitter) terminal, drain (collector) terminal, or source (base) terminal of the field effect transistor (FE T) that constitutes the multiplier or amplifier
• the control signal S 12 or the control signal D9
• the transmission data for each pulse described in the method that can suppress the change in the pulse waveform depending on the transmission data string for each pulse and maintain the desired pulse waveform. It is not limited to the application to.
• a DC cut capacitor is inserted between the control signal generation unit and the intermittent operation circuit.
• the control signal S12 (or control signal D9) is transferred to the burst signal OF.
• F interval force It is generally known that a DC offset occurs when shifting to the burst signal ON interval, and the leading hundreds of thousands of symbols in the burst signal ON interval are affected. Therefore, the same effect can be obtained even if the waveform shaping is performed on the burst signal sequence instead of the data sequence using the method described in the above-described embodiment.
• One aspect of the pulse modulation circuit of the present invention includes an intermittent operation circuit that intermittently outputs a transmission signal in accordance with a control signal, and the intermittent operation circuit in accordance with transmission data, the first transmission
• the control circuit includes a control circuit that performs switching control between an oscillation state in which a signal is output and an idling state in which a second transmission signal having a lower amplitude or lower frequency than the first transmission signal is output.
• the circuit capacity of the intermittent operation circuit when in the transmission state is the idling state even if the immediately preceding state is not the transmission state. Is charged almost uniformly.
• the Nose waveform of the first transmission signal can be made independent of the immediately preceding transmission data string.
• the first transmission signal having a desired pulse width and abruptly generated at a desired timing can be generated without being influenced by the transmission data string. It is possible to obtain good reception quality by suppressing the degradation of reception performance due to the fluctuation of the tatum and timing jitter.
• the intermittent operation circuit is operated so as to generate a second transmission signal having a low amplitude or a low frequency, so that a desired pulse waveform can be generated while minimizing power consumption.
• a pulse modulation signal having the same can be generated.
• One aspect of the pulse modulation circuit of the present invention employs a configuration in which the intermittent operation circuit includes one or more of an oscillator, a multiplier, and an amplifier.
• a control signal is input to either the gate (emitter) terminal, drain (collector) terminal, or source (base) terminal of an FET that constitutes an oscillator, multiplier, or amplifier.
• the intermittent operation circuit can be intermittently operated to generate a transmission signal.
• the control circuit controls the intermittent operation circuit to a transmission state when the transmission data is “1”, and the transmission data is “0”. Place In this case, the intermittent operation circuit is controlled to the idling state, and the intermittent operation circuit is controlled so that the period of each idling state is shorter than the period of each transmission state.
• the idling state period in which the transmission data is "0" and the desired first transmission signal is not generated is shortened, and the operation time of the intermittent operation circuit is shortened.
• the power consumption of the operation circuit can be reduced.
• control circuit further switches the intermittent operation circuit to a stop state in which a transmission signal is not output between the transmission state and the idling state. Take the configuration to control.
• One aspect of the pulse modulation circuit of the present invention employs a configuration in which the control circuit variably controls the switching timing to the idling state in accordance with the parasitic capacitance of the intermittent operation circuit.
• the operation time in the idling state of the intermittent operation circuit can be minimized and the circuit capacity of the intermittent operation circuit can be charged by a necessary and sufficient amount. It is possible to stably generate a pulse signal with a steep rise while reducing power consumption.
• One aspect of the pulse modulation circuit of the present invention employs a configuration in which the amplitude of the second transmission signal in the idling state is variably controlled in accordance with the parasitic capacitance of the intermittent operation circuit.
• the amplitude of the second transmission signal output in the idling state can be reduced, and the parasitic capacity of the intermittent operation circuit can be charged by a necessary and sufficient amount. While reducing the power consumption of the circuit, a pulse signal with a steep rise can be generated stably.
• One aspect of the pulse modulation circuit of the present invention allows the first transmission signal output in the transmission state to pass while blocking the second transmission signal output in the idling state. A configuration further comprising signal blocking means is adopted.
• the unnecessary second transmission signal can be blocked, and only the desired first transmission signal can be passed. It is possible to prevent the reception quality from being degraded.
• One aspect of the pulse modulation circuit of the present invention uses a multiplier as the signal cut-off means, and controls the conversion efficiency of the multiplier to pass the first transmission signal. In addition, the second transmission signal is cut off.
• One aspect of the pulse modulation circuit of the present invention is a modulator that changes at least one of an amplitude or a phase of the first transmission signal formed by the intermittent operation circuit according to the transmission data, Is further provided.
• an ASK modulation signal or phase modulation signal having a desired pulse width and generated at a desired timing can be generated. Therefore, an AC that is completely synchronized with the modulation signal on the receiving side. This eliminates the need for a circuit for generating a wave signal, and suppresses deterioration in reception performance due to spectrum fluctuations and timing jitter, thereby obtaining good reception quality.
• One aspect of the pulse modulation circuit of the present invention employs a configuration in which the control circuit controls the intermittent operation circuit to an idling state only when the transmission data immediately after becomes “1”. .
• the intermittent operation circuit is controlled to the idling state only when the immediately following transmission data becomes "1", so that the operation time of the intermittent operation circuit can be suppressed, and the intermittent operation circuit Power consumption can be further reduced.
• One aspect of the pulse modulation circuit of the present invention includes an additional signal generation unit that generates a second data signal sequence for shaping a waveform of a predetermined array portion of the first data signal sequence, and the second signal generation unit.
• a waveform shaping unit that generates a signal having an overshoot unit by shaping the first data signal sequence using the data signal sequence, and a circuit based on the signal shaped by the waveform shaping unit When the capacitor is charged and the circuit capacity reaches a predetermined value, an intermittent operation unit that outputs a transmission signal is employed.
• the circuit capacity of the intermittent operation circuit easily reaches a predetermined capacity value when the transmission state is set to the transmission state, and the waveform of the transmission signal is not affected by the immediately preceding data string. be able to.
• One aspect of the pulse modulation circuit of the present invention employs a configuration in which the intermittent operation circuit includes one or more of an oscillator, a multiplier, and an amplifier.
• a control signal is input to either the gate (emitter) terminal, drain (collector) terminal, or source (base) terminal of an FET that constitutes an oscillator, multiplier, or amplifier.
• the intermittent operation circuit can be operated intermittently to generate a transmission signal.
• the predetermined arrangement is a data signal sequence that becomes “1” immediately after “0”
• the attached calo signal generation unit generates a pulse signal that rises at a timing when the first data signal sequence becomes “1” immediately after “0” as the second data signal sequence, and the waveform shaping unit Then, a configuration is adopted in which a ringing signal is added to the rising portion where the first data signal sequence becomes “1” immediately after “0” based on the second data signal sequence.
• the first data signal sequence when the first data signal sequence is "1" and the intermittent operation circuit is set to the transmission state, the first data signal sequence is "0" even if the immediately preceding data is "0". Since the rising part that becomes “1” is overshooted, the input capacity of the intermittent operation circuit is charged earlier. As a result, the charging time of the input capacity of the intermittent operation circuit when the immediately preceding data force is “0” can be made the same as when the immediately preceding data is “0” and depends on the data string. Without generating a transmission signal that has a desired pulse width and abruptly occurs at a desired timing It ’s just like you can do it.
• One aspect of the pulse modulation circuit of the present invention includes a variable band limiting unit that varies a cut-off frequency for band-limiting the first data signal sequence according to the second data signal sequence. The structure to do is taken.
• the additional signal generation unit generates the ringing signal based on the second data signal sequence
• the waveform shaping unit includes the first data A configuration is adopted in which the ringing signal is synthesized with a signal sequence.
• the first data signal sequence when the first data signal sequence is "1" and the intermittent operation circuit is set to the transmission state, the first data signal sequence is "0" even if the immediately preceding data is "0". You can overshoot the rising part that becomes “1”.
• One aspect of the pulse modulation circuit of the present invention employs a configuration in which the ringing signal has the same or substantially the same frequency as the frequency of the intermittent operation unit.
• the input capacity of the intermittent operation circuit can be efficiently charged.
• the present invention can form a pulse modulation signal having a desired pulse waveform regardless of the transmission data signal sequence, for example, a pulse that intermittently generates an AC wave signal according to transmission data. It is useful for a modulation circuit and a pulse modulation method.

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