Classifications

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Definitions

• the invention relates to a component which comprises a device chip applied to a carrier substrate in a flip-chip technique and to a method for producing the same.
• a component encapsulation is known, for example, from US Pat. No. 6,898,380 B1, in which a component chip carrying the component structures is mounted on a carrier substrate in flip-chip technology by means of bump connections, in which the component chip is arranged at a distance from the carrier substrate above it is. In this case, between the component chip and the carrier substrate
• Object of the present invention is to provide a device that is easy to manufacture and can be safely sealed against the outside world.
• An electrical component which uses a flip-chip technique on a single or multi-layered comprises a supported substrate substrate applied chip.
• the electrical and mechanical connection between the component chip and the carrier substrate having an electrical wiring is effected by means of bumps.
• a support frame is arranged, which is adapted in its height to the height of the bumps and has a plane in particular planarized and, for example, ground surface, so that it fits tightly against the underside of the component chip.
• Such a device is characterized in particular by two advantages over known encapsulated in a similar manner components.
• the flat surface of the frame ensures a positive contact with the component chip, which also has a planar surface resting thereon. There remains a minimal or no gap between the frame and the component chip, and this results in a good closure of the cavity enclosed between the underside of the component chip and the surface of the carrier substrate within the frame.
• This device may also be used on an uneven and e.g. Nonlinear warped panel may be applied as a carrier substrate.
• bumps are understood to mean all electrically conductive structures via which bonding takes place Specifically, these can be:
• Studbumps which are pressed together by mechanical force with simultaneous ultrasound action and welded to the substrate. Studbumps themselves can be produced with specially equipped wire bonders or galvanically. At studbumps, au-studs are currently standard;
• Pillars made of Cu are used.
• the height of the frame is adapted to the height of the bumps. This means that when bumping the component chip and in the case of solder bumps during the subsequent reflow, the bumps can only collapse or deform to such an extent and thus reduce their height that the underside of the component chip just comes to rest on the plane surface of the support frame. As a result, only minimal mechanical tensile forces act on the corresponding metallizations on the component chip via the bumps and the support frame, because the thermal expansion coefficients of bumps and solder frames are very well matched.
• the flat surfaces of the support frame and the component chip prevent tilting due to uneven overlapping. This is particularly advantageous when the device structures and thus the device itself is sensitive to mechanical stress, as they may occur, for example, later in the encapsulation of the components with a plastic sheath. With the proposed device so sensitive component structures can be included stress-free and tight against environmental influences and hermetically encapsulated by further measures.
• the component chip can advantageously be a MEMS component (micro-electro-mechanical system) which connects electrical and mechanical functions with one another.
• the micro-electro-mechanical functions may be those of sensors, actuators, switches or electro-acoustic components and in particular working with acoustic waves components. These components are mostly miniaturized, so that even the smallest forces are sufficient to disturb the function or to change the properties of the MEMS component inadmissible. In principle, however, it is also possible to carry out any desired electrical component which has component structures to be protected on its surface in the manner according to the invention.
• the carrier substrate has an integrated electrical wiring.
• it is preferably multi-layered, wherein on and between individual layers of a mechanically stable and electrically insulating material structured metallization levels are provided, which realize a corresponding wiring.
• the individual metallization levels are connected to one another via preferably plated-through plated-through holes, so that an electrical contact is produced for metallic contact pads applied on the surface of the carrier substrate and external contacts arranged on the underside of the carrier substrate is.
• a mechanically stable material is a particular highly filled plastic material with low water absorption, low gas permeability and an adaptable coefficient of thermal expansion (eg LCP (Liquid Crystal Polymer) or a ceramic, in particular a HTCC (High
• the terminal metallizations on the upper side of the carrier substrate have a solderable or bondable surface, in particular a UBM metallization (Under Bump Metalization). Corresponding metallizations are also provided on the component chip.
• the bumps for connecting the device chip and the carrier substrate are preferably solder bumps, stud bumps or solder coated metals e.g. Co-pillars coated with solder.
• the device chip is made of a ceramic, semiconductive, or other crystalline material, such as silicon, depending on the device. formed a piezoelectric crystal.
• the support frame is preferably produced on the carrier substrate and in particular made of a plastic material or of metal.
• the coefficient of expansion of the material forming the support frame is adapted to that of the bumps. In this way, it is guaranteed that the finished component does not generate any additional mechanical stress in the bending direction, even under thermal cycling.
• the support frame can be applied to a ceramic carrier substrate by screen printing before sintering or in other methods after sintering of the carrier substrate or in part before sintering and the remaining part after sintering, eg currentless or galvanic.
• the component structures may be mechanically movable structures or, in the case of components working with acoustic waves, metallizations with the aid of which acoustic waves are generated, reflected or converted back into electrical signals.
• the joint region between the lower edge of the component chip and the support frame ⁇ can be sealed with a foil.
• This film is in ⁇ particular a laminatable thermoplastic (eg LCP (Liquid Crystal Polymer) film) or a thermoset in the B state, which is preferably soft and has a low modulus of elasticity.
• LCP Liquid Crystal Polymer
• Such a film can serve as a base for further covering layers and thereby absorb, buffer or distribute forces acting on the component chip (eg thermal cycles). In addition, it protects the cavity in subsequent processes, for example, in the electroless or galvanic application of shields (Shieldings).
• the film may be single-layer or multi-layer, wherein identical or different partial films can be joined or laminated on top of each other.
• the support frame consists essentially of a metal whose thermal expansion coefficient is adapted to the usually made of solder metal bumps or the metal of the Studbumps.
• Well suited for this purpose are copper, nickel, silver or gold, which, moreover, can be easily electrodeposited.
• the support frame can also be composed of several layers of different materials, in which case the thermal expansion coefficient averaged over all the layers is matched as well as possible with that of the bumps.
• the joint area between the lower edge of the component chip and the support frame with a
• Metal layer sealed which forms a metal closure for the joint. Accordingly, the metal layer terminates at least with the device chip and the support frame.
• the metal layer can be applied only in the joint area or alternatively also over larger parts of the component, that is to say also on the rear side of the component chip, the frame or the surface of the carrier substrate.
• Treatment with a molten metal can moisten this. This makes it easy to produce the metal closure while applying the metal layer at the same time selectively over the wetting layer. This is advantageous if the metal layer is to be limited to the joint area in order not to lead to interfering capacitive couplings with component electrodes, for example on the back side of the component chip.
• a component chip covered with a laminate film which already has a certain seal of the joint area, can additionally be reinforced with a backside metallization. While the laminate film still has a certain permeability to gases and in particular water vapor, a hermetically sealed, electrically shielded component can be obtained with a closed backside metallization. It is advantageous if the back-side metallization has a direct connection to a metallic one Support frame and / or having the surface of the carrier substrate. For this purpose, it may be necessary ieren the laminate film before the generation of the back-side structure to ⁇ and to remove at least in a shape of a frame around the chip Bauelement- drawn portion.
• the backside metallization can be applied in two stages by first applying a thin base metallization in a thin film process or by treatment with a nucleating agent, e.g. Palladium chloride-containing solution is produced. Subsequently, this base metallization can be electrolessly and / or galvanically reinforced. It is well suited, for example, to sputter on a titanium or a titanium / copper layer and to strengthen it galvanically with copper.
• a nucleating agent e.g. Palladium chloride-containing solution
• a direct structuring of the laminate film succeeds, for example, by ablation with a laser.
• a support frame is sufficient as a spacer and for supporting the component chip over the carrier substrate for miniaturized components.
• a large distance between two support points can lead to bending of the component chip and thereby likewise to a stress-related impairment of the component function.
• It is therefore advantageous between component chip and Carrier substrate provide further support elements, which are structured together with the frame and provide additional support points for the device chip with reduced distances between each other and allow safe and low-tension support.
• a cover film can be laminated, which is sufficiently thick and sufficiently deformable, thereby enabling a planarization Glob top-top.
• the cover film has an overall height above the carrier substrate that is higher than the height of the backside of the device chip over the carrier substrate.
• the covering film or the glob top cover thus produced is to be selected in its modulus of elasticity, its coefficient of thermal expansion and the glass transition temperature such that minimal mechanical stress results during soldering of the component and during thermal cycles.
• a large-area carrier substrate in particular a panel or a carrier wafer, each having a plurality of slots for component chips.
• Each slot has at least metallic
• the frame structures are first of all produced in a number corresponding to the bays, and are advantageously structured in such a way that at least the metallic bays assigned to a berth
• Support elements can be generated together with the support frame. If support frames and support elements are produced galvanically by means of a common resist mask, then the subsequent planarization process of support frames and support elements can take place before the resist mask is removed again. As a result, support frame and support elements can be mechanically stabilized against the press, grinding or milling process used.
• the planarization process resembles not only sub ⁇ differences from the frame height, resulting from the tolerances of the manufacturing processes, but also those which result from the topology of the carrier wafer.
• the bumps are generated on the component chip. This can be done advantageously by means of printing a solder paste by screen printing. With this method, the Bump Beat is easily adjustable, as this is essentially determined by the controllable size of the UBM and the amount of applied solder paste.
• the bumps are preferably generated on the device chip BC. Exceptions are the already mentioned pillars, which can be produced together with the frame structure in the same process and from the same material on the carrier substrate. Already during production, the pillars and possibly also the frame structure can be provided with a solder layer which is thin relative to the height of the pillars, typically e.g. 5 ⁇ m thickness are provided.
• the component chip is placed on the carrier substrate and with this in a suitable method over connected the bumps.
• solder bumps are used, a reflow process is suitable.
• the solder bump collapses and changes its cross-sectional shape, in particular, its height is reduced.
• Adhesion forces on the wetting UBM cause the device chip to pull down.
• the height of the (collapsed) bumps is adapted to the height of the support frame and the support elements, this leads to a placement of the component chip on the support frame and the support elements.
• the pillars are also soldered.
• a thermocompression method can be used, which also leads to a deformation of the bumps, whereby these are reduced in height.
• the sealing of the component takes place in the joint area between the component chip and the support frame, in which either a thin laminate film is laminated, a metal closure is produced or a thick cover film is directly laminated to produce a glob top.
• the sealing by means of thin laminate foil can be supplemented with a backside metallization and all sealing methods can be additionally combined with an applied thick covering layer.
• the preferred production of the metallic closure is carried out with molten metal in the dipping process or in a standing wave.
• the amount or the thickness of the metal can be controlled via gas nozzles by means of air or N 2 (Hot Air Leveling).
• the required or advantageous wetting layer can be applied in structured form to corresponding surface regions of one or more elements selected from the component chip, carrier wafer and support frame or over the entire surface thereof Bonding of the component chip are applied to the arrangement.
• individual areas of the surface can be excluded by a protective film from the coating with the wetting layer.
• the protective film can be selectively printed, for example by an ink-jet method.
• the outer device chip edges may be selectively provided with a wetting layer. This can advantageously take place in the process stage, in which the component chips are separated.
• the singulation can take place with the so-called DBG method (Dicing Before Grinding), in which first cuts are made on the surface of the component wafer bearing the component structures along the intended parting lines. In order to protect the surface of the device wafer (e.g., from chipping), it is covered with a sticky tape serving as a protective film. After the cuts have been made, the side edges of the individual component chips are exposed therein, and thus accessible to a metallization for producing a wetting layer, for example a layer combination of titanium / copper / gold, which is e.g. can be sputtered.
• a metallization for producing a wetting layer for example a layer combination of titanium / copper / gold, which is e.g. can be sputtered.
• the component wafer is ground off from the rear side until the incisions are completely opened from this side, with which the component chips are also separated.
• the component chip edges can be provided with a wetting layer by applying pyroelectrically generated charges only on the back side to the application of the wetting layer in a manner opposite to the state of charge of the top surface. surfaces sensitive activation or metallization is avoided.
• Wetting layers on the surfaces of carrier wafer and component chip can be applied directly, for example by means of thin-layer processes via corresponding masks or directly by means of screen printing.
• FIG. 1 shows the cross-sectional views on the basis of schematic cross sections
• FIG. 2 shows a carrier wafer with support structures applied thereto in plan view
• FIG. 3 shows a carrier wafer in schematic cross-section after the application of bumps
• FIG. 4 shows the carrier wafer after the bonding of a component chip
• FIG. 5 shows a schematic cross-section of various relative arrangements of component chip edges and frame structures
• FIG. 6 shows a component sealed with a covering film
• FIG. 7 shows a component sealed with a laminate film and a cover film
• FIG. 8 shows two different possibilities of hermetically sealing a component with a laminate foil and a backside metallization
• FIG. 9 shows various possibilities of a metal closure
• FIG. 10 shows a process flow diagram for the production of a support frame
• FIG. 11 shows a process flow diagram for the application of a laminate
• Figure 12 shows a process flow diagram for making a laminate film and backside metallization seal.
• FIG. 1 shows a schematic cross-section of different process stages for the production of the support frame SR and additional Licher support elements SE on a support substrate.
• the starting point is a carrier wafer or panel, hereinafter referred to only as a carrier wafer TW, which is preferably constructed in multiple layers and in which a wiring is integrated. (Not shown in the figure). Also not shown are pads on the top and external contacts on the bottom of the carrier wafer TW.
• the carrier wafer TW which carries UBM structures and, if it consists of HTCC or LTCC, is linearly and nonlinearly warped, is measured with high accuracy with respect to the UBM positions.
• a metallic growth layer WS is applied to the surface, for example, electroless or in a PVD process.
• a galvanostable resist GR is applied and patterned according to the desired structure of the support frame and the support elements, e.g. by laser lithography.
• FIG. 1A shows the arrangement according to the structuring of the galvanic resist GR.
• the reinforcing layer VS is then produced in the depressions of the electroplating resist in which the growth layer WS is exposed, for example by deposition of copper (see FIG. 1B).
• FIG. 1C shows the arrangement after the implementation of a planarization process in which the surfaces of the electroplating resist GR and the reinforcing layer VS are removed until an overall planar surface is produced. Subsequently, the galvanic resist GR is removed and the underlying residues of the growth layer WS etched away.
• FIG. ID shows the arrangement with the support frames SR and support elements SE thus produced.
• FIG. 2 shows a top view of a possible arrangement of support frame SR and support elements SE on a carrier wafer TW. Between different bays EP for individual components, the dividing lines TL are indicated by dashed lines.
• Each support frame encloses metallic ⁇ An AFL mating surfaces for the later component contacting and, optionally, together with the support frame constructive ⁇ tured support elements SE.
• the two-dimensional shape of the support frame in the illustration preferably follows the dimensions of the device chip to be applied thereto and is at least dimensioned so that the device chip can rest all around, wherein the device chip edge can be flush with the outer edge of the support frame, or either component chip or support frame can survive.
• a metallic support frame and supporting elements produced in parallel can also be produced by applying metal-containing mass in the inkjet process.
• the bumps can be produced together with the support frame or with the support elements on the carrier wafer as metal pillars. However, they may also be formed on the opposite wafer-based device chip, as illustrated above, in the case of solder bumps or studbumps. This can be done in particular by printing a solder paste. For a small number of bumps, the use of studbumps can also be advantageous or cost-effective.
• FIG. 3 shows the arrangement with bump precursors printed here on the carrier wafer TW. They protrude above the support frame and possibly existing support elements so that thereon a component chip BC can be placed on it and soldered.
• FIG. 4 shows the attached component chip after soldering.
• the solder is either on the Cu pillars of the carrier wafer TW or on the SAC bumps of the component chip BC.
• Thermosonic is connected without solder ver ⁇ in.
• SAC bumps the bumps collapse during soldering by wetting the UBM surfaces on the carrier wafer, the component chip BC resting on the support frame SR and the support elements SE.
• the volume and the height of the bumps BU is also dimensioned on the component chip in the production thereof such that a corresponding height would be set during collapse or deformation of the bumps BU even without the support frames and support elements acting as spacers, which is equal to that of the support elements or slightly lower. This ensures that the connection made by the bumps is largely free of tensile forces that could be in the form of distortions on the device chip and thus adversely affect its device functions.
• the device chip may already be seated on the support frame prior to bonding.
• FIG. 5 shows a schematic cross-section of various possibilities for how the component chip can rest on the support frame.
• the edge of the component chip BC can rest centrally on the support frame.
• a tolerance value for both the positioning of the support frame and the positioning of the component chip on the support frame therefore remains almost the entire width of the support frame.
• FIG. 5B shows a variant in which the support frame extends to the parting line TL, which represents the later component edge. This embodiment requires a separation of the components by means of a guided through the support frame section, at the same time a circumferential strip of metallic surface is formed at the saw edges of the support frame.
• FIG. 5C shows a component chip whose edge projects beyond the support frame SR.
• FIG. 5D shows a limiting case in which the outside edge of the support frame and the outside edge of the component chip are flush.
• this is an ideal case, which is neither sought nor maintained in practice due tolerances to be maintained. In general, such an arrangement is selected, which has a minimum component volume or a minimum component area result.
• Embodiments according to FIGS. 5A and 5B are preferred if only a small contact surface is available on the underside of the component chip, which is free of component structures.
• Embodiments of Figures 5C and 5D are optimized with respect to the footprint of the bays.
• Figure 6 shows a way to seal the device in the joint area between component chip BC and support frame SR.
• This can, as shown in Figure 6, take place by applying a cover sheet AF.
• This is relatively thick and comprises a polymer in the B state, so that it can thermally deform and then harden.
• the cover film AF is applied to the surface under heat and pressure so that it closely follows their topography, without cavities remain during lamination between cover film AF and carrier wafer TW or frame structure RS and component chip BC.
• cover film AF is applied to the surface under heat and pressure so that it closely follows their topography, without cavities remain during lamination between cover film AF and carrier wafer TW or frame structure RS and component chip BC.
• the overall height of the laminated cover film over the component chip ensures that the component chip is covered by the cover film as well as its joint area with the frame structure.
• a laminate film LF which consists in particular of a soft thermoplastic material, can be applied under the cover film AF.
• a thin film can be laminated more easily and with less contact pressure than the relatively thick cover film.
• Their low modulus of elasticity also means that the component chip itself is optimally protected against forces that might have an effect on the component chip BC when soldering it in, during thermal cycles or only in the second level in the ummoldeten (with a Moldverkapselung) module it effectively acts as a buffer and also absorbs and distributes forces more effectively.
• Laminate film LF and cover film AF can be laminated in separate or in the same step.
• Figure 7 shows a detail of such a sealed component in the schematic cross section.
• FIG. 8 shows a further possibility of sealing in which a laminate foil LF is applied in the first step, similar to the embodiment according to FIG.
• the laminate film LF can be patterned, wherein at least the joint region between the frame structure and the component chip remains covered by the laminate film.
• a backside metallization RM is produced over the laminate film LF, for example As shown in Figure 1 for the support frame shown in a two-step process by means of a thin film applied base metallization, which can then be galvanically reinforced.
• the base layer may, for example, be titanium-containing, the galvanic reinforcement may comprise copper.
• Figure 8A shows an embodiment of the patterning of laminate film LF and backside metallization RM in which both the edges of the laminate film and the backside metallization both terminate on the surface of the support frame SR.
• Figure 8B shows a variant in which the laminate film is removed in a frame-shaped sealing area above the now exposed surface of the support frame, so that the support frame can be contacted by the back side metallization RM.
• the metal-metal connection between back-side metallization and supporting frame SR results in a particularly tight connection, in particular with respect to moisture diffusion.
• the tension-free rear-side metallization increases the mechanical stability of the entire component. This is advantageous if the component is later encapsulated in a so-called transfer molding process for further packaging and encapsulation with a plastic compound.
• the backside metallization serves to electromagnetic shield the device.
• FIG. 9 shows various possibilities for how the joint area can be closed with a metallic closure MV.
• a suitable wetting layer BS is arranged at least in the joint area between the support frame and in the region of the component chip edge. This can after applied to the soldering of the component chip and, for example sputtered or vapor-deposited. Furthermore, it is possible to apply the wetting layer on the component chip itself as well as on the surface of the support frame prior to placement of the component chip.
• FIG. 9A shows a possible embodiment of the metal closure MV in schematic cross section. At least on parts of the surface of the component chip, on its edge and on the surface of the support frame, a wetting layer BS is provided. Then molten metal is deposited and allowed to cool, with the metal closure MV adhering to the locations on the device where the wetting layer is present.
• the embodiment shown in FIG. 9A does not exclude that the wetting layer rests over the whole area on the component chip and also on the carrier wafer. It is also possible that the support frame is completely covered by a wetting layer.
• FIG. 9B shows an arrangement in which the component chip edge projects beyond the support frame.
• the wetting layer is therefore required only on the underside of the protruding component chip, on the outside of the support frame and on a surface region of the carrier wafer below the protruding component chip edge.
• FIG. 9C shows a similar embodiment, in which, however, the wetting layer is formed only on the underside of the component chip in the projecting region and on the (overall) Surface of the support frame is applied. Even with this minimized embodiment, the joint area is optimally sealed.
• Figure 9D shows an embodiment in which the edge of the component chip BC is flush or approximately flush with the outer edge of the support frame SR. Both outer edges are therefore provided with a wetting layer BS, to which the metal closure is then applied by one of the methods mentioned.
• the molten metal to be deposited When sealed with a metal closure MV, the molten metal to be deposited may be selected to have a lower melting point than the bump connection. As a result, melting of the bumps is avoided when producing the metal closure.
• a higher-melting alloy can be obtained by remelting with the metal closure, which does not become liquid during later soldering of the component.
• a metal closure is suitable which comprises tin, which forms a corresponding alloy in contact with the Ti / Cu / Au wetting layer.
• all embodiments of the metal closure MV shown for example in FIG. 9 can be covered by an additional nickel layer deposited over the metal closure.
• FIG. 9E shows a further variant of the method in which the bump height is dimensioned so that a small gap remains between the component chip and the frame structure during soldering.
• a circumferential frame-shaped wetting layer is applied on the underside of the component chip.
• Another wetting layer is found on the surface of the frame structure and is applied, for example, after its planarization, for example, electroless as typically 0.1 micron thick Au layer.
• the remaining after soldering of the component chip gap can be filled with the metal closure.
• the capillary depression in the gap prevents penetration of the liquid metal into the cavity below the device chip.
• FIG. 9F shows a further variant of the method in which, in addition to the support frame SR on the carrier wafer TW, a circumferential frame structure RS is also applied to the component chip BC.
• This may be structured much finer than the support frame and e.g. typically of 5 ⁇ m width and height each. It can consist of the same material and is at least partially wettable with solder.
• the support frame SR on the carrier wafer TW has a typical height and width of 50 ⁇ m each. Both frames can be soldered together. The joint during bonding then arises between support frame SR and frame structure RS and is provided with a metal closure MV.
• the advantage of this arrangement is that due to the smaller width of the frame structure RS a larger usable chip area remains on the component chip than if the relatively wide support frame were placed on the component chip.
• FIG. 10 shows a process flow diagram for the production of a frame structure on a carrier wafer, as it already is was explained with reference to FIG.
• step 1 a growth layer is sputtered over the entire surface of the carrier wafer.
• step 2 a photoresist is laminated.
• step 3 the photoresist is exposed.
• step 4 the resist is developed to form the desired resist pattern.
• the growth layer is reinforced by electrodeposition of copper to a desired layer thickness.
• the grown metal layer together with the overlying galvanic resist mask is planarized by means of a milling process.
• the so-called FIy Cutting method can be used, in which a diamond rotates over the surface to be abraded. The grinding is performed up to a predetermined height of the frame structure.
• the carrier wafer TW or the support frame protection law can be provided without current with a wetting layer BS of typ. 0.1 micron Au. This measure also prevents, for example, that in step 8 - etching away the growth layer - the surface of the planarized reinforcing layer is etched.
• step 7 the resist is removed, the remaining now exposed area of the growth layer is etched away in step 8. Subsequently, the support wafers provided with support frames and support elements are ready for the implementation of the flip-chip process.
• Figure 11 shows a flow chart for a lamination seal.
• step A the component chips are placed on the carrier wafers at the corresponding slots. Bondet.
• step B a reflow soldering process takes place, followed by a lamination process in process step C.
• Two foils are laid one over the other and laminated over the entire surface over the backs of the bonded component chips.
• the lower layer is relatively thin, thermo ⁇ plastic and soft, while the upper layer is a curable and relatively filled with a filler layer. It is also possible during this lamination process to laminate an intermediate third film, which is also relatively soft but already harder than the one
• Laminate film is.
• step D the composite of carrier wafers, component chips and laminating film is subjected to a grinding process from the top in order to achieve a minimum overall height. Subsequently, the components are separated in step F, for example by means of a sawing process.
• step B and C a cleaning process can be carried out by means of a plasma containing oxygen and hydrogen molecules.
• step D and E the device can be tested and optionally labeled.
• FIG. 12 shows a process flow diagram for the production of a backside metallization.
• the components are bonded to the carrier wafers in a flip-chip process a) and subsequently soldered by means of a reflow soldering process in step b).
• a lamination process c) in which a thin, soft laminate film is laminated over the entire surface via component chips and carrier wafers.
• the foil is then removed again in step d), for example by means of laser ablation or sawing.
• a plasma cleaning step again follows in an oxygen and / or hydrogen-containing plasma.
• the components are dried in vacuo.
• step g) the production of a base metallization by sputtering a titanium / copper mixture, which is then reinforced in step h) by electrodeposition of copper and then nickel.
• the components realized on the carrier wafer are now completed and, if appropriate, can be fed by means of sawing while performing laser marking and electrical testing for the device properties in step i).
• Wire-bonding technology or embedded in the modules on the modules embedded elements or over-laminated with globtop-like materials are obtained which are minimized in terms of their external dimensions, which are impermeable to environmental influences and in particular to moisture and which can be produced in the process according to the invention simpler than heretofore.
• the components have improved mechanical stability with equal or smaller dimensions and show improved moldability and increased thermal cycling resistance.
• the invention is not limited to the embodiments shown in the embodiments and the figures but is defined solely by the claims. It is therefore within the scope of the invention to further combine the individual possibilities for sealing with one another or to vary the sealing methods.
• the components can be realized per type of component with any number of support frames with and without additional support elements. It is also possible to mount and to match different component chips on a carrier wafer, to separate different components containing components chips or to different components.

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