JP5220004B2 - フリップチップ素子及びその製造方法 - Google Patents
フリップチップ素子及びその製造方法 Download PDFInfo
- Publication number
- JP5220004B2 JP5220004B2 JP2009512410A JP2009512410A JP5220004B2 JP 5220004 B2 JP5220004 B2 JP 5220004B2 JP 2009512410 A JP2009512410 A JP 2009512410A JP 2009512410 A JP2009512410 A JP 2009512410A JP 5220004 B2 JP5220004 B2 JP 5220004B2
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- support frame
- element chip
- chip
- metal
- layer
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- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/11—Device type
- H01L2924/12—Passive devices, e.g. 2 terminal devices
- H01L2924/1204—Optical Diode
- H01L2924/12041—LED
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/10—Details of semiconductor or other solid state devices to be connected
- H01L2924/146—Mixed devices
- H01L2924/1461—MEMS
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
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- H01L2924/3025—Electromagnetic shielding
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/30—Technical effects
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- H01L2924/351—Thermal stress
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/4913—Assembling to base an electrical component, e.g., capacitor, etc.
- Y10T29/49144—Assembling to base an electrical component, e.g., capacitor, etc. by metal fusion
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- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
- Y10T29/00—Metal working
- Y10T29/49—Method of mechanical manufacture
- Y10T29/49002—Electrical device making
- Y10T29/49117—Conductor or circuit manufacturing
- Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
- Y10T29/49155—Manufacturing circuit on or in base
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- General Physics & Mathematics (AREA)
- Wire Bonding (AREA)
Description
・半田バンプ、例えば半田付け中にUBM(Under Bump Metallization)へと崩壊するSAC(Sn Ag Cu)半田バンプ。
・超音波効果を併用した機械力により基板に圧接され融合するスタッドバンプ。
スタッドバンプ自体は、特別に用意されたワイヤボンダ、又は電解を利用して作成される。スタッドバンプとして、Auスタッドが現在のところ標準的となっている。
・スタッドバンプと等価である、表面に半田溜まりをもつ金属柱。
すなわち、このような金属柱には、使用できる金属の選択肢はより広くなる。例えば、Cuからなる柱が使用可能である。
TW キャリアウェハ
EP 実装場所
AFL 金属接合面
TL 実装場所の分離線
SR 支持フレーム
GR 電解レジスト
WS 成長層
VS WSに対する補強層
SE 支持要素
BC 素子チップ
BS 素子構造体
AK 外部接点
BU バンプ
LF ラミネートフィルム
RM 背面メタライゼーション構造体
DS 薄いフィルム
AF カバーフィルム
BS 濡れ層
MV 金属密閉体
RS フレーム構造体
Claims (22)
- 電気配線を有する単層又は複層のキャリア基板(TS)と、
バンプ(BU)を利用したフリップチップ技術により前記キャリア基板(TS)に実装され、前記配線と電気的に接続され、その前記キャリア基板(TS)と対向する表面に素子構造体(BES)を有する素子チップ(BC)と、
前記キャリア基板と前記素子チップとの間に配置され、その高さが前記バンプ(BU)に適合され、平坦な又は平坦化された面を有し、前記素子チップ(BC)の底面と密着し、金属を含む支持フレーム(SR)と、
前記素子チップ(BC)の底面端部と前記支持フレーム(SR)との間の、フィルムでシールされた結合領域と、
を備えることを特徴とする電気素子。 - 少なくとも前記素子チップ(BC)の底面端部と前記支持フレーム(SR)との間の前記結合領域は金属層でシールされていることを特徴とする請求項1に記載の素子。
- 前記金属層は前記支持フレーム(SR)の金属を終端させることを特徴とする請求項1又は2に記載の素子。
- 前記金属層は前記素子チップ(BC)を終端させることを特徴とする請求項3に記載の素子。
- 前記素子チップ(BC)の前記素子構造体(BES)の反対側の背面は、前記支持フレームを終端させるラミネートフィルム(LF)で覆われていることを特徴とする請求項1ないし4の何れか1項に記載の素子。
- 前記ラミネートフィルム(LF)上に配置された背面メタライゼーション構造体(RM)を更に備えることを特徴とする請求項5に記載の素子。
- 前記支持フレームと高さが適合する支持要素と、前記支持フレーム内の前記素子チップ及びキャリア基板の間に配置された材料と、を更に備えることを特徴とする請求項1ないし6の何れか1項に記載の素子。
- 前記金属層上又は前記ラミネートフィルム上に配置され、表面を平坦化された樹脂カバーを更に備えることを特徴とする請求項1ないし7の何れか1項に記載の素子。
- 素子チップ(BC)に対する複数の実装場所(EP)を有し、素子チップ(BC)の電気的接続のための金属接合面(AF)が各実装場所に設けられたキャリア基板(TS)を用意する工程と、
各実装場所を囲むフレーム構造体(RS)を形成する工程と、
前記フレーム構造体(RS)を機械的方法により平坦化する工程と、
前記接合面(AF)上又は前記素子チップ(BC)上にバンプ(BU)を形成する工程と、
前記素子チップ(BC)を前記バンプ(BU)を利用したフリップチップ処理により接合し、前記バンプ(BU)は前記素子チップが対応する支持フレーム(SR)上に載置されるように崩壊又は変形する工程であって、前記フレーム構造体(RS)は平坦化後の前記支持フレーム(SR)の高さが接合後の変形又は崩壊した前記バンプ(BU)の高さに一致するように平坦化されている工程と、
前記素子チップ(BC)の底面端部と前記支持フレーム(SR)との間の結合領域をシール材で覆う工程と、
を有することを特徴とする素子の製造方法。 - 前記フレーム構造体を形成する工程は前記支持フレーム(SR)が前記キャリア基板(TS)上にリソグラフィにより形成されるように電解レジスト(GR)からなる成形マスクを設ける工程から構成され、前記キャリア基板の全表面に積層された金属成長層(WS)は電解を利用して補強されることを特徴とする請求項9に記載の方法。
- 前記結合領域を覆う工程は、前記シール材が前記素子チップ(BC)の背面上及び前記支持フレーム(SR)上を覆うように、前記シール材として熱可塑性樹脂から構成されるラミネートフィルム(LF)を全構成上にラミネートする工程から構成されることを特徴とする請求項9又は10に記載の方法。
- 前記ラミネートする工程の後に、前記ラミネートフィルム(LF)を各素子チップ(BC)に対してフレーム形状の領域及び前記支持フレーム(SR)が露出させられる領域を除去する工程と、その後に金属層を全表面に積層する工程とを更に有することを特徴とする請求項11に記載の方法。
- 前記結合領域の少なくとも前記素子チップ(BC)の端部と前記支持フレーム(SR)とに濡れ層を形成する工程と、前記結合領域をシールする金属層がそこに形成されるように溶融金属を前記濡れ層に到達させる工程とを更に有することを特徴とする請求項9又は10に記載の方法。
- 前記濡れ層(BS)を形成する工程はTi/Cu/Au配列層を積層する工程から構成されることを特徴とする請求項13に記載の方法。
- 前記溶融金属はディップ法で積層されるか又は定在波で積層されることを特徴とする請求項13又は14に記載の方法。
- 前記金属はプラズマスプレー法で積層されることを特徴とする請求項13又は14に記載の方法。
- 前記素子チップ(BC)の背面は、背面に積層された樹脂層の援助により、前記溶融金属によるコーティングから保護されていることを特徴とする請求項13ないし16の何れか1項に記載の方法。
- 前記溶融金属と前記濡れ層(BC)とは前溶融金属の融点よりも高い融点を示す合金を形成することを特徴とする請求項13ないし17の何れか1項に記載の方法。
- 前記素子にカバーフィルムをラミネートする工程を更に有し、前記カバーフィルムのキャリア基板(TS)上の全高は前記素子チップ(BC)の背面の高さよりも高く設定され、前記ラミネートされたカバーフィルムは平坦化されることを特徴とする請求項9ないし18の何れか1項に記載の方法。
- 前記カバーフィルム(AF)をラミネートする工程は、ラミネートした後に熱で硬化するB状態の樹脂材料から構成された熱で変形可能なカバーフィルムを利用するか、又は熱可塑性樹脂材料から構成されたカバーフィルムを利用する工程から構成されることを特徴とする請求項19に記載の方法。
- 支持要素を前記支持フレーム(SR)と並行して共通の工程で形成する工程を更に有し、前記支持要素(SE)は前記支持フレーム内に位置して前記支持フレームと同一の高さを有し、前記支持要素は前記素子チップ(BC)が素子構造体(BES)に固定されない面領域を有して前記支持要素上に載置するように配置されることを特徴とする請求項9ないし20の何れか1項に記載の方法。
- 支持要素を前記支持フレーム(SR)と並行して共通の工程で形成する工程を更に有し、前記支持要素(SE)は前記支持フレーム内に位置して前記支持フレームと同一の高さを有し、前記素子チップ(BC)の接合の後に、前記支持要素の一部により、前記素子構造体と前記金属接合面との間の電気的接続が前記キャリア基板上に形成されることを特徴とする請求項9ないし21の何れか1項に記載の方法。
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DE102004020204A1 (de) * | 2004-04-22 | 2005-11-10 | Epcos Ag | Verkapseltes elektrisches Bauelement und Verfahren zur Herstellung |
JP3998658B2 (ja) * | 2004-04-28 | 2007-10-31 | 富士通メディアデバイス株式会社 | 弾性波デバイスおよびパッケージ基板 |
JP4095049B2 (ja) * | 2004-08-30 | 2008-06-04 | シャープ株式会社 | 電極気密封止を用いた高信頼性半導体装置 |
US7545029B2 (en) * | 2006-08-18 | 2009-06-09 | Tessera, Inc. | Stack microelectronic assemblies |
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US20090071710A1 (en) | 2009-03-19 |
DE102006025162B3 (de) | 2008-01-31 |
JP2009539235A (ja) | 2009-11-12 |
US7673386B2 (en) | 2010-03-09 |
WO2007137568A1 (de) | 2007-12-06 |
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