WO2007122769A1 - ディスプレイコントローラ、グラフィックスプロセッサ、描画処理装置および描画制御方法 - Google Patents
ディスプレイコントローラ、グラフィックスプロセッサ、描画処理装置および描画制御方法 Download PDFInfo
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- WO2007122769A1 WO2007122769A1 PCT/JP2006/323950 JP2006323950W WO2007122769A1 WO 2007122769 A1 WO2007122769 A1 WO 2007122769A1 JP 2006323950 W JP2006323950 W JP 2006323950W WO 2007122769 A1 WO2007122769 A1 WO 2007122769A1
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- buffer
- frame buffer
- frame
- drawing data
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Classifications
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/399—Control of the bit-mapped memory using two or more bit-mapped memories, the operations of which are switched in time, e.g. ping-pong buffers
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2340/00—Aspects of display data processing
- G09G2340/04—Changes in size, position or resolution of an image
- G09G2340/0407—Resolution change, inclusive of the use of different resolutions for different screen areas
- G09G2340/0435—Change or adaptation of the frame rate of the video stream
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N5/00—Details of television systems
- H04N5/44—Receiver circuitry for the reception of television signals according to analogue transmission standards
- H04N5/46—Receiver circuitry for the reception of television signals according to analogue transmission standards for receiving on more than one standard at will
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- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0117—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level involving conversion of the spatial resolution of the incoming video signal
- H04N7/012—Conversion between an interlaced and a progressive signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N7/00—Television systems
- H04N7/01—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level
- H04N7/0127—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter
- H04N7/0132—Conversion of standards, e.g. involving analogue television standards or digital television standards processed at pixel level by changing the field or frame frequency of the incoming video signal, e.g. frame rate converter the field or frame frequency of the incoming video signal being multiplied by a positive integer, e.g. for flicker reduction
Definitions
- the present invention relates to a drawing processing technique, and more particularly to a display controller, a graphics processor, a drawing processing apparatus, and a drawing control method for generating image data suitable for a display.
- the image signal is matched with the display device specifications by converting the horizontal frequency or vertical frequency of the image signal.
- a display controller that has the function of a converter that converts the data into a video is required.
- displayable image signal specifications such as frame rate and resolution
- the display controller converts the image signal according to the specifications of the output display device.
- the vertical sync signal of an NTSC TV is 59.97Hz
- the vertical sync signal of a PAL TV is 50Hz
- the video provided by the NTSC system is displayed on a PAL TV.
- conversion processing is performed to adapt the frame rate of the video to the PAL method.
- each frame of the movie is created at 59.97 Hz from the beginning, so there is a problem if it is displayed on a display with a different vertical synchronization frequency. Occurs and the playback quality of the moving image deteriorates.
- the present invention has been made in view of these problems, and an object of the present invention is to provide a drawing processing technique for displaying a moving image on display devices having different synchronization frequencies.
- a display controller sequentially switches and selects a plurality of frame buffers in which drawing data is held in units of frames, and scans the selected frame buffer.
- the display controller supplies the drawing data read out to the display, and switches the frame buffer at a frequency different from the vertical synchronization frequency of the display.
- the frequency for switching the frame buffer may be a vertical synchronization frequency assumed when the graphics processor generates the drawing data in units of frames.
- the buffer switching signal generated at the assumed vertical synchronization frequency may be received from the graphics processor, and the switching timing of the frame buffer may be controlled by the buffer switching signal.
- Another aspect of the present invention is a graphics processor.
- This graphics processor sequentially switches and selects a plurality of frame buffers in which drawing data is held in units of frames, scans the selected frame buffer, and supplies the drawing data read out to the display controller.
- a graphics processor for providing a buffer switching signal for giving a switching timing of the frame buffer, wherein the graphics processor has a vertical synchronization frequency assumed when the graphics processor generates the drawing data in units of frames. A switching signal is generated.
- Yet another embodiment of the present invention is a drawing processing apparatus.
- the apparatus sequentially switches between the plurality of frame buffers for holding drawing data in units of frames and the plurality of frame buffers, and selects the frame buffer to which the drawing data is to be written.
- a drawing processing unit that generates the drawing data in a frame buffer and a plurality of frame buffers are sequentially switched to select a frame buffer from which the drawing data is read, and the selected reading destination frame buffer is scanned.
- a display controller for supplying the drawing data to be read to the display, and a command for instructing the display controller to switch the frame buffer of the reading destination.
- a switching signal generation unit that generates a buffer switching signal. The switching signal generation unit generates the buffer switching signal at a frequency different from the vertical synchronization frequency of the display.
- Yet another embodiment of the present invention is also a drawing processing apparatus.
- the apparatus sequentially switches between a plurality of frame buffers that hold drawing data in units of frames and the plurality of frame buffers, and selects a writing destination frame buffer for the drawing data.
- a drawing processing unit that generates drawing data, and a plurality of frame buffers that are sequentially switched to select a reading-out frame buffer of the drawing data, and the drawing that is read out by scanning the selected reading-destination frame buffer
- a display controller that supplies data to the display; and a switching signal generation unit that generates a buffer switching signal for instructing the display controller to switch a frame buffer to be read out.
- the switching signal generation unit determines whether or not a vertical synchronization frequency assumed when the drawing processing unit generates the drawing data in units of frames and an actual vertical synchronization frequency of the display match. If not, the buffer switching signal is generated at the assumed vertical synchronization frequency, and if they match, the buffer switching signal is generated at the actual vertical synchronization frequency of the display.
- Yet another embodiment of the present invention is a drawing control method.
- a plurality of frame buffers in which drawing data is held in units of frames are sequentially switched and selected, and the drawing data read by scanning the selected frame buffer is supplied to a display controller.
- the switching timing of the frame buffer scanned by the display controller is controlled by a noffer switching signal generated at a frequency different from the vertical synchronization frequency of the display.
- FIG. 1 is a configuration diagram of a drawing processing apparatus according to an embodiment.
- FIG. 2 is a diagram for explaining a buffer switching signal generated by the switching signal generation unit in FIG. 1.
- FIG. 3A is a diagram for explaining a display control operation in the case where the vertical synchronization frequency of the display matches the vertical synchronization frequency assumed by the graphics processor.
- FIG. 3B is a diagram for explaining the display control operation when the vertical synchronization frequency of the display and the vertical synchronization frequency assumed by the graphics processor match.
- FIG. 3C is a diagram for explaining the display control operation when the vertical synchronization frequency of the display and the vertical synchronization frequency assumed by the graphics processor match.
- FIG. 4A is a diagram illustrating a display control operation when the vertical synchronization frequency of the display and the vertical synchronization frequency assumed by the graphics processor do not match.
- FIG. 4B is a diagram for explaining the display control operation when the vertical synchronization frequency of the display and the vertical synchronization frequency assumed by the graphics processor do not match.
- FIG. 4C is a diagram for explaining the display control operation when the vertical synchronization frequency of the display and the vertical synchronization frequency assumed by the graphics processor do not match.
- FIG. 4D is a diagram for explaining the display control operation when the vertical synchronization frequency of the display does not match the vertical synchronization frequency assumed by the graphics processor.
- FIG. 5 is a sequence diagram for explaining the display control operation of FIGS. 4A to 4D.
- FIG. 6 is a diagram for explaining an example of application to frame rate rendering.
- 10 main processor 20 main memory, 30 graphics processor, 32 drawing processing unit, 36 switching signal generation unit, 40 local memory, 44 frame buffer, 50 display controller, 60 display, 80 communication unit, 100 drawing processing apparatus.
- FIG. 1 is a configuration diagram of a drawing processing apparatus 100 according to the embodiment.
- the rendering processing apparatus 100 performs rendering processing for generating rendering data to be displayed on the screen based on the 3D model information of the object to be rendered (hereinafter simply referred to as “object”).
- object 3D model information of the object to be rendered
- This figure is a block diagram that focuses on the functions, and these functional blocks can be realized in various forms by using hardware only, software only, or combining them.
- the drawing processing apparatus 100 includes a main processor 10, a main memory 20, a graphics processor 30, a local memory 40, a display controller 50, a display 60, and a communication unit 80. These are connected to the bus, not shown.
- the main memory 20 is a storage area mainly used by the main processor 10, and stores vertex data and control parameters of the object.
- the main processor 10 performs an object geometry calculation process and the like, and generates a drawing command for instructing the graphics processor 30 to draw the object.
- the local memory 40 is a storage area mainly used by the graphics processor 30, and stores a shader program for executing a drawing algorithm, a texture to be pasted on the surface of an object, and the like.
- the local memory 40 is provided with a frame buffer for holding intermediate results and final results of drawing data.
- the graphics processor 30 renders an object to generate drawing data, and stores the drawing data in the local memory 40.
- the graphics processor 30 includes a drawing processor 32 and a switching signal generator 36.
- the drawing processing unit 32 performs various drawing calculation processes such as shading and texture mapping on the object according to the drawing command instructed from the main processor 10, and draws the drawing data in the frame buffer in the local memory 40. Write to 44.
- the drawing processing unit 32 includes functional blocks such as a rasterizer, a shader unit, and a texture unit (not shown).
- the frame buffer 44 is composed of a multi-buffer such as a double buffer or a triple buffer so that drawing data can be written and read independently, and is different from the buffer being read by the display controller 50.
- the drawing data for the next frame is written to the buffer.
- the display controller 50 sequentially shifts the frame buffer 44 composed of multiple buffers according to the actual vertical synchronization frequency (also called “refresh rate”) of the display 60 or the vertical synchronization frequency assumed by the graphics processor 30. Switch to the next scan.
- the display controller 50 generates a vertical synchronizing signal (VSYNC; vertical synchronizing signal) in accordance with the vertical synchronizing frequency of the display 60, and supplies the vertical synchronizing signal to the switching signal generator 36 of the graphics processor 30.
- VSYNC vertical synchronizing signal
- the switching signal generator 36 receives the vertical synchronization signal of the display 60 from the display controller 50, generates a buffer switching signal for instructing the switching timing of the frame buffer 44 composed of multiple buffers, and displays the display controller. Give to 50.
- the switching signal generation unit 36 matches the actual vertical synchronization frequency of the display 60 with the vertical synchronization frequency assumed when the graphic status processor 30 generates the drawing data in units of frames. If they match, a buffer switching signal is generated at the actual vertical synchronization frequency of the display 60. When the actual vertical synchronization frequency of the display 60 is different from the vertical synchronization frequency assumed by the graphics processor 30, the switching signal generator 36 assumes the Dallas processor 30 that does not match the actual vertical synchronization frequency of the display 60. Generate buffer switching signal at vertical synchronization frequency
- the display controller 50 switches and selects the frame buffer 44 composed of multi-buffers at the timing of the buffer switching signal given from the switching signal generator 36, and scans the selected buffer to obtain drawing data. read out.
- the scanning operation of the frame buffer 44 by the display controller 50 will be described in more detail.
- the display controller 50 sequentially reads pixel data of drawing data from the frame buffer 44 in the form of lines. That is, the display controller 50 scans from the upper left corner pixel of the frame buffer 44 in the horizontal direction, and reads out the first horizontal row of pixel data. Next, move one pixel in the vertical direction and read the next row of pixels. When scanning is completed up to the bottom pixel row, the same scan is performed again from the top pixel row.
- the switching signal generator 36 buffers the buffer at the actual vertical synchronization frequency of the display 60 or the vertical synchronization frequency assumed by the graphics processor 30.
- Switching signal to display controller 50 The display controller 50 controls to switch the frame buffer for scanning the drawing data.
- the display controller 50 suspends the reading of the pixel column from the first frame buffer that has been scanned until the timing when the switching signal is received from the switching signal generator 36, and the first frame buffer power is also the second frame buffer power. Switch to the frame buffer, and the second frame buffer also reads the next pixel column.
- the display controller 50 converts the display image data having the RGB color value read out from the frame buffer 44 in this way into an image signal having a format corresponding to the display 60 and supplies the image signal to the display 60.
- the graphics processor 30 and the main processor 10 are connected via an input / output interface (not shown), and the graphics processor 30 can access the main memory 20 via the input / output interface. Conversely, the main processor 10 can access the local memory 40 via the input / output interface.
- the communication unit 80 can transmit and receive data via a network in accordance with a command from the main processor 10. Data transmitted and received by the communication unit 80 is held in the main memory 20.
- FIG. 2 is a diagram for explaining a buffer switching signal generated by the switching signal generation unit 36.
- the frame buffer 44 is configured as a double buffer here as an example, and includes a first frame buffer 44a and a second frame buffer 44b.
- the switching unit 74 on the input side of the frame buffer 44 selects either the first frame buffer 44a or the second frame buffer 44b to which the drawing processing unit 32 writes the drawing data.
- the input side switching unit 74 switches the drawing data writing destination from the drawing processing unit 32 to the other frame buffer. As a result, the drawing data of the next frame is written into the other frame buffer.
- the switching unit 76 on the output side of the frame buffer 44 selects either the first frame buffer 44a or the second frame buffer 44b to which the display controller 50 reads image data.
- the display controller 50 gives a vertical synchronization signal to the switching signal generator 36, and the switching signal
- the signal generation unit 36 generates a buffer switching signal for switching the frame buffer, and provides it to the input side switching unit 74 and the output side switching unit 76 of the frame buffer 44.
- the switching unit 74 on the input side of the frame buffer 44 changes the drawing data writing destination by the drawing processing unit 32 from the current writing destination frame buffer to the other in accordance with the buffer switching signal from the switching signal generating unit 36. Switch to the frame buffer.
- the switching unit 76 on the output side of the frame buffer 44 determines whether the display controller 50 is currently reading the drawing data reading destination, and the frame buffer power currently being read is the other frame. Switch to buffer. As a result, subsequent scanning by the display controller 50 is performed on the other frame buffer.
- the switching signal generator 36 sets the vertical synchronization frequency assumed by the graphics processor 30 to the vertical synchronization frequency. To generate a buffer switching signal.
- the buffer switching signal generated at the vertical synchronization frequency assumed by the graphics processor 30 is called “dummy single vertical synchronization signal (dummy VSYNC)”, and the vertical synchronization generated by the display controller 50 at the vertical synchronization frequency of the display 60 The signal is called the “original vertical sync signal (original VSYNC)”.
- the vertical synchronization frequency of the display 60 is 50 Hz and the vertical synchronization frequency assumed by the graphics processor 30 is 60 Hz.
- the display controller 50 supplies the original vertical synchronization signal to the switching signal generation unit 36 at the vertical synchronization frequency of 50 Hz of the display 60.
- the switching signal generation unit 36 is a dummy at the vertical synchronization frequency 60 Hz assumed by the graphics processor 30.
- a vertical synchronization signal is generated.
- the drawing processing unit 32 generates the drawing data for one frame in the frame buffer while switching the first frame buffer 44a and the second frame buffer 44b at the timing of the dummy vertical synchronization signal, that is, every 1Z60 seconds.
- 50 is also referred to by switching the first frame buffer 44a and the second frame buffer 44b every 1Z60 seconds, ie, the timing of the dummy vertical synchronizing signal.
- the display controller 50 is the vertical assumed by the graphics processor 30. At the sync frequency of 60 Hz, the drawing data readout destination is simply switched between the first frame buffer 44 a and the second frame buffer 44 b, and the actual vertical sync frequency of the display 60 is 50 Hz. Note that there is no change in scanning one screen. In other words, the display controller 50 reads the drawing data while switching the destination frame buffer every 1 Z 60 seconds in accordance with the vertical synchronization frequency assumed by the graphics processor 30, and matches the actual vertical synchronization frequency of the display 60. One frame of drawing data is supplied to the display 60 every 1Z50 seconds.
- FIGS. 3A to 3C the display control operation when the actual vertical synchronization frequency of the display 60 and the vertical synchronization frequency assumed by the graphics processor 30 match will be described, and then FIGS. 4A to 4D will be described.
- the display control operation when the actual vertical synchronization frequency of the display 60 and the vertical synchronization frequency assumed by the graphics processor 30 do not match will be described.
- the switching signal generator 36 receives the original vertical synchronization signal from the display controller 50. Since the vertical synchronization frequency of the display 60 and the vertical synchronization frequency assumed by the graphics processor 30 match, the switching signal generation unit 36 generates a buffer switching signal at the vertical synchronization frequency of the display 60, and the frame buffer 44 This is given to the switching unit 74 on the input side and the switching unit 76 on the output side.
- the display controller 50 Upon receiving this nota switch signal, the display controller 50 switches the read destination to the first frame buffer 44a, and the frame image held in the first frame buffer 44a (this is referred to as the "first frame image"). Is read to the last line force and displayed on the display 60.
- the drawing processing unit 32 switches the writing destination to the second frame buffer 44b, and while the display controller 50 reads the frame image from the first frame buffer 44a, the second frame image is transferred to the second frame buffer 4b. Write to 4b.
- FIG. 3B shows the operation at the generation timing of the second buffer switching signal.
- the switching signal generation unit 36 gives a second buffer switching signal to the input side switching unit 74 and the output side switching unit 76 of the frame buffer 44 to switch the input / output path of the frame buffer 44.
- the display controller 50 displays the second frame image held in the second frame buffer 44b from the first line to the last line. Read and display on display 60.
- the drawing processing unit 32 writes the third frame image to the first frame buffer 44a while the display controller 50 reads the second frame image from the second frame buffer 44b.
- FIG. 3C shows the operation at the generation timing of the third buffer switching signal.
- the switching signal generation unit 36 gives a third buffer switching signal to the input side switching unit 74 and the output side switching unit 76 of the frame buffer 44 to switch the input / output path of the frame buffer 44.
- the display controller 50 Upon receiving the switching operation at the timing of the third buffer switching signal, the display controller 50 displays the third frame image held in the first frame buffer 44a from the first line to the last line. Read and display on display 60. On the other hand, the drawing processing unit 32 writes the fourth frame image to the second frame buffer 44b while the display controller 50 reads the third frame image from the first frame buffer 44a.
- the switching signal generation unit 36 may display the display controller. Generate a buffer switching signal at the vertical synchronization frequency supplied from 50 and switch the input / output path of the frame buffer 44.
- the switching signal generator 36 receives the supply of the original vertical synchronization signal from the display controller 50. Since the vertical sync frequency of the display 60 and the vertical sync frequency assumed by the graphics processor 30 do not match, the switching signal generator 36 generates a dummy vertical sync signal at the vertical sync frequency assumed by the graphics processor 30.
- the buffer switching signal is supplied to the switching unit 74 on the input side and the switching unit 76 on the output side of the frame buffer 44.
- FIG. 4A shows an operation from when the first dummy vertical synchronization signal is given from the switching signal generator 36 to when the second dummy vertical synchronization signal is given.
- the display controller 50 sequentially scans the first frame image held in the first frame buffer 44a from the first line and displays it on the display 60.
- the scan line immediately before the second dummy vertical synchronization signal is given from the switching signal generator 36 is indicated by a dotted line (reference numeral 200). This scan line is called the “buffer switching line” because the buffer at the read destination switches this scan line power
- the display 60 displays the first line image of the first frame image held in the first frame buffer 44a.
- the area up to the first buffer switching line 200 (the part indicated by A in the figure) is displayed.
- the drawing processing unit 32 writes the second frame image in the second frame buffer 44b while the display controller 50 reads the first frame image from the first frame buffer 44a.
- FIG. 4B shows an operation after the second dummy vertical synchronization signal is generated from the switching signal generation unit 36.
- the switching signal generation unit 36 gives a dummy vertical synchronization signal to the switching units 74 and 76
- the reading destination of the display controller 50 is switched to the second frame buffer 44b
- the writing destination of the drawing processing unit 32 is the first frame buffer. Switch to 44a
- the display controller 50 scans the second frame image held in the second frame buffer 44b from the buffer switching line 200 to the last line (the portion indicated by B1 in the figure). , Display on display 60.
- the drawing processing unit 32 writes the third frame image to the first frame buffer 44a while the display controller 50 reads the frame image from the second frame buffer 44b.
- the second frame image held in the second frame buffer 44b is scanned up to the last line, and when the display 60 finishes displaying the last line on the screen, This is the timing at which the original vertical synchronization signal is generated from the spray controller 50.
- FIG. 4C shows the operation after the display controller 50 generates the original vertical synchronization signal.
- the display controller 50 When the second frame image held in the second frame buffer 44b scans to the last line, the display controller 50 then returns to the first line of the second frame image and starts scanning.
- the display controller 50 sequentially scans the second frame images held in the second frame buffer 44b from the first line and displays them on the display 60.
- the switching signal generator 36 When scanning is completed up to the dotted line (reference numeral 202) (second buffer switching line) of the second frame image, the switching signal generator 36 generates the third dummy vertical synchronization signal.
- FIG. 4D shows an operation after the third dummy vertical synchronization signal is generated from the switching signal generation unit 36.
- the third dummy vertical synchronization signal By the third dummy vertical synchronization signal, the reading destination of the display controller 50 is switched to the first frame buffer 44a, and the writing destination of the drawing processing unit 32 is switched to the second frame buffer 44b.
- the display controller 50 displays the third frame image held in the first frame buffer 44a from the second buffer switching line 202 to the third buffer switching line 204 (indicated by C in the figure). Part) is scanned and displayed on display 60. On the other hand, the drawing processing unit 32 writes the fourth frame image into the second frame buffer 44b while the display controller 50 reads out the frame image from the first frame buffer 44a.
- FIG. 5 is a sequence diagram for explaining the display control operation of FIGS. 4A to 4D.
- the actual vertical synchronization frequency of the display 60 is illustrated as 50 Hz
- the vertical synchronization frequency assumed by the graphics processor 30 is illustrated as 60 Hz.
- a dummy vertical synchronizing signal of 60 Hz and an original vertical synchronizing signal of 50 Hz are shown.
- the 0th to 4th dummy vertical synchronization signals are generated.
- the first and second original vertical sync signals are generated.
- the first dummy vertical sync signal generation time tl and the first The final vertical synchronization signal Tl is assumed to be at the same time.
- the drawing processing unit 32 writes the first to fourth frame images while switching between the first frame buffer 44a and the second frame buffer 44b with a dummy vertical synchronization signal of 60 Hz.
- the display controller 50 reads the drawing data while switching between the first frame buffer 44a and the second frame buffer 44b at the timing when the dummy vertical synchronization signal of 60 Hz is generated. For example, the drawing data is read from the first frame buffer 44a until the time tl force is t2, and switched to the second frame buffer 44b at the time t2, and the second frame buffer 44b is switched to the time t2 force until the t3. Read the drawing data.
- the frame buffer to be read is switched at the generation timing of the dummy vertical synchronization signal.
- the read destination is switched from the first frame buffer 44a to the second frame buffer 44b at time t2, and the read destination is switched from the second frame buffer 44b to the first frame buffer 44a at time t3.
- the display controller 50 completes scanning up to the last line of the screen at the generation timing of the original vertical synchronizing signal, switches the screen, returns to the first line of the screen, and starts scanning. In the figure, at the time T2, the last line of the screen is reached, the screen switches, and scanning starts again from the first line.
- the first dummy vertical synchronization signal generation time tl to the second dummy vertical synchronization signal generation time t2 correspond to FIG. 4A, and the display controller 50 controls the first frame from the first frame buffer 44a to the first frame. Data in area A of the image is read and displayed in the area from the first line of the display 60 to the buffer switching line. At the time t2 when the second dummy vertical synchronization signal is generated, the read-out frame buffer is switched from the first frame buffer 44a to the second frame buffer 44b.
- the display controller 50 causes the second frame buffer 44b to generate the second frame image.
- the data in area B1 is read, and the previous buffer switching line force on the screen of display 60 is also displayed in the area up to the last line.
- the screen of the display 60 is switched and scanning of the first line force starts.
- the second original vertical synchronization signal generation time T2 to the third dummy vertical synchronization signal generation time t3 correspond to FIG. 4C.
- the display controller 50 causes the second frame buffer 44b to generate the second frame image.
- the data in area B2 is read and displayed in the area from the top line of the display 60 screen to the buffer switching line.
- the read frame buffer switches from the second frame buffer 44b to the first frame buffer 44a.
- the display controller 50 has a vertical synchronization frequency assumed when the graphics processor 30 draws a frame, which is not the actual vertical synchronization frequency of the display 60. Switch the frame buffer to which drawing data is read. This allows the video to be displayed on a display 60 with a different vertical synchronization frequency without ignoring the frame rate of the video drawn by the graphics processor 30, and the unnaturalness associated with the frequency conversion that occurs in the played video. Can be minimized.
- the graphics processor 30 that does not need to change the frame rate at the time of drawing in accordance with the vertical synchronization frequency of the display 60 may be drawn assuming a standard vertical synchronization frequency. This eliminates the need for a converter to convert the display 60 to the vertical synchronization frequency.
- FIG. 6 is a diagram for explaining an application example to high frame rate rendering.
- the drawing processing unit 32 generates drawing data with a high frame rate at 240 Hz.
- Display 60 has a 60 Hz vertical sync frequency.
- the switching signal generator 36 receives the 60 Hz original vertical synchronizing signal from the display controller 50 and provides the 240 Hz dummy vertical synchronizing signal to the switching units 74 and 76.
- the drawing processing unit 32 writes the drawing data for one frame in each of the frame buffers 44a to 44d while sequentially switching the four frame buffers 44a to 44d at 240 Hz.
- the display controller 50 sequentially switches the four frame buffers 44a to 44d at 240Hz, while drawing data A from the first line of the first frame buffer 44a to the first buffer switching line 210 and the second frame buffer 44b.
- Drawing data B from the first buffer switching line 210 to the second buffer switching line 212
- drawing data C from the second buffer switching line 212 to the third buffer switching line 214 of the third frame buffer 44c
- fourth frame buffer The drawing data D from the third buffer switching line 214 of 44d to the last line is read out and displayed side by side in one screen of the display 60 that switches at 60Hz.
- the present invention can be used in the field of drawing processing.
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CN2006800542884A CN101427300B (zh) | 2006-04-19 | 2006-11-30 | 显示器控制器、图形处理器、描绘处理装置及描绘控制方法 |
US12/297,546 US8026919B2 (en) | 2006-04-19 | 2006-11-30 | Display controller, graphics processor, rendering processing apparatus, and rendering control method |
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JP2006-116069 | 2006-04-19 | ||
JP2006116069A JP4327173B2 (ja) | 2006-04-19 | 2006-04-19 | グラフィックスプロセッサ、描画処理装置および描画制御方法 |
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JP5255196B2 (ja) * | 2006-10-19 | 2013-08-07 | 任天堂株式会社 | ゲーム機、無線モジュール、ゲームシステムおよびゲーム処理方法 |
US8040334B2 (en) * | 2006-12-29 | 2011-10-18 | 02Micro International Limited | Method of driving display device |
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US8026919B2 (en) | 2011-09-27 |
JP4327173B2 (ja) | 2009-09-09 |
JP2007286519A (ja) | 2007-11-01 |
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