Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W74/00—Encapsulations, e.g. protective coatings
  • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
  • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
  • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/01—Manufacture or treatment
  • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
  • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
  • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W20/00—Interconnections in chips, wafers or substrates
  • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
  • H10W20/211—Through-semiconductor vias, e.g. TSVs
  • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
  • H10W20/2125—Top-view shapes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/01—Manufacture or treatment
  • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
  • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
  • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
  • H10W70/69—Insulating materials thereof
  • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
  • H10W72/251—Materials
  • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/921—Structures or relative sizes of bond pads
  • H10W72/922—Bond pads being integral with underlying chip-level interconnections
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/921—Structures or relative sizes of bond pads
  • H10W72/923—Bond pads having multiple stacked layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/941—Dispositions of bond pads
  • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/941—Dispositions of bond pads
  • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/90—Bond pads, in general
  • H10W72/951—Materials of bond pads
  • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
• • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
  • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
  • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
  • Y10T29/00—Metal working
  • Y10T29/49—Method of mechanical manufacture
  • Y10T29/49002—Electrical device making
  • Y10T29/49117—Conductor or circuit manufacturing
  • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
  • Y10T29/49155—Manufacturing circuit on or in base
  • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

Definitions

• the present invention relates to the production of electrical feedthroughs by non- or semiconducting substrates, in particular for IC-compatible substrates, and thus the production of substrates or electrical / electronic components containing such feedthroughs. Furthermore, the invention relates to the corresponding substrates or components themselves.
• the object of the present invention is to eliminate the disadvantages mentioned and to provide a process which can be carried out with relatively few steps and thus is cost-effective for realizing feedthroughs through a non-conductive or semiconductive substrate.
• both stacked chip structures such as those required for example as MEMS-CSP, Opto-CSP or the like for measuring rotation rates, accelerations etc., as well as individual components such as CCD, CMOS or BICMOS image sensors (camera chips) can be produced.
• the MEMS-CSP and Opto-CSP with vertical electrical feedthroughs can be equipped with SMT mounters very simply, but with high precision and enable the realization of smallest assemblies at low cost.
• Figure 2 shows the via on the example of an image sensor.
• Suitable substrate materials are semiconductors such as silicon wafers, but also other non-conductive substrate materials such as GaAs, glass, pyrex and ceramics; the method is in principle not limited in this respect.
• Process control and process parameters that do not change pre-processed components (eg at wafer level) in their functional properties.
• all steps can be carried out at temperatures below 400 ° C., more preferably even below 200 ° C., which makes use of the method also suitable for the production of color camera image sensors.
• the method according to the invention is directed to the production of integrated circuit systems, it is easy to use IC-compatible auxiliaries and materials for this purpose. Special processes in lithography are avoided by having open perforations in the semiconductor substrate at no time.
• the method is applicable both to uncoated substrates and to substrates whose surfaces are covered on one or both sides with a coating, for example a passivation.
• a coating for example a passivation.
• An example of this is a silicon wafer covered with a thin SiO 2 layer.
• Step (b) of the method the formation of at least one recess in the substrate from its rear side, preferably takes place by means of an etching process.
• recesses are etched into the substrate via a lithographically produced mask on the back of the substrate.
• the mask may be placed on the substrate so that it can later be removed or otherwise removed; but it can also consist of a material that adheres to the substrate, for example, a resistant to the etching medium paint or aluminum layer or a Si ⁇ 2 layer ("hard mask”) be. This can, but does not have to, remain below on the substrate.
• the etching may be a plasma etching process using a suitable gas mixture.
• This may, for example, contain an oxidizing sulfur hexafluoride if the substrate is a silicon wafer.
• silicon can be treated by means of the so-called "deep reactive etching" (DRIE). Such etching processes attack silicon, but not SiO 2 , aluminum or paints.
• the recess can be generated mechanically, for example by removing UV laser irradiation.
• the depressions obtained according to step (b) can have any diameter. Often one will aim for diameters of about 10 to 250 microns, preferably 20 to 100 microns, with a thickness of the substrate of preferably 35 to 500 microns.
• the recesses receive a cone-like shape, in which the cross-section of the recesses decreases in the direction of the front side of the substrate.
• the flanks of this recess are much more accessible in later coating operations and allow a more even support of material as a via-like implementation with the same diameter. They preferably have a flank angle of about 90 ° -70 °, preferably 85 ° -75 ° and most preferably of about 80 °.
• the recesses may, but need not, be uniform or symmetrical.
• the cone-like shape of the recesses may extend over the entire thickness of the substrate; instead, however, one can also work with a so-called "undercut” in which the hole diameter widens only shortly behind the rear outer surface to its maximum diameter and then conically constricted.
• a flank structure can be obtained, for example, by etching according to the Bosch method (alternating application of etching gas, eg SF 6 , and a gas which is suitable for a
• Passivation by plasma polymerization can provide, for example, C 4 Fs) or using a dry etching process with SF 6 / ⁇ 2 achieve as a mixed gas, wherein Si ⁇ 2 forms as an inorganic sidewall passivation.
• ions and radicals are produced in the process gas.
• the ions are directed onto the wafer by means of a bias voltage and, as a result of their sputtering effect, impinge the passivation layer on the bottom of the hole when they strike, where they react with silicon to form gaseous SiF. Accordingly, very few ions strike the sidewalls. If you now turn off the bias and etched primarily with the neutral particles in the already exposed area, which optionally increases the proportion of neutral particles by increasing the working gas pressure, you can influence the formation of sidewall passivation. This can additionally be done by the duration of the passivation. An unclosed sidewall passivation is vulnerable to the neutral particles, resulting in an outward caustic effect.
• the ratio of directional ionic etching (by different bias) to sidewall passivation thickness at the same working gas pressure By controlling the ratio of directional ionic etching (by different bias) to sidewall passivation thickness at the same working gas pressure, one can thus determine the formation of a hole angle.
• the conditions of the etching process are chosen such that the electrically conductive contact point located on the front side of the substrate is exposed from the rear side, but not attacked. When the pad is exposed, the etching process is stopped by its very low removal rate on this material. The contact point covers the formed depression towards the front in such a way that the substrate remains gas-tight.
• the contact points themselves are designed according to the requirements of the later component. They will usually consist of a suitable metal, e.g. was sputtered or evaporated. It may or may not be wire bonding surfaces. A particularly preferred variant of the formation of contact points will be described below.
• the conductive structure may then be applied directly to the substrate according to step (c).
• semiconductor chips which are intended for special cases such as high power amplifiers for mobile phones.
• a better potential matching to earth and at the same time a better cooling of the chip can be obtained.
• this procedure is also suitable in all cases in which the substrate is a non-conductor.
• the conductive structure of step (c) may be prepared by conventional techniques, e.g. physical sputtering, vapor deposition, electroplating or electroless plating from solutions. It can be one or more layers. Suitable materials for this are e.g. Metals such as titanium, chromium, tungsten, TiN, aluminum, nickel, gold, silver or copper or alloys containing these metals. Suitable multilayer metallizations are e.g. Ti / Ni / Ag, TiW / Gold, Cr / Cu / Au, Al / NiV / Cu or Ti / TiN / Cu.
• a continuous layer is produced, it can then be structured by conventional methods, such as preferably spin-on or dry-resist lithography and wet etching, but also by dry etching or lift-off technology.
• both the metallization around the bushings around as well as tracks and solder pads can be structured simultaneously.
• the solder surfaces can be arranged in a structured manner offset from the bushings or superposed with the bushings. In this case, contact materials are applied directly to the bushing.
• the conductive structure can of course be applied directly in a structured form with the aid of a mask.
• a passivation layer is disposed on the substrate prior to application of the conductive pattern of step (c).
• the substrate is made of silicon, it may for example consist of silicon dioxide, silicon nitride or a silicon nitride.
• the advantage of such passivations is their high temperature resistance.
• an insulating polymer in particular an organic or inorganic-organic polymer, are applied. Also favorable for this are materials which are relatively largely temperature resistant.
• the passivation layer can be applied in any thickness; are low, for example, 0.4-2 microns.
• the passivation layer can be applied in any manner. Also favorable for this purpose are low-temperature plasma or plasma-assisted processes, e.g. in the case that the layer consists of parylene or of SiN.
• the passivation not only covers the recesses in the substrate, but also desired parts or even the entire back of the substrate.
• it can be applied in a structured manner.
• the passivation layer is applied such that it also covers the backs of the front-side contact points, they must be exposed again before the application of the conductive layer according to step (c). This can be done by means of a gas phase etching process. If the metal of the contact site has been oxidized during passivation or has been oxidized for other reasons, it may e.g. be deoxidized by argon ion bombardment again. The subsequently deposited metal layer thus has a small contact resistance and a high current carrying capacity.
• the rear side of the substrate can be covered with a passivation layer partially or completely except for the places (soldering surfaces) and / or sawing streets intended for subsequent contacting.
• This layer preferably consists of benzocyclobutene (BCB) or polyimide (PI).
• BCB benzocyclobutene
• PI polyimide
• other organic polymers but also inorganic-organic or purely inorganic materials such as SiO2 come into question for this purpose.
• the passivation layer can be subsequently structured, eg lithographically, or else be applied in a structured manner, eg via a mask or in a structured printing process.
• solder balls made of a defined solder alloy are optionally applied. This can be done via a solder paste printing process with subsequent remelting and cleaning or by settling preformed solder balls and remelting or by a galvanic deposition of solder material on the exposed solder pads.
• an alternative contact material such as palladium, nickel, gold, copper or the like can be applied, preferably by means of a galvanic deposition.
• the substrate material for the present invention may be one which may be covered on one or even on both sides with a coating, for example a passivation.
• the electrically conductive contact point will optionally be offset on top, but preferably in or below said layer in such, but possibly also other justified cases.
• the front of the substrate may be pre-patterned, e.g. by etching this layer at the desired contact points and by applying the electrically conductive contact material at this point.
• a particularly preferred embodiment of the present invention which is particularly suitable for the contacting of preprocessed semiconductor substrates, therefore provides for such cases as well as for cases where the contact point on the front of the substrate can not or can not be contacted directly from the rear side for other reasons , the additional formation of a contact hole in the form of a recess in the layer structure of the front side in front, such that the recess preferably extends as far as the semiconductor substrate itself. If necessary, this recess is then provided with a passivation layer, before finally a metallization layer is deposited and patterned therein, such that the metallization layer electrically connects the base of the recess formed with the electrically conductive contact point.
• the front side is covered with a mask, for example by applying and structuring a photoresist.
• a mask for example by applying and structuring a photoresist.
• the various methods known in semiconductor production can be used for the etching of the recess, if appropriate also in combination.
• wet structuring with HF-containing acids is possible.
• those methods for the formation of the front-side recess can be used, which are given above for the back side recess.
• the shape of the recess can be chosen arbitrarily. In a preferred embodiment of the invention, like the rear recess of the present invention, it has a flank angle of approximately 90 ° -70 °, preferably 85 ° -75 ° and most preferably of approximately 80 °.
• the recesses may, but need not, be uniform or symmetrical.
• the cone-like shape of the recesses may extend over the entire thickness of the substrate; instead, however, one can also work with a so-called "undercut” in which the hole diameter widens only shortly behind the rear outer surface to its maximum diameter and then conically constricted. However, it is equally preferable if the recess has vertical side walls.
• a passivation layer is optionally applied, for example, preferably of SiO 2, if the substrate is a silicon material.
• This can subsequently be structured via a lithography and a dry etching process, in such a way that both the front-side contact point and a contact window in the recess are open.
• This paint is then removed again.
• At least one metal layer or a metallic layer composite is then applied to the wafer front side.
• the metal layer for example, an aluminum alloy such as AISH, AISHCU O is suitable.
• layer composite one of at least two, but possibly also three or even more layers can be used, selected from adhesion promoter and / or diffusion barrier layers and a highly electrically conductive cover layer.
• layer composites are Ti / TiN / Cu, TiW, / Ni / Au or Ti / Pt / Au.
• These layers can either be sputtered (eg with the aid of PVD) or vapor-deposited or applied by chemical vapor deposition (CVD). Other variants of the method, as known in the art, are possible. In a further process step, this must full-surface metal layer are then patterned, for example by means of a lithographic process.
• dry etching processes may be used for this purpose; At first, however, wet etching processes are used, in successive cover layers also in different etching liquors in succession.
• the lithography mask, usually a paint, is then removed again.
• Structuring is carried out so that, as a result, there is a more or less short or direct electrical connection between the front-side contact point and the recess newly introduced into the front-side substrate structure.
• the recess is preferably metallized somewhat overlapping to the upper edge; but at least there is a conductor track which completely covers the contact window located at the bottom of the recess.
• an additional passivation layer for example of SiO 2 or SiN, can be applied partially or completely to the front surface of the substrate structure by one of the methods described.
• said additional formation of a contact hole in the form of a recess in the layer structure of the front side takes place before the formation of the rear-side recess.
• the rear recess is then attached so as to end toward the front of the substrate under the metal layer that has been inserted into the front recess.
• the substrate remains continuous and thus gas-impermeable, so that it can act as a seal for the opposite side or surface. If there is a passivation layer underneath this metal layer, which is optionally possible as described above, then it must either eliminate the contact window from the outset or else be subsequently removed from the rear side together with the substrate.
• FIG. 3 shows by way of example a substrate with IC processing applied on the front side
• the recessed front side contact is shown, which may be formed by the method described above.
• An optional passivation layer 2 lines the flanks of the recess or the contact hole 1 and, moreover, covers the remaining layer structure 5 of the IC processing with the exception of the contact points 0, but is not present in the contact area of the rear-side contact-making.
• a possibly existing adhesion promoter or diffusion barrier layer above the passivation layer is not shown, therefore, above the passivation layer is the metallization layer 3 covered by a passivation layer 4.
• the metallization 3 connects the contact points 0 to the contact window 6 between the front and back contacts.
• the rear recess is slightly conical; their flanks 14 have a flank angle of 180 ° -ß. Like the front recess 1, it is lined with a passivation layer 8, which, however, eliminates the contact window. There is a metallization layer 9 and a passivation layer 10 thereon. Via the metallization 9, there is contact with a solderable contact surface 11 and a solder contact 12. It should be clear that the back side recess may also have further layers, as above for the front side recess and further explained in the description of the method.

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• Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
• Manufacturing Of Printed Wiring (AREA)

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• 2005
  • 2005-11-09 DE DE102005053494A patent/DE102005053494A1/de not_active Ceased
• 2006
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  • 2006-11-08 JP JP2008539431A patent/JP2009515348A/ja active Pending
  • 2006-11-08 WO PCT/EP2006/068247 patent/WO2007054521A1/de not_active Ceased
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