JP2009515348A - 非導電性または半導電性の基板に導電性ブッシングを製作する方法 - Google Patents

非導電性または半導電性の基板に導電性ブッシングを製作する方法 Download PDF

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JP2009515348A
JP2009515348A JP2008539431A JP2008539431A JP2009515348A JP 2009515348 A JP2009515348 A JP 2009515348A JP 2008539431 A JP2008539431 A JP 2008539431A JP 2008539431 A JP2008539431 A JP 2008539431A JP 2009515348 A JP2009515348 A JP 2009515348A
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substrate
conductive
notch
layer
contact
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JP2009515348A5 (https=
Inventor
ライネルト，ヴォルフガング
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フラウンホーファー・ゲゼルシャフト・ツール・フェルデルング・デア・アンゲヴァンテン・フォルシュング・エー・ファウ
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Publication of JP2009515348A publication Critical patent/JP2009515348A/ja
Publication of JP2009515348A5 publication Critical patent/JP2009515348A5/ja
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/111—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed
    • H10W74/129—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being completely enclosed forming a chip-scale package [CSP]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0234—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes that stop on pads or on electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H10W20/023—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias
    • H10W20/0242—Manufacture or treatment of interconnections within wafers or substrates the interconnections being through-semiconductor vias comprising etching via holes from the back sides of the chips, wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/20—Interconnections within wafers or substrates, e.g. through-silicon vias [TSV]
    • H10W20/211—Through-semiconductor vias, e.g. TSVs
    • H10W20/212—Top-view shapes or dispositions, e.g. top-view layouts of the vias
    • H10W20/2125—Top-view shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/095—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers of vias therein
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/69—Insulating materials thereof
    • H10W70/698—Semiconductor materials that are electrically insulating, e.g. undoped silicon
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/922—Bond pads being integral with underlying chip-level interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/923—Bond pads having multiple stacked layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9415—Dispositions of bond pads relative to the surface, e.g. recessed, protruding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/942—Dispositions of bond pads relative to underlying supporting features, e.g. bond pads, RDLs or vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10T—TECHNICAL SUBJECTS COVERED BY FORMER US CLASSIFICATION
    • Y10T29/00—Metal working
    • Y10T29/49—Method of mechanical manufacture
    • Y10T29/49002—Electrical device making
    • Y10T29/49117—Conductor or circuit manufacturing
    • Y10T29/49124—On flat or curved insulated base, e.g., printed circuit, etc.
    • Y10T29/49155—Manufacturing circuit on or in base
    • Y10T29/49165—Manufacturing circuit on or in base by forming conductive walled aperture in base

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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Manufacturing Of Printed Wiring (AREA)
JP2008539431A 2005-11-09 2006-11-08 非導電性または半導電性の基板に導電性ブッシングを製作する方法 Pending JP2009515348A (ja)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102005053494A DE102005053494A1 (de) 2005-11-09 2005-11-09 Verfahren zum Herstellen elektrisch leitender Durchführungen durch nicht- oder halbleitende Substrate
PCT/EP2006/068247 WO2007054521A1 (de) 2005-11-09 2006-11-08 Verfahren zum herstellen elektrisch leitender durchführungen durch nicht- oder halbleitende substrate

Publications (2)

Publication Number Publication Date
JP2009515348A true JP2009515348A (ja) 2009-04-09
JP2009515348A5 JP2009515348A5 (https=) 2009-11-05

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JP2008539431A Pending JP2009515348A (ja) 2005-11-09 2006-11-08 非導電性または半導電性の基板に導電性ブッシングを製作する方法

Country Status (5)

Country Link
US (1) US7781331B2 (https=)
EP (1) EP1946367B1 (https=)
JP (1) JP2009515348A (https=)
DE (1) DE102005053494A1 (https=)
WO (1) WO2007054521A1 (https=)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009200228A (ja) * 2008-02-21 2009-09-03 Panasonic Corp 基板モジュールおよびその製造方法ならびに電子機器
WO2013176203A1 (ja) * 2012-05-25 2013-11-28 株式会社村田製作所 半導体装置

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5298559B2 (ja) * 2007-06-29 2013-09-25 富士通株式会社 半導体装置及びその製造方法
JP2009021433A (ja) * 2007-07-12 2009-01-29 Fujikura Ltd 配線基板及びその製造方法
US7973416B2 (en) * 2008-05-12 2011-07-05 Texas Instruments Incorporated Thru silicon enabled die stacking scheme
DE102008031836A1 (de) * 2008-07-05 2010-01-21 Deutsche Cell Gmbh Lotkontakt
JP5351164B2 (ja) * 2008-07-28 2013-11-27 株式会社アドバンテスト 半導体装置、プローブウエハおよび製造方法
JP2010251558A (ja) * 2009-04-16 2010-11-04 Toshiba Corp 固体撮像装置
FR2951017A1 (fr) * 2009-10-05 2011-04-08 St Microelectronics Crolles 2 Via de connexion electrique pour substrat de dispositif semi-conducteur
FR2951018A1 (fr) * 2009-10-05 2011-04-08 St Microelectronics Crolles 2 Via de connexion electrique pour substrat de dispositif semi-conducteur
JP2011187754A (ja) * 2010-03-10 2011-09-22 Toshiba Corp 固体撮像装置及びその製造方法
US8946083B2 (en) * 2011-06-24 2015-02-03 Taiwan Semiconductor Manufacturing Company, Ltd. In-situ formation of silicon and tantalum containing barrier
US20150243597A1 (en) * 2014-02-25 2015-08-27 Inotera Memories, Inc. Semiconductor device capable of suppressing warping
US9601354B2 (en) * 2014-08-27 2017-03-21 Nxp Usa, Inc. Semiconductor manufacturing for forming bond pads and seal rings
JP7008828B2 (ja) 2017-12-26 2022-01-25 ポスコ リチウム二次電池用正極活物質、その製造方法、およびこれを含むリチウム二次電池
DE102023101372B3 (de) 2023-01-20 2024-03-28 Audi Aktiengesellschaft Elektronikanordnung, Kraftfahrzeug und Verfahren zum elektrischen Verbinden

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US4726879A (en) * 1986-09-08 1988-02-23 International Business Machines Corporation RIE process for etching silicon isolation trenches and polycides with vertical surfaces
JPH04174539A (ja) * 1990-11-07 1992-06-22 Oki Electric Ind Co Ltd 半導体装置
US6110825A (en) * 1997-11-26 2000-08-29 Stmicroelectronics, S.R.L. Process for forming front-back through contacts in micro-integrated electronic devices
JP2002208655A (ja) * 2000-06-02 2002-07-26 Seiko Epson Corp 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
JP2003332417A (ja) * 2002-05-08 2003-11-21 Toshiba Corp 半導体チップの製造方法
JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法
US6833079B1 (en) * 2000-02-17 2004-12-21 Applied Materials Inc. Method of etching a shaped cavity

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US4097890A (en) * 1976-06-23 1978-06-27 Hewlett-Packard Company Low parasitic capacitance and resistance beamlead semiconductor component and method of manufacture
US4897708A (en) * 1986-07-17 1990-01-30 Laser Dynamics, Inc. Semiconductor wafer array
US5910687A (en) * 1997-01-24 1999-06-08 Chipscale, Inc. Wafer fabrication of die-bottom contacts for electronic devices
JP3724110B2 (ja) * 1997-04-24 2005-12-07 三菱電機株式会社 半導体装置の製造方法
US6300670B1 (en) * 1999-07-26 2001-10-09 Stmicroelectronics, Inc. Backside bus vias
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DE10244077B4 (de) 2002-09-06 2007-03-15 INSTITUT FüR MIKROTECHNIK MAINZ GMBH Verfahren zur Herstellung von Halbleiterbauteilen mit Durchkontaktierung
WO2004064159A1 (ja) 2003-01-15 2004-07-29 Fujitsu Limited 半導体装置及び三次元実装半導体装置、並びに半導体装置の製造方法
TWI249767B (en) 2004-02-17 2006-02-21 Sanyo Electric Co Method for making a semiconductor device
TWI303864B (en) * 2004-10-26 2008-12-01 Sanyo Electric Co Semiconductor device and method for making the same

Patent Citations (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4726879A (en) * 1986-09-08 1988-02-23 International Business Machines Corporation RIE process for etching silicon isolation trenches and polycides with vertical surfaces
JPH04174539A (ja) * 1990-11-07 1992-06-22 Oki Electric Ind Co Ltd 半導体装置
US6110825A (en) * 1997-11-26 2000-08-29 Stmicroelectronics, S.R.L. Process for forming front-back through contacts in micro-integrated electronic devices
US6833079B1 (en) * 2000-02-17 2004-12-21 Applied Materials Inc. Method of etching a shaped cavity
JP2002208655A (ja) * 2000-06-02 2002-07-26 Seiko Epson Corp 半導体装置及びその製造方法、積層型半導体装置、回路基板並びに電子機器
JP2003332417A (ja) * 2002-05-08 2003-11-21 Toshiba Corp 半導体チップの製造方法
JP2004095849A (ja) * 2002-08-30 2004-03-25 Fujikura Ltd 貫通電極付き半導体基板の製造方法、貫通電極付き半導体デバイスの製造方法

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2009200228A (ja) * 2008-02-21 2009-09-03 Panasonic Corp 基板モジュールおよびその製造方法ならびに電子機器
WO2013176203A1 (ja) * 2012-05-25 2013-11-28 株式会社村田製作所 半導体装置

Also Published As

Publication number Publication date
US7781331B2 (en) 2010-08-24
WO2007054521A1 (de) 2007-05-18
US20080233740A1 (en) 2008-09-25
EP1946367B1 (de) 2016-10-26
DE102005053494A1 (de) 2007-05-16
EP1946367A1 (de) 2008-07-23

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